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[174.21.9.133]) by smtp.gmail.com with ESMTPSA id a79-v6sm23094458pfa.124.2018.10.16.15.31.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 15:31:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2bzU8lG8drgMg4KC0ysLIKiccci5Uymtc7dafrI+w/M=; b=MQXXcWpNw4JdkAgDjuilYU3Jm/6tT+Az9pXrnLcr0ava5HpxAL4BjOU6c+X3K135Ev ZnurC5KsOndaQNO4jM3jF+3fnJnNGQTI20AXcgWYGTm6aB3ebog6xjeKnsCIV4qJ/jDK mGf3lD6/dY0P5xTEEYuJjzIeu7wKT+YIIBOZo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2bzU8lG8drgMg4KC0ysLIKiccci5Uymtc7dafrI+w/M=; b=Dh6UP/1yftn6lj0zg9EjtzKv1MRY6pEENbXcuSOUAe6LvoVrgRUjlw/6pdcxOBQ9LM EH+KhEYuZcQ4RXbGKLfADYmw6HYcYaFvOvpDwgrT2Bsbn7mVlN+O4NuomTEnl3zXBJ7w EzCq1zZAw+QsC77VeSrmXH6GDqo0LpgTnhmAWSLADFfxXQYlrti38Bu9Cv2dfAeMfpR4 zfNHmBPf5gY/DZcQYZVh+4NMEQQDLhz9WhbfxcMBTX18W8rVggLFwF08u+mwjcbIgxqD 3MvqoJUJDmYNJ+d1Qoqgrdoh9ULy0n5mDxmbMHHJQOYzp9V6xgY19qASxZ1JsTTyK+bu NZHg== X-Gm-Message-State: ABuFfohGDINuLi7D4HO/2NPonU84c7ULK0oHHJwv0WooM8t6rZyTq9KF N/3iXdtx8axjpFSsGo9RbJ2tuVvWxyY= X-Google-Smtp-Source: ACcGV63xqOeF6ohj4BCPNBpTq0qNbq21XdxG/ZegJdsqd37LMyTBd0CZ4WCWxmwEJ50rg20/SOgg8A== X-Received: by 2002:a65:6295:: with SMTP id f21-v6mr22213943pgv.167.1539729086553; Tue, 16 Oct 2018 15:31:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 15:31:12 -0700 Message-Id: <20181016223115.24100-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016223115.24100-1-richard.henderson@linaro.org> References: <20181016223115.24100-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 5/8] target/arm: Convert jazelle from feature bit to isar1 test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Having V6 alone imply jazelle was wrong for cortex-m0. Change to an assertion for V6 & !M. This was harmless, because the only place we tested ARM_FEATURE_JAZELLE was for 'bxj' in disas_arm(), which is unreachable for M-profile cores. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 +++++- target/arm/cpu.c | 17 ++++++++++++++--- target/arm/translate.c | 2 +- 3 files changed, 20 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a757aecd57..4fdace5de1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1586,7 +1586,6 @@ enum arm_features { ARM_FEATURE_PMU, /* has PMU support */ ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ - ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ ARM_FEATURE_SVE, /* has Scalable Vector Extension */ ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ ARM_FEATURE_M_MAIN, /* M profile Main Extension */ @@ -3153,6 +3152,11 @@ static inline bool isar_feature_arm_div(const ARMISA= Registers *id) return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; } =20 +static inline bool isar_feature_jazelle(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) !=3D 0; +} + static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) !=3D 0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9319f92f1f..8f16e96b6c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -854,8 +854,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error *= *errp) } if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); - set_feature(env, ARM_FEATURE_JAZELLE); if (!arm_feature(env, ARM_FEATURE_M)) { + assert(cpu_isar_feature(jazelle, cpu)); set_feature(env, ARM_FEATURE_AUXCR); } } @@ -1082,11 +1082,16 @@ static void arm926_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); - set_feature(&cpu->env, ARM_FEATURE_JAZELLE); cpu->midr =3D 0x41069265; cpu->reset_fpsid =3D 0x41011090; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00090078; + + /* + * ARMv5 does not have the ID_ISAR registers, but we can still + * set the field to indicate Jazelle support within QEMU. + */ + cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); } =20 static void arm946_initfn(Object *obj) @@ -1112,12 +1117,18 @@ static void arm1026_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_AUXCR); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); - set_feature(&cpu->env, ARM_FEATURE_JAZELLE); cpu->midr =3D 0x4106a262; cpu->reset_fpsid =3D 0x410110a0; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00090078; cpu->reset_auxcr =3D 1; + + /* + * ARMv5 does not have the ID_ISAR registers, but we can still + * set the field to indicate Jazelle support within QEMU. + */ + cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); + { /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0= ,2 */ ARMCPRegInfo ifar =3D { diff --git a/target/arm/translate.c b/target/arm/translate.c index 8b2be71439..e56b5cdff7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -42,7 +42,7 @@ #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) /* currently all emulated v5 cores are also v5TE, so don't bother */ #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5) -#define ENABLE_ARCH_5J arm_dc_feature(s, ARM_FEATURE_JAZELLE) +#define ENABLE_ARCH_5J dc_isar_feature(jazelle, s) #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6) #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K) #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2) --=20 2.17.2