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[174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mNeH2UybqAeBdXYEpo8e4HunbPQRrwwxFmV/1vG0wc0=; b=L8hsWgHPoTn1N+ReG3sdFnB1EP5+woEo6VbD15HtbVc07WhCxoeMQ0R9uQKjZfWTxu ygVCGU6JgYu1OyzEf60WlXaLLv6hJ0B6Bo9VwTD/gWTNVTw3HFQgy7UkiRX0cfEUK6Ef KVY0X2ohP4cM9hZDlp57Pff6IWwoThRm499k8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mNeH2UybqAeBdXYEpo8e4HunbPQRrwwxFmV/1vG0wc0=; b=n3oouBQ/p854TqL/Js7FISV7I8awLfbj44moiH/wsk6h3+VILR35usP/6vSmooWBfJ UFQKrh7PiYxUYu2kgZeU8Mef2PgSjI5/xXeaqVfnikj2gbDhW764lci6LYiA1r4B6T55 zr22OrrWq/1qfkd+FaYL3yBBG3VMtDO4ZxtW3hise87+Kfi38pNw6+jcEuOxRL5q9W4V RiMkCup/yIAyAbXUAa4XidWpftelZHCIxt/WNmAQayXtmC4ESoX50OL0hMzpqdWL8dwS q66n5ZYIaNGGFazW0evTf1khlplm97dFrHOyPh0vYYo17QWVc5ryZyae/cnEbVEgaRyN ubNg== X-Gm-Message-State: ABuFfogcdr5R7czF3l8N8fgS8msP/k+RvydGAz3AoZhwMi1rdpXzI+4f IZ+iWKAZZsYSv6XMt8Qzu0ZfMLtLeWs= X-Google-Smtp-Source: ACcGV607XB/Vnutke6J8J1twtXrW3W6nJn/dsKAoWAIqyX8UlktpVD25ViqiaY+t1aozdeR6yxW3lA== X-Received: by 2002:a62:ce83:: with SMTP id y125-v6mr23119326pfg.201.1539712166064; Tue, 16 Oct 2018 10:49:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:48:58 -0700 Message-Id: <20181016174911.9052-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PULL 08/21] exec: introduce tlb_init X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" Paves the way for the addition of a per-TLB lock. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Message-Id: <20181009174557.16125-4-cota@braap.org> Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 8 ++++++++ accel/tcg/cputlb.c | 4 ++++ exec.c | 1 + 3 files changed, 13 insertions(+) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5f78125582..815e5b1e83 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -99,6 +99,11 @@ void cpu_address_space_init(CPUState *cpu, int asidx, =20 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* cputlb.c */ +/** + * tlb_init - initialize a CPU's TLB + * @cpu: CPU whose TLB should be initialized + */ +void tlb_init(CPUState *cpu); /** * tlb_flush_page: * @cpu: CPU whose TLB should be flushed @@ -258,6 +263,9 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_i= dx, uintptr_t retaddr); #else +static inline void tlb_init(CPUState *cpu) +{ +} static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) { } diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f4702ce91f..502eea2850 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -73,6 +73,10 @@ QEMU_BUILD_BUG_ON(sizeof(target_ulong) > sizeof(run_on_c= pu_data)); QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16); #define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1) =20 +void tlb_init(CPUState *cpu) +{ +} + /* flush_all_helper: run fn across all cpus * * If the wait flag is set then the src cpu's helper will be queued as diff --git a/exec.c b/exec.c index d0821e69aa..4fd831ef06 100644 --- a/exec.c +++ b/exec.c @@ -965,6 +965,7 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) tcg_target_initialized =3D true; cc->tcg_initialize(); } + tlb_init(cpu); =20 #ifndef CONFIG_USER_ONLY if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { --=20 2.17.2