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[174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=co7JbT0NTKhwEIVbXq3uW8PxRjMU/VzANbjq0dvGlrg=; b=bYojRkeB5hPXYmRNZGoaYPvL/25CT6cdfoAIefIoDy0UOzFo/0kCA82/xssUIaZUF3 rT7JJLigJUA0OmonwnbhZUlLlrlgmZ7BrfnkGnAXKA70TfZ3uYBGjgHikXCtRj0JvD7Z gXi/Ln6SJeHphSPYMxkqCAS6YjH8tuSB8Bbbs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=co7JbT0NTKhwEIVbXq3uW8PxRjMU/VzANbjq0dvGlrg=; b=VvNZosTCubdpJXuJ3pQ/lhAW9z3lWl+5cjTABDWr9/9LaVU28TxpyswNvJoRq1ELHo Bd8RSWbIo39hqXvn6GFeTSCN21fM/Z0JEJHx9vb0BMlF1pUzuFiPy/cPahECH9siepdf 3JdifT5Pfzjpa19/cPo+xeb4ccEM38/QXWzDRbOT1ZR6f/tt6sYN8G0LQgEcY2OEgSuz 1/RuyVCV9bORdaZ+qKgM7gKCD5Vbb1Wjylal45l2GiYkCo+ry4nleqAERlgQ0HYz2YLz lnkP0GoDTds/yw2MSavl6iqh4BUf5rpdroty1XrIcFV/BjnpO3xQ8ksRbDqFanqMZgKL kJPA== X-Gm-Message-State: ABuFfoiZseEuHaBSzufrA/GDh3+kJ+hMIMxVs8TQGoeyLuUK1z/XJHEN Cp/lR4mcbr+FMaOdmWXbwR9rMFhgnoo= X-Google-Smtp-Source: ACcGV63F+hH19FRaktntvE36duSZLTN2tN6aDaiNpNwhNuBJ1vQUExPohC5vCuONDmpeYu9t4LboTw== X-Received: by 2002:a62:fd0b:: with SMTP id p11-v6mr22662777pfh.167.1539712180701; Tue, 16 Oct 2018 10:49:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:49:08 -0700 Message-Id: <20181016174911.9052-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42a Subject: [Qemu-devel] [PULL 18/21] target/s390x: Split do_cdsg, do_lpq, do_stpq X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/mem_helper.c | 128 ++++++++++++++++++-------------------- 1 file changed, 61 insertions(+), 67 deletions(-) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index e106f61b4e..b5858d2fa2 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1380,57 +1380,58 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t = r1, uint32_t r2, return cc; } =20 -static void do_cdsg(CPUS390XState *env, uint64_t addr, - uint32_t r1, uint32_t r3, bool parallel) +void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, + uint32_t r1, uint32_t r3) { uintptr_t ra =3D GETPC(); Int128 cmpv =3D int128_make128(env->regs[r1 + 1], env->regs[r1]); Int128 newv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); Int128 oldv; + uint64_t oldh, oldl; bool fail; =20 - if (parallel) { -#if !HAVE_CMPXCHG128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); - oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, = ra); - fail =3D !int128_eq(oldv, cmpv); -#endif - } else { - uint64_t oldh, oldl; + check_alignment(env, addr, 16, ra); =20 - check_alignment(env, addr, 16, ra); + oldh =3D cpu_ldq_data_ra(env, addr + 0, ra); + oldl =3D cpu_ldq_data_ra(env, addr + 8, ra); =20 - oldh =3D cpu_ldq_data_ra(env, addr + 0, ra); - oldl =3D cpu_ldq_data_ra(env, addr + 8, ra); - - oldv =3D int128_make128(oldl, oldh); - fail =3D !int128_eq(oldv, cmpv); - if (fail) { - newv =3D oldv; - } - - cpu_stq_data_ra(env, addr + 0, int128_gethi(newv), ra); - cpu_stq_data_ra(env, addr + 8, int128_getlo(newv), ra); + oldv =3D int128_make128(oldl, oldh); + fail =3D !int128_eq(oldv, cmpv); + if (fail) { + newv =3D oldv; } =20 + cpu_stq_data_ra(env, addr + 0, int128_gethi(newv), ra); + cpu_stq_data_ra(env, addr + 8, int128_getlo(newv), ra); + env->cc_op =3D fail; env->regs[r1] =3D int128_gethi(oldv); env->regs[r1 + 1] =3D int128_getlo(oldv); } =20 -void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, - uint32_t r1, uint32_t r3) -{ - do_cdsg(env, addr, r1, r3, false); -} - void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr, uint32_t r1, uint32_t r3) { - do_cdsg(env, addr, r1, r3, true); + uintptr_t ra =3D GETPC(); + Int128 cmpv =3D int128_make128(env->regs[r1 + 1], env->regs[r1]); + Int128 newv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); + int mem_idx; + TCGMemOpIdx oi; + Int128 oldv; + bool fail; + + if (!HAVE_CMPXCHG128) { + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + } + + mem_idx =3D cpu_mmu_index(env, false); + oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); + fail =3D !int128_eq(oldv, cmpv); + + env->cc_op =3D fail; + env->regs[r1] =3D int128_gethi(oldv); + env->regs[r1 + 1] =3D int128_getlo(oldv); } =20 static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, @@ -2097,16 +2098,25 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t a= ddr) #endif =20 /* load pair from quadword */ -static uint64_t do_lpq(CPUS390XState *env, uint64_t addr, bool parallel) +uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t addr) { uintptr_t ra =3D GETPC(); uint64_t hi, lo; =20 - if (!parallel) { - check_alignment(env, addr, 16, ra); - hi =3D cpu_ldq_data_ra(env, addr + 0, ra); - lo =3D cpu_ldq_data_ra(env, addr + 8, ra); - } else if (HAVE_ATOMIC128) { + check_alignment(env, addr, 16, ra); + hi =3D cpu_ldq_data_ra(env, addr + 0, ra); + lo =3D cpu_ldq_data_ra(env, addr + 8, ra); + + env->retxl =3D lo; + return hi; +} + +uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uint64_t addr) +{ + uintptr_t ra =3D GETPC(); + uint64_t hi, lo; + + if (HAVE_ATOMIC128) { int mem_idx =3D cpu_mmu_index(env, false); TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); Int128 v =3D helper_atomic_ldo_be_mmu(env, addr, oi, ra); @@ -2120,27 +2130,23 @@ static uint64_t do_lpq(CPUS390XState *env, uint64_t= addr, bool parallel) return hi; } =20 -uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t addr) -{ - return do_lpq(env, addr, false); -} - -uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uint64_t addr) -{ - return do_lpq(env, addr, true); -} - /* store pair to quadword */ -static void do_stpq(CPUS390XState *env, uint64_t addr, - uint64_t low, uint64_t high, bool parallel) +void HELPER(stpq)(CPUS390XState *env, uint64_t addr, + uint64_t low, uint64_t high) { uintptr_t ra =3D GETPC(); =20 - if (!parallel) { - check_alignment(env, addr, 16, ra); - cpu_stq_data_ra(env, addr + 0, high, ra); - cpu_stq_data_ra(env, addr + 8, low, ra); - } else if (HAVE_ATOMIC128) { + check_alignment(env, addr, 16, ra); + cpu_stq_data_ra(env, addr + 0, high, ra); + cpu_stq_data_ra(env, addr + 8, low, ra); +} + +void HELPER(stpq_parallel)(CPUS390XState *env, uint64_t addr, + uint64_t low, uint64_t high) +{ + uintptr_t ra =3D GETPC(); + + if (HAVE_ATOMIC128) { int mem_idx =3D cpu_mmu_index(env, false); TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); Int128 v =3D int128_make128(low, high); @@ -2150,18 +2156,6 @@ static void do_stpq(CPUS390XState *env, uint64_t add= r, } } =20 -void HELPER(stpq)(CPUS390XState *env, uint64_t addr, - uint64_t low, uint64_t high) -{ - do_stpq(env, addr, low, high, false); -} - -void HELPER(stpq_parallel)(CPUS390XState *env, uint64_t addr, - uint64_t low, uint64_t high) -{ - do_stpq(env, addr, low, high, true); -} - /* Execute instruction. This instruction executes an insn modified with the contents of r1. It does not change the executed instruction in mem= ory; it does not change the program counter. --=20 2.17.2