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[174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=v87Nv8KtOwBwH1Vf6pnmPV08acciS7b2jzoCLS0sc10=; b=GqN2EAokRKp+BnHs4uXJQaCIXM0RiwVaJQcM9H692MdmkINxpMR38aRsxc9neifpFk x3Dob6MF54oHiVHwW6uC/ynho4TigCSapPic4ayfY2A1omP1oBeG4VXb60j0fYD+syAA 2wYKryKBywUWe4qG7L5y94WkMC2f/LFtBXM6M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=v87Nv8KtOwBwH1Vf6pnmPV08acciS7b2jzoCLS0sc10=; b=eZJH/RxPdAg8pLabZg1uvWkJW1rkNv+iqJ/eAWVF+UdEj/laUI1iXNb7dPUEVXMjk8 CPzPOUkNnSHYWPNxa6aFRmtK361lZzjVC3AgrmrTVUrUcQMaz/UpAUVM6j5vCONVv2ws T6hYbKwd/GH0SDZX9lWIJPvat7Lf77cIG62TB/L4J2ZaHbcV6q908EFr4wW9GcHt5lV4 Gz7+behJ9+HnLzgi88isscd8RcBcxi7ytntM0zV8FXHRyFmYo1IMGwOQNbO0iacsmXxj Wq1FaFsWMxdYAgtllZmcklkj6cZ5G/iMTnodL+oOYs06A95Jd8VzhY2S3QzDiYtlNkOk eANA== X-Gm-Message-State: ABuFfoi9yxvB8usXhy2Wdk1zbe9RrjoJndSI9yK2Tanq/8YBEiVNg5Ux uVsxXcRRcIFbG8dqe8NiEqLorJQxvKM= X-Google-Smtp-Source: ACcGV62vv/nbXziGOTMIoxm1cTZRmT9+Cw4YreNGebrk2l9ieqJDWzlAwmapiRfjRQLxyjRUnJd22Q== X-Received: by 2002:a63:b518:: with SMTP id y24-v6mr21252670pge.436.1539712155213; Tue, 16 Oct 2018 10:49:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:48:51 -0700 Message-Id: <20181016174911.9052-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42c Subject: [Qemu-devel] [PULL 01/21] tcg: Implement CPU_LOG_TB_NOCHAIN during expansion X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Rather than test NOCHAIN before linking, do not emit the goto_tb opcode at all. We already do this for goto_ptr. Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 2 +- tcg/tcg-op.c | 9 ++++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 6bcb6d99bd..870027d435 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -416,7 +416,7 @@ static inline TranslationBlock *tb_find(CPUState *cpu, } #endif /* See if we can patch the calling TB. */ - if (last_tb && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { + if (last_tb) { tb_add_jump(last_tb, tb_exit, tb); } return tb; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index daa416a143..7a8015c5a9 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2586,6 +2586,10 @@ void tcg_gen_exit_tb(TranslationBlock *tb, unsigned = idx) seen this numbered exit before, via tcg_gen_goto_tb. */ tcg_debug_assert(tcg_ctx->goto_tb_issue_mask & (1 << idx)); #endif + /* When not chaining, exit without indicating a link. */ + if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { + val =3D 0; + } } else { /* This is an exit via the exitreq label. */ tcg_debug_assert(idx =3D=3D TB_EXIT_REQUESTED); @@ -2603,7 +2607,10 @@ void tcg_gen_goto_tb(unsigned idx) tcg_debug_assert((tcg_ctx->goto_tb_issue_mask & (1 << idx)) =3D=3D 0); tcg_ctx->goto_tb_issue_mask |=3D 1 << idx; #endif - tcg_gen_op1i(INDEX_op_goto_tb, idx); + /* When not chaining, we simply fall through to the "fallback" exit. = */ + if (!qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { + tcg_gen_op1i(INDEX_op_goto_tb, idx); + } } =20 void tcg_gen_lookup_and_goto_ptr(void) --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539714387617816.919104111206; Tue, 16 Oct 2018 11:26:27 -0700 (PDT) Received: from localhost ([::1]:59601 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCU30-0004eP-D7 for importer@patchew.org; Tue, 16 Oct 2018 14:26:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59698) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTTP-00046V-6H for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCTTL-00010T-1V for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:38 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:34559) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gCTTK-0000fG-LU for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:34 -0400 Received: by mail-pf1-x429.google.com with SMTP id f78-v6so6060615pfe.1 for ; Tue, 16 Oct 2018 10:49:18 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=w2Bp504AhgXMpCvkutSLGODfC2pPE7Pe3qOAFYLZ3OM=; b=QuHesdlDa4Zg7r33c+v6PzJYBHzJorvcjeOS7JHinX5v6XREj+pm7vEULcObKo8eHU mdilLbiOFJ2d7iuf1lU29jQR6hvRP6L/xvGgd3LV5fcr7aVxZmPSrcEBmm95ju9JLRme xHLAugFDEGUVPUhWfvqEZfHXRfVIf2QdDEmmE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=w2Bp504AhgXMpCvkutSLGODfC2pPE7Pe3qOAFYLZ3OM=; b=hNYhtr7moFpdLqUT0ev2eqeTG4IH/gENS4DjOzPphiP/eUOA3pz+4JB0U29vuItVZd 9UGyA79+Rm62/3BLOcqlEe8+boBXvjO7iW/ssrdOjuVgK0ZN9Um8Viasyc3GME9Osu0g 0TrhiLsDScM6n4FqW1GJ7VQCJYE/P4H++0JW/Sdy16Fo9JIx7VDPUbHspBFHrSfFYRd1 /908eRnuvXWgE8RHSz6GshYu4Wl8WdkWPa7wCzN/EseuRzlcU0TgZ7GMjhCdH4aPWpz+ GsEjO+i3Ma9Lj9sDkHkkfyuXJ4C8mcV68WzJB+k/rA7dzfpfM6X9zBs/P7ZrBJ4O5fso SGug== X-Gm-Message-State: ABuFfohpQvfDhT96bb1FsbE2/yKgcP8sGURUilcGjHpoPr64BrcKEoNn qS3/BbdLHB6WbCrIEc9v1B1jwZ6pyZE= X-Google-Smtp-Source: ACcGV62KCdyGm1c13YF2h5OpV0HFSH2q0WA0GU8WEyzrr2Z43NYykONeWjC4e7iwLioWf+er3sSfKA== X-Received: by 2002:a63:6c4a:: with SMTP id h71-v6mr20888859pgc.326.1539712156756; Tue, 16 Oct 2018 10:49:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:48:52 -0700 Message-Id: <20181016174911.9052-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::429 Subject: [Qemu-devel] [PULL 02/21] tcg: access cpu->icount_decr.u16.high with atomics X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Consistently access u16.high with atomics to avoid undefined behaviour in MTTCG. Note that icount_decr.u16.low is only used in icount mode, so regular accesses to it are OK. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Message-Id: <20181010144853.13005-2-cota@braap.org> Signed-off-by: Richard Henderson --- accel/tcg/tcg-all.c | 2 +- accel/tcg/translate-all.c | 2 +- qom/cpu.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 56dbb56a16..3d25bdcc17 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -51,7 +51,7 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask) if (!qemu_cpu_is_self(cpu)) { qemu_cpu_kick(cpu); } else { - cpu->icount_decr.u16.high =3D -1; + atomic_set(&cpu->icount_decr.u16.high, -1); if (use_icount && !cpu->can_do_io && (mask & ~old_mask) !=3D 0) { diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index ad5c758246..356dcd0948 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -2341,7 +2341,7 @@ void cpu_interrupt(CPUState *cpu, int mask) { g_assert(qemu_mutex_iothread_locked()); cpu->interrupt_request |=3D mask; - cpu->icount_decr.u16.high =3D -1; + atomic_set(&cpu->icount_decr.u16.high, -1); } =20 /* diff --git a/qom/cpu.c b/qom/cpu.c index 92599f3541..20ad54d43f 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -266,7 +266,7 @@ static void cpu_common_reset(CPUState *cpu) cpu->mem_io_pc =3D 0; cpu->mem_io_vaddr =3D 0; cpu->icount_extra =3D 0; - cpu->icount_decr.u32 =3D 0; + atomic_set(&cpu->icount_decr.u32, 0); cpu->can_do_io =3D 1; cpu->exception_index =3D -1; cpu->crash_occurred =3D false; --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539714063145841.0064357173563; Tue, 16 Oct 2018 11:21:03 -0700 (PDT) Received: from localhost ([::1]:59565 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTxg-0007Ml-Ru for importer@patchew.org; Tue, 16 Oct 2018 14:20:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59690) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTTP-00046Q-3p for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCTTK-0000zZ-LL for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:38 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:33381) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gCTTK-0000gZ-CD for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:34 -0400 Received: by mail-pf1-x42b.google.com with SMTP id 78-v6so9443564pfq.0 for ; Tue, 16 Oct 2018 10:49:19 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XPHfakviOHeoyHH8+nY/3eH0/sW+Fz1CCwfjdYYgSx4=; b=e9HD1dXTm0bltAwCnqMjvCCfJUv2HsF6O6fDThu0d5Ku9/+fMzMT0hQmPt1LFFxfrc dSV5HQwlbYZp5nzihpJ5LLjZ7eEYsXDnUubAi0HDcZW83voGddiAeMmxO7aCp2R0jQD+ DeCIcZ1gsRUMElml+qnciT/Hi8cqHNpROv0Lw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XPHfakviOHeoyHH8+nY/3eH0/sW+Fz1CCwfjdYYgSx4=; b=UjRFi4RdyOO/R3CvZGqfW2qU+qqBq7ngUnorM+cknVTQUsX6wQTmIECip7CXam9T0d iCXUBMxOuG/qiXat9C1HKKx3G/a3FN4Zu9nsvGiv9bYtgRIzUieaIZy3R3n+G58OXuqz SSuNpiU35dXJhaoVez8GohNLA/ieTuC7QMs895vnCHSxVbolgxTGsfnjLzqznHzaEvpr ilJv5F2ZIcgKa7syUNjqVdjyw8mIANeNTKr6djhtZjsPUN5/jhJ3M2/7HBfF/lErlHRA 6H/gXXa3IyuPLhM9FwRb6Zo8cY64zXe87h96j1t5g9oaV/hbYwCPx+TlJaoN+jgdgZ1C zgGQ== X-Gm-Message-State: ABuFfohGaSkEwCgSgQi9fhWyiMIIxjpEj/XjLLG/F+p+gCGe26sjQ/7H P2qnYcjQJXUcr+YY1LDALV3FksimCK0= X-Google-Smtp-Source: ACcGV605H3MuQYX3jqVwwWT2Uj51iLqyouQ2pQpirWmtGOKFslkWvbZNBR051rcSIyqZiP+Bxpj7TA== X-Received: by 2002:a62:1655:: with SMTP id 82-v6mr22735255pfw.11.1539712158259; Tue, 16 Oct 2018 10:49:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:48:53 -0700 Message-Id: <20181016174911.9052-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42b Subject: [Qemu-devel] [PULL 03/21] tcg: fix use of uninitialized variable under CONFIG_PROFILER X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" We forgot to initialize n in commit 15fa08f845 ("tcg: Dynamically allocate TCGOps", 2017-12-29). Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Emilio G. Cota Message-Id: <20181010144853.13005-3-cota@braap.org> Signed-off-by: Richard Henderson --- tcg/tcg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index f27b22bd3c..8f26916b99 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3430,7 +3430,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) =20 #ifdef CONFIG_PROFILER { - int n; + int n =3D 0; =20 QTAILQ_FOREACH(op, &s->ops, link) { n++; --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539714441864272.3729019466193; Tue, 16 Oct 2018 11:27:21 -0700 (PDT) Received: from localhost ([::1]:59602 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCU3s-0005LR-KZ for importer@patchew.org; Tue, 16 Oct 2018 14:27:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59678) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTTO-000468-S9 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCTTK-0000ya-9o for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:38 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:37750) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gCTTK-0000hK-0m for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:34 -0400 Received: by mail-pf1-x430.google.com with SMTP id j23-v6so11817986pfi.4 for ; Tue, 16 Oct 2018 10:49:21 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HIK9nMwv5A9Xjvh/YPMt/fmhRKI03KqcehqyTqQt1wo=; b=McZOj+tHzdaNtmt8rt3ZGXzw9RP9gDX2T087weMkdroDHbpIWXi0CgK6EjhCnGObRd /Snov2/ReQgd9bh8bKR4Rqxxq696HMLNFAABlemChhDgtYEoxwNFAGOFVals33Arl8U5 bVO68t+d9pIgj3GlF9t+ArWy18iEiyQHuMJP8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HIK9nMwv5A9Xjvh/YPMt/fmhRKI03KqcehqyTqQt1wo=; b=go9A3y8keNzt61kkGjPfm9fWJS67lMMcGj5XC7MDmNC0wMQdeSFY6OjvS0mH9YjwdR VncvFYw++fj6uok5+OGAJHBIogovayMoYxamXNXgmH3TlC0hgCeTiH6yppTiGsy1sWE+ HL3WmL47k+oNbOJ1G7FMdnumJeO+9IXd8/eSCAIqwKMmiyo3CYvu0aBEcgNxAAPqBKRU YuJCnKOxoXLfhp0FU38Jn2rNUpcPJrDvXopiJatkt9lTjg9sYhxfuFSGHI19x740oN4b 3nr1UFfygNSW3GMM1mtpyagOvd4pG+/0Sb55Dp2VTBfvmVYU40+vabjnbnEpMs7/ov7X eM6Q== X-Gm-Message-State: ABuFfoidhAYx+4PRpm10hriDKb5Roothce60n4ks0KOBq9fVrSGZw+CV g2vc8i618T0tI/2zThkQ9IfPAEifT08= X-Google-Smtp-Source: ACcGV601b5qJvpStLLTZ/cilE2oFygVg+Dyw8pCDVolTxW1W+g95blxTjqqRUN+rwKPencFhb2tpDQ== X-Received: by 2002:a62:5441:: with SMTP id i62-v6mr23174268pfb.155.1539712159863; Tue, 16 Oct 2018 10:49:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:48:54 -0700 Message-Id: <20181016174911.9052-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::430 Subject: [Qemu-devel] [PULL 04/21] tcg: plug holes in struct TCGProfile X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" This plugs two 4-byte holes in 64-bit. Signed-off-by: Emilio G. Cota Message-Id: <20181010144853.13005-4-cota@braap.org> Signed-off-by: Richard Henderson --- tcg/tcg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index f9f12378e9..d80ef2a883 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -633,8 +633,8 @@ typedef struct TCGProfile { int64_t tb_count; int64_t op_count; /* total insn count */ int op_count_max; /* max insn per TB */ - int64_t temp_count; int temp_count_max; + int64_t temp_count; int64_t del_op_count; int64_t code_in_len; int64_t code_out_len; --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539713870662115.42665818939474; Tue, 16 Oct 2018 11:17:50 -0700 (PDT) Received: from localhost ([::1]:59548 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTuc-0004Bx-9b for importer@patchew.org; Tue, 16 Oct 2018 14:17:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59701) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTTP-00046X-6p for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCTTK-0000zU-L1 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:38 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:44118) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gCTTK-0000iN-9K for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:34 -0400 Received: by mail-pf1-x429.google.com with SMTP id r9-v6so11810587pff.11 for ; Tue, 16 Oct 2018 10:49:22 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TgDCiAlCqNyacH51QEaK7ppBxrOCvC2iTKIGNr6fsnY=; b=fB2N+I6OuCYnekuFBdu1GwQJLr0WrHGdLdTZ4rlAEO6THkvqQRExNmLVcYggkgqCTL 7x+S2WVm6qZ3EiKvBHuT3m7Tluudf8YijgWcV+fyDZBWOMhNZgnNV93wFwSfN6yHqusc GVtO1OKavZuVGFeY2ImoPd122E4AtOzaBwrCk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TgDCiAlCqNyacH51QEaK7ppBxrOCvC2iTKIGNr6fsnY=; b=f4DmWyR9iQ2txgLNxSzyKhxdkmg7HsQTg3FcqCMNZjVqXQsDfXsIKCI106NW8dl8pT sxZSBpXhlj/DSjEV/EUiq+Odr3j6aMpOXDJmmJvxR14wrmz3p1+Fw4RRwsVt9gYpHPd3 pNmuMm3BD+W9KRmmb41jf5TIPov71G6Yr8KJXfZM4uXvnwbX6VIYLuFXH64hHhA5Mj7D 4tl1aJ1HkQ6HRNfiO+uRj+XkFVB4GXTh6PSBaJZByQ/pjbPwtrnumRYRGBCYHENNSwDs UMtoYLN3l8/6UzZtmZp/6b7pDT64PIAFYnXSieXN9JJqCNsQwE91AsYGRRLoEi/b01T2 pvGA== X-Gm-Message-State: ABuFfoi7b4X0vLu5pTwLJUGOzJvxK4xBHx019u5P8uDRDQJIJc2FW2lv 1aZYcJRXWOU9Cshw7iU+JQhQr92zZ48= X-Google-Smtp-Source: ACcGV60UWuE6tjNQnxPrYNamsYvuJr81Pk31wIIR2MGMQ/6qOg9xVN7oBp3NQbm3g8UQuf3oA28p6Q== X-Received: by 2002:a63:4a64:: with SMTP id j36-v6mr21044940pgl.168.1539712161508; Tue, 16 Oct 2018 10:49:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:48:55 -0700 Message-Id: <20181016174911.9052-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::429 Subject: [Qemu-devel] [PULL 05/21] tcg: distribute tcg_time into TCG contexts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" When we implemented per-vCPU TCG contexts, we forgot to also distribute the tcg_time counter, which has remained as a global accessed without any serialization, leading to potentially missed counts. Fix it by distributing the field over the TCG contexts, embedding it into TCGProfile with a field called "cpu_exec_time", which is more descriptive than "tcg_time". Add a function to query this value directly, and for completeness, fill in the field in tcg_profile_snapshot, even though its callers do not use it. Signed-off-by: Emilio G. Cota Message-Id: <20181010144853.13005-5-cota@braap.org> Signed-off-by: Richard Henderson --- include/qemu/timer.h | 1 - tcg/tcg.h | 2 ++ cpus.c | 3 ++- monitor.c | 13 ++++++++++--- tcg/tcg.c | 23 +++++++++++++++++++++++ 5 files changed, 37 insertions(+), 5 deletions(-) diff --git a/include/qemu/timer.h b/include/qemu/timer.h index a005ed2692..dfecd03e28 100644 --- a/include/qemu/timer.h +++ b/include/qemu/timer.h @@ -1046,7 +1046,6 @@ static inline int64_t profile_getclock(void) return get_clock(); } =20 -extern int64_t tcg_time; extern int64_t dev_time; #endif =20 diff --git a/tcg/tcg.h b/tcg/tcg.h index d80ef2a883..c59f254e27 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -629,6 +629,7 @@ typedef struct TCGOp { QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); =20 typedef struct TCGProfile { + int64_t cpu_exec_time; int64_t tb_count1; int64_t tb_count; int64_t op_count; /* total insn count */ @@ -1002,6 +1003,7 @@ int tcg_check_temp_count(void); #define tcg_check_temp_count() 0 #endif =20 +int64_t tcg_cpu_exec_time(void); void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf); void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf); =20 diff --git a/cpus.c b/cpus.c index 361678e459..cce64874e6 100644 --- a/cpus.c +++ b/cpus.c @@ -1425,7 +1425,8 @@ static int tcg_cpu_exec(CPUState *cpu) ret =3D cpu_exec(cpu); cpu_exec_end(cpu); #ifdef CONFIG_PROFILER - tcg_time +=3D profile_getclock() - ti; + atomic_set(&tcg_ctx->prof.cpu_exec_time, + tcg_ctx->prof.cpu_exec_time + profile_getclock() - ti); #endif return ret; } diff --git a/monitor.c b/monitor.c index b9258a7438..823b5a1099 100644 --- a/monitor.c +++ b/monitor.c @@ -83,6 +83,7 @@ #include "sysemu/cpus.h" #include "sysemu/iothread.h" #include "qemu/cutils.h" +#include "tcg/tcg.h" =20 #if defined(TARGET_S390X) #include "hw/s390x/storage-keys.h" @@ -1966,16 +1967,22 @@ static void hmp_info_numa(Monitor *mon, const QDict= *qdict) =20 #ifdef CONFIG_PROFILER =20 -int64_t tcg_time; int64_t dev_time; =20 static void hmp_info_profile(Monitor *mon, const QDict *qdict) { + static int64_t last_cpu_exec_time; + int64_t cpu_exec_time; + int64_t delta; + + cpu_exec_time =3D tcg_cpu_exec_time(); + delta =3D cpu_exec_time - last_cpu_exec_time; + monitor_printf(mon, "async time %" PRId64 " (%0.3f)\n", dev_time, dev_time / (double)NANOSECONDS_PER_SECOND); monitor_printf(mon, "qemu time %" PRId64 " (%0.3f)\n", - tcg_time, tcg_time / (double)NANOSECONDS_PER_SECOND); - tcg_time =3D 0; + delta, delta / (double)NANOSECONDS_PER_SECOND); + last_cpu_exec_time =3D cpu_exec_time; dev_time =3D 0; } #else diff --git a/tcg/tcg.c b/tcg/tcg.c index 8f26916b99..e85133ef05 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -30,6 +30,7 @@ /* Define to jump the ELF file used to communicate with GDB. */ #undef DEBUG_JIT =20 +#include "qemu/error-report.h" #include "qemu/cutils.h" #include "qemu/host-utils.h" #include "qemu/timer.h" @@ -3361,6 +3362,7 @@ void tcg_profile_snapshot(TCGProfile *prof, bool coun= ters, bool table) const TCGProfile *orig =3D &s->prof; =20 if (counters) { + PROF_ADD(prof, orig, cpu_exec_time); PROF_ADD(prof, orig, tb_count1); PROF_ADD(prof, orig, tb_count); PROF_ADD(prof, orig, op_count); @@ -3412,11 +3414,32 @@ void tcg_dump_op_count(FILE *f, fprintf_function cp= u_fprintf) prof.table_op_count[i]); } } + +int64_t tcg_cpu_exec_time(void) +{ + unsigned int n_ctxs =3D atomic_read(&n_tcg_ctxs); + unsigned int i; + int64_t ret =3D 0; + + for (i =3D 0; i < n_ctxs; i++) { + const TCGContext *s =3D atomic_read(&tcg_ctxs[i]); + const TCGProfile *prof =3D &s->prof; + + ret +=3D atomic_read(&prof->cpu_exec_time); + } + return ret; +} #else void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf) { cpu_fprintf(f, "[TCG profiler not compiled]\n"); } + +int64_t tcg_cpu_exec_time(void) +{ + error_report("%s: TCG profiler not compiled", __func__); + exit(EXIT_FAILURE); +} #endif =20 =20 --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pJ03w/05K8uS57fQC05w2JHgSo9jMtdD8AAptElnit8=; b=FAoEqDjB1BX97nAhxapxYX7jNcIrH/1U3SCegvWzK925sgzb9eO8/JbMl4A8XOK/ic VmbP4cXFYRNMHbRhi84ipmb5INeYqXcYx3LdmkgL0oUHmmO3wQwuzZXGFoPyAFWMyAZO +zOh83snBTcUNOU2Anu/oKwxxM3H0y00PR0yU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pJ03w/05K8uS57fQC05w2JHgSo9jMtdD8AAptElnit8=; b=T6s4sldroYWs5Vs8Qg+14WPVCdwPQL3yB+Wm2H5McaNVf+crJsKIbP9DvnivLCqeHf W7sEc3/i1NvGMrU/WVxkscBCgaUNGbVwFtCTcIrasVLcrEZ4rdE2JPzlLdTAtwHp8oUd +8UiBmTBXIF6Ufm+Q6L14RB4WWAYNtAUAkFHJ3/qUGoOh3tj4o9u/YIAVKzcWx0mEk+A Sr+A6Lc7t3ASggPPKQbE7B2zwwnbozZrUNHEr/zaJfgNGRYAPygTZ7aN7JMJxHQE9O3h jV+9g64YfEDyVD8hhfOGdety7d0ooSrkpQXs0p/MmQJ3cRiZtm64LAF0corCXRpC31s9 Ok2A== X-Gm-Message-State: ABuFfoiG9osf2pHV0H9/fXuV0c+L/cWUfok3gbcR4GvdvyP2pZ9cfmW6 dUg/X2shLVIAsXIdr1i5P6T6uGJmroQ= X-Google-Smtp-Source: ACcGV62b1h2ryGg1h1+z/HpLZdlTfW60XzkZUZyfIGVsxLbOcvSDC7Rth8qJJHULrLkme8N+PXA+0A== X-Received: by 2002:a17:902:7798:: with SMTP id o24-v6mr21916245pll.299.1539712163150; Tue, 16 Oct 2018 10:49:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:48:56 -0700 Message-Id: <20181016174911.9052-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62f Subject: [Qemu-devel] [PULL 06/21] target/alpha: remove tlb_flush from alpha_cpu_initfn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" As far as I can tell tlb_flush does not need to be called this early. tlb_flush is eventually called after the CPU has been realized. This change paves the way to the introduction of tlb_init, which will be called from cpu_exec_realizefn. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Message-Id: <20181009174557.16125-2-cota@braap.org> Signed-off-by: Richard Henderson --- target/alpha/cpu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index b08078e7fc..a953897fcc 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -201,7 +201,6 @@ static void alpha_cpu_initfn(Object *obj) CPUAlphaState *env =3D &cpu->env; =20 cs->env_ptr =3D env; - tlb_flush(cs); =20 env->lock_addr =3D -1; #if defined(CONFIG_USER_ONLY) --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539713498391610.9490452052012; Tue, 16 Oct 2018 11:11:38 -0700 (PDT) Received: from localhost ([::1]:59505 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTof-00071D-1Z for importer@patchew.org; Tue, 16 Oct 2018 14:11:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59668) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTTO-00045V-6u for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCTTJ-0000y7-Rr for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:37 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:38062) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gCTTI-0000lD-HZ for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:33 -0400 Received: by mail-pg1-x52d.google.com with SMTP id f8-v6so11197723pgq.5 for ; Tue, 16 Oct 2018 10:49:25 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iQuRnp6tSFYZasKkNBV6hIxMETb4h2l2cVJHyyzAdxw=; b=UzoJjn+hj54+B0pMBN1AzUyT9Yctrsi4g6bNYcuxxLbHkMggjQLyJdGj45gGvZ+F9t TceNlEK93BvMfCg9CS2Pj7hUUGrnlXi7JKbPd2ZrZHK1t5l4g8Hl0zCApsIu4L/jqOKz K+uBMVqf7D0qwobPZNei968jbW6RKLqzCGUy0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iQuRnp6tSFYZasKkNBV6hIxMETb4h2l2cVJHyyzAdxw=; b=IaxioscBvJ0BmwaTn9gJV07QWI2SXdHgqJgYAFlzPQ9kVOdKMBRGd3SFq1xC0br57a L8Y9u0mE91ETNr2au9d/UrVt9hmVtTHHj4NYSUbYuMm3A5EbQHBLpv5Rcq89Jgk1O3Ns eoLbrogW5ut6gyZMXwD4ZbiDfwIKQOADbmujNlEU0dJfmR8K7DE8TpJxlzW/4rz7litQ CdsPESpvNXDaQn4ys1IWtVu3C0NL+uH+9cZiQDKrYVmV/+gusZGc0jVG3EdHH8pVmBKu BoaYM84QIOiJlk/s2DiTD4Q5F4WM8DkZKOBmJ3dlbtyZcY8w4Wb1GvRUo+pEiC5qSPQ2 ocxg== X-Gm-Message-State: ABuFfogUmoP9nopYrL8MiJG6KjO/7D0gHAROCmaiUeUS1bbka+DxMGFm 0ZBG1yTPKz5EZP9xFiVKF/Ko65BYzMo= X-Google-Smtp-Source: ACcGV60zuHif70vlqoZSzxqeLo6Q80v5pR3I8P/OHsdncMea+YvMdpPoY2BVQzQ5Xewl9vP2ZEuiuA== X-Received: by 2002:a62:7501:: with SMTP id q1-v6mr22815804pfc.225.1539712164490; Tue, 16 Oct 2018 10:49:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:48:57 -0700 Message-Id: <20181016174911.9052-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52d Subject: [Qemu-devel] [PULL 07/21] target/unicore32: remove tlb_flush from uc32_init_fn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Guan Xuetao , peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" As far as I can tell tlb_flush does not need to be called this early. tlb_flush is eventually called after the CPU has been realized. This change paves the way to the introduction of tlb_init, which will be called from cpu_exec_realizefn. Cc: Guan Xuetao Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Message-Id: <20181009174557.16125-3-cota@braap.org> Signed-off-by: Richard Henderson --- target/unicore32/cpu.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 68f978d80b..2b49d1ca40 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -116,8 +116,6 @@ static void uc32_cpu_initfn(Object *obj) env->uncached_asr =3D ASR_MODE_PRIV; env->regs[31] =3D 0x03000000; #endif - - tlb_flush(cs); } =20 static const VMStateDescription vmstate_uc32_cpu =3D { --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539713672523485.93460980617465; Tue, 16 Oct 2018 11:14:32 -0700 (PDT) Received: from localhost ([::1]:59517 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTrO-0001jI-7F for importer@patchew.org; Tue, 16 Oct 2018 14:14:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59696) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTTP-00046U-5w for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCTTK-0000zh-Qr for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:38 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:34983) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gCTTK-0000lq-Hr for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:34 -0400 Received: by mail-pg1-x544.google.com with SMTP id 32-v6so20135pgu.2 for ; Tue, 16 Oct 2018 10:49:27 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mNeH2UybqAeBdXYEpo8e4HunbPQRrwwxFmV/1vG0wc0=; b=L8hsWgHPoTn1N+ReG3sdFnB1EP5+woEo6VbD15HtbVc07WhCxoeMQ0R9uQKjZfWTxu ygVCGU6JgYu1OyzEf60WlXaLLv6hJ0B6Bo9VwTD/gWTNVTw3HFQgy7UkiRX0cfEUK6Ef KVY0X2ohP4cM9hZDlp57Pff6IWwoThRm499k8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mNeH2UybqAeBdXYEpo8e4HunbPQRrwwxFmV/1vG0wc0=; b=n3oouBQ/p854TqL/Js7FISV7I8awLfbj44moiH/wsk6h3+VILR35usP/6vSmooWBfJ UFQKrh7PiYxUYu2kgZeU8Mef2PgSjI5/xXeaqVfnikj2gbDhW764lci6LYiA1r4B6T55 zr22OrrWq/1qfkd+FaYL3yBBG3VMtDO4ZxtW3hise87+Kfi38pNw6+jcEuOxRL5q9W4V RiMkCup/yIAyAbXUAa4XidWpftelZHCIxt/WNmAQayXtmC4ESoX50OL0hMzpqdWL8dwS q66n5ZYIaNGGFazW0evTf1khlplm97dFrHOyPh0vYYo17QWVc5ryZyae/cnEbVEgaRyN ubNg== X-Gm-Message-State: ABuFfogcdr5R7czF3l8N8fgS8msP/k+RvydGAz3AoZhwMi1rdpXzI+4f IZ+iWKAZZsYSv6XMt8Qzu0ZfMLtLeWs= X-Google-Smtp-Source: ACcGV607XB/Vnutke6J8J1twtXrW3W6nJn/dsKAoWAIqyX8UlktpVD25ViqiaY+t1aozdeR6yxW3lA== X-Received: by 2002:a62:ce83:: with SMTP id y125-v6mr23119326pfg.201.1539712166064; Tue, 16 Oct 2018 10:49:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:48:58 -0700 Message-Id: <20181016174911.9052-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PULL 08/21] exec: introduce tlb_init X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" Paves the way for the addition of a per-TLB lock. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Message-Id: <20181009174557.16125-4-cota@braap.org> Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 8 ++++++++ accel/tcg/cputlb.c | 4 ++++ exec.c | 1 + 3 files changed, 13 insertions(+) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5f78125582..815e5b1e83 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -99,6 +99,11 @@ void cpu_address_space_init(CPUState *cpu, int asidx, =20 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* cputlb.c */ +/** + * tlb_init - initialize a CPU's TLB + * @cpu: CPU whose TLB should be initialized + */ +void tlb_init(CPUState *cpu); /** * tlb_flush_page: * @cpu: CPU whose TLB should be flushed @@ -258,6 +263,9 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_i= dx, uintptr_t retaddr); #else +static inline void tlb_init(CPUState *cpu) +{ +} static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) { } diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f4702ce91f..502eea2850 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -73,6 +73,10 @@ QEMU_BUILD_BUG_ON(sizeof(target_ulong) > sizeof(run_on_c= pu_data)); QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16); #define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1) =20 +void tlb_init(CPUState *cpu) +{ +} + /* flush_all_helper: run fn across all cpus * * If the wait flag is set then the src cpu's helper will be queued as diff --git a/exec.c b/exec.c index d0821e69aa..4fd831ef06 100644 --- a/exec.c +++ b/exec.c @@ -965,6 +965,7 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) tcg_target_initialized =3D true; cc->tcg_initialize(); } + tlb_init(cpu); =20 #ifndef CONFIG_USER_ONLY if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539713882999238.71016832585758; Tue, 16 Oct 2018 11:18:02 -0700 (PDT) Received: from localhost ([::1]:59550 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTur-0004Pm-Vx for importer@patchew.org; Tue, 16 Oct 2018 14:18:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59675) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTTO-000466-RE for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCTTK-0000yU-87 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:38 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:46851) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gCTTJ-0000mJ-Ts for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:34 -0400 Received: by mail-pf1-x42b.google.com with SMTP id r64-v6so11807586pfb.13 for ; Tue, 16 Oct 2018 10:49:28 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::42b Subject: [Qemu-devel] [PULL 09/21] cputlb: fix assert_cpu_is_self macro X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota Message-Id: <20181009174557.16125-5-cota@braap.org> Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 502eea2850..f6b388c961 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -58,9 +58,9 @@ } \ } while (0) =20 -#define assert_cpu_is_self(this_cpu) do { \ +#define assert_cpu_is_self(cpu) do { \ if (DEBUG_TLB_GATE) { \ - g_assert(!cpu->created || qemu_cpu_is_self(cpu)); \ + g_assert(!(cpu)->created || qemu_cpu_is_self(cpu)); \ } \ } while (0) =20 --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153971453067318.600356512061353; Tue, 16 Oct 2018 11:28:50 -0700 (PDT) Received: from localhost ([::1]:59611 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCU5E-0006R6-G3 for importer@patchew.org; Tue, 16 Oct 2018 14:28:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59700) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTTP-00046W-6h for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCTTK-0000yo-DL for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:38 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:33209) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gCTTJ-0000qx-VY for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:34 -0400 Received: by mail-pl1-x62e.google.com with SMTP id s4-v6so11383340plp.0 for ; Tue, 16 Oct 2018 10:49:30 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cE+f8hj2LV4MNdZZfNJ1txs6SrJLXsbsS3xsy84Ye68=; b=P9F1u4r7iQXVsPuTqyUJE7WPZFHGfzjdXGRr+/ujmkX6Iw8Fm4isMurHjTu9hOk7fF eG8VllAxSrjGDCOAa8JQtAP/d+5G+1/dend/lb5IZdK0yQI48CYtMjc02kE3DmYHsROs bSJ5u2TmKWGNAk5B4CTot/7AiM2wFbFSjR4gA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cE+f8hj2LV4MNdZZfNJ1txs6SrJLXsbsS3xsy84Ye68=; b=GxzZ2vwYuOdg6GVRVjiG1NFtbhoy9FP1nrOal4ul9aMp6qApOWDbmhs1EjuKMWGTMq eSNsL5l9+poxdtClCjnKbtZljRg1vNmpjvnX/vVdaCPUIX10n43q/pHVKPE0a5pY+tGF Zr2Kq96gz5QwBvwb7ZwMq86EdHfx+Qstb/w1vTPgJuIfIgSP/nRVPvZxb3xscXty0MPT vZSXV4tGLeoyHsvztQvgxDQMDRF+LKibBAsYocuHNulxT8CqLQQSQ1weVOeDf++aV9Fb 116nOo2kL8dFF6zFiNBqng4ZfSF5FgKnj2sgsp2PF2tdS1UhnFaS0lzXOhTjfMOnXsM/ vmqw== X-Gm-Message-State: ABuFfohLDkRj3GiMm3aBdn/al3XhXxm776lIVq3YgT3qpaaAlh8cyMvB xHrl2m9enAHNKil9VmZIkXBEG4xFQuI= X-Google-Smtp-Source: ACcGV62H8o9dHtC0NqWRxtfvQqb1y+LsVOEJquOIWcaWA9YgJwfrKX00/vX4ZiG2W5HQ79q3ChcE6Q== X-Received: by 2002:a17:902:ac8e:: with SMTP id h14-v6mr22062416plr.300.1539712169386; Tue, 16 Oct 2018 10:49:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:49:00 -0700 Message-Id: <20181016174911.9052-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62e Subject: [Qemu-devel] [PULL 10/21] cputlb: serialize tlb updates with env->tlb_lock X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 From: "Emilio G. Cota" Currently we rely on atomic operations for cross-CPU invalidations. There are two cases that these atomics miss: cross-CPU invalidations can race with either (1) vCPU threads flushing their TLB, which happens via memset, or (2) vCPUs calling tlb_reset_dirty on their TLB, which updates .addr_write with a regular store. This results in undefined behaviour, since we're mixing regular and atomic ops on concurrent accesses. Fix it by using tlb_lock, a per-vCPU lock. All updaters of tlb_table and the corresponding victim cache now hold the lock. The readers that do not hold tlb_lock must use atomic reads when reading .addr_write, since this field can be updated by other threads; the conversion to atomic reads is done in the next patch. Note that an alternative fix would be to expand the use of atomic ops. However, in the case of TLB flushes this would have a huge performance impact, since (1) TLB flushes can happen very frequently and (2) we currently use a full memory barrier to flush each TLB entry, and a TLB has many entries. Instead, acquiring the lock is barely slower than a full memory barrier since it is uncontended, and with a single lock acquisition we can flush the entire TLB. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota Message-Id: <20181009174557.16125-6-cota@braap.org> Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 3 + accel/tcg/cputlb.c | 155 ++++++++++++++++++++++------------------ 2 files changed, 87 insertions(+), 71 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index a171ffc1a4..4ff62f32bf 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -24,6 +24,7 @@ #endif =20 #include "qemu/host-utils.h" +#include "qemu/thread.h" #include "qemu/queue.h" #ifdef CONFIG_TCG #include "tcg-target.h" @@ -142,6 +143,8 @@ typedef struct CPUIOTLBEntry { =20 #define CPU_COMMON_TLB \ /* The meaning of the MMU modes is defined in the target code. */ \ + /* tlb_lock serializes updates to tlb_table and tlb_v_table */ \ + QemuSpin tlb_lock; \ CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f6b388c961..c2a6190674 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -75,6 +75,9 @@ QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16); =20 void tlb_init(CPUState *cpu) { + CPUArchState *env =3D cpu->env_ptr; + + qemu_spin_init(&env->tlb_lock); } =20 /* flush_all_helper: run fn across all cpus @@ -129,8 +132,17 @@ static void tlb_flush_nocheck(CPUState *cpu) atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); tlb_debug("(count: %zu)\n", tlb_flush_count()); =20 + /* + * tlb_table/tlb_v_table updates from any thread must hold tlb_lock. + * However, updates from the owner thread (as is the case here; see the + * above assert_cpu_is_self) do not need atomic_set because all reads + * that do not hold the lock are performed by the same owner thread. + */ + qemu_spin_lock(&env->tlb_lock); memset(env->tlb_table, -1, sizeof(env->tlb_table)); memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table)); + qemu_spin_unlock(&env->tlb_lock); + cpu_tb_jmp_cache_clear(cpu); =20 env->vtlb_index =3D 0; @@ -182,6 +194,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cp= u, run_on_cpu_data data) =20 tlb_debug("start: mmu_idx:0x%04lx\n", mmu_idx_bitmask); =20 + qemu_spin_lock(&env->tlb_lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { =20 if (test_bit(mmu_idx, &mmu_idx_bitmask)) { @@ -191,6 +204,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cp= u, run_on_cpu_data data) memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[= 0])); } } + qemu_spin_unlock(&env->tlb_lock); =20 cpu_tb_jmp_cache_clear(cpu); =20 @@ -247,19 +261,24 @@ static inline bool tlb_hit_page_anyprot(CPUTLBEntry *= tlb_entry, tlb_hit_page(tlb_entry->addr_code, page); } =20 -static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong pa= ge) +/* Called with tlb_lock held */ +static inline void tlb_flush_entry_locked(CPUTLBEntry *tlb_entry, + target_ulong page) { if (tlb_hit_page_anyprot(tlb_entry, page)) { memset(tlb_entry, -1, sizeof(*tlb_entry)); } } =20 -static inline void tlb_flush_vtlb_page(CPUArchState *env, int mmu_idx, - target_ulong page) +/* Called with tlb_lock held */ +static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_i= dx, + target_ulong page) { int k; + + assert_cpu_is_self(ENV_GET_CPU(env)); for (k =3D 0; k < CPU_VTLB_SIZE; k++) { - tlb_flush_entry(&env->tlb_v_table[mmu_idx][k], page); + tlb_flush_entry_locked(&env->tlb_v_table[mmu_idx][k], page); } } =20 @@ -286,10 +305,12 @@ static void tlb_flush_page_async_work(CPUState *cpu, = run_on_cpu_data data) =20 addr &=3D TARGET_PAGE_MASK; i =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + qemu_spin_lock(&env->tlb_lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); - tlb_flush_vtlb_page(env, mmu_idx, addr); + tlb_flush_entry_locked(&env->tlb_table[mmu_idx][i], addr); + tlb_flush_vtlb_page_locked(env, mmu_idx, addr); } + qemu_spin_unlock(&env->tlb_lock); =20 tb_flush_jmp_cache(cpu, addr); } @@ -326,12 +347,14 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUSt= ate *cpu, tlb_debug("page:%d addr:"TARGET_FMT_lx" mmu_idx:0x%lx\n", page, addr, mmu_idx_bitmap); =20 + qemu_spin_lock(&env->tlb_lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { if (test_bit(mmu_idx, &mmu_idx_bitmap)) { - tlb_flush_entry(&env->tlb_table[mmu_idx][page], addr); - tlb_flush_vtlb_page(env, mmu_idx, addr); + tlb_flush_entry_locked(&env->tlb_table[mmu_idx][page], addr); + tlb_flush_vtlb_page_locked(env, mmu_idx, addr); } } + qemu_spin_unlock(&env->tlb_lock); =20 tb_flush_jmp_cache(cpu, addr); } @@ -454,72 +477,44 @@ void tlb_unprotect_code(ram_addr_t ram_addr) * most usual is detecting writes to code regions which may invalidate * generated code. * - * Because we want other vCPUs to respond to changes straight away we - * update the te->addr_write field atomically. If the TLB entry has - * been changed by the vCPU in the mean time we skip the update. + * Other vCPUs might be reading their TLBs during guest execution, so we u= pdate + * te->addr_write with atomic_set. We don't need to worry about this for + * oversized guests as MTTCG is disabled for them. * - * As this function uses atomic accesses we also need to ensure - * updates to tlb_entries follow the same access rules. We don't need - * to worry about this for oversized guests as MTTCG is disabled for - * them. + * Called with tlb_lock held. */ - -static void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start, - uintptr_t length) +static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry, + uintptr_t start, uintptr_t length) { -#if TCG_OVERSIZED_GUEST uintptr_t addr =3D tlb_entry->addr_write; =20 if ((addr & (TLB_INVALID_MASK | TLB_MMIO | TLB_NOTDIRTY)) =3D=3D 0) { addr &=3D TARGET_PAGE_MASK; addr +=3D tlb_entry->addend; if ((addr - start) < length) { +#if TCG_OVERSIZED_GUEST tlb_entry->addr_write |=3D TLB_NOTDIRTY; - } - } #else - /* paired with atomic_mb_set in tlb_set_page_with_attrs */ - uintptr_t orig_addr =3D atomic_mb_read(&tlb_entry->addr_write); - uintptr_t addr =3D orig_addr; - - if ((addr & (TLB_INVALID_MASK | TLB_MMIO | TLB_NOTDIRTY)) =3D=3D 0) { - addr &=3D TARGET_PAGE_MASK; - addr +=3D atomic_read(&tlb_entry->addend); - if ((addr - start) < length) { - uintptr_t notdirty_addr =3D orig_addr | TLB_NOTDIRTY; - atomic_cmpxchg(&tlb_entry->addr_write, orig_addr, notdirty_add= r); + atomic_set(&tlb_entry->addr_write, + tlb_entry->addr_write | TLB_NOTDIRTY); +#endif } } -#endif } =20 -/* For atomic correctness when running MTTCG we need to use the right - * primitives when copying entries */ -static inline void copy_tlb_helper(CPUTLBEntry *d, CPUTLBEntry *s, - bool atomic_set) +/* + * Called with tlb_lock held. + * Called only from the vCPU context, i.e. the TLB's owner thread. + */ +static inline void copy_tlb_helper_locked(CPUTLBEntry *d, const CPUTLBEntr= y *s) { -#if TCG_OVERSIZED_GUEST *d =3D *s; -#else - if (atomic_set) { - d->addr_read =3D s->addr_read; - d->addr_code =3D s->addr_code; - atomic_set(&d->addend, atomic_read(&s->addend)); - /* Pairs with flag setting in tlb_reset_dirty_range */ - atomic_mb_set(&d->addr_write, atomic_read(&s->addr_write)); - } else { - d->addr_read =3D s->addr_read; - d->addr_write =3D atomic_read(&s->addr_write); - d->addr_code =3D s->addr_code; - d->addend =3D atomic_read(&s->addend); - } -#endif } =20 /* This is a cross vCPU call (i.e. another vCPU resetting the flags of - * the target vCPU). As such care needs to be taken that we don't - * dangerously race with another vCPU update. The only thing actually - * updated is the target TLB entry ->addr_write flags. + * the target vCPU). + * We must take tlb_lock to avoid racing with another vCPU update. The only + * thing actually updated is the target TLB entry ->addr_write flags. */ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) { @@ -528,22 +523,26 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1= , ram_addr_t length) int mmu_idx; =20 env =3D cpu->env_ptr; + qemu_spin_lock(&env->tlb_lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { unsigned int i; =20 for (i =3D 0; i < CPU_TLB_SIZE; i++) { - tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], - start1, length); + tlb_reset_dirty_range_locked(&env->tlb_table[mmu_idx][i], star= t1, + length); } =20 for (i =3D 0; i < CPU_VTLB_SIZE; i++) { - tlb_reset_dirty_range(&env->tlb_v_table[mmu_idx][i], - start1, length); + tlb_reset_dirty_range_locked(&env->tlb_v_table[mmu_idx][i], st= art1, + length); } } + qemu_spin_unlock(&env->tlb_lock); } =20 -static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vad= dr) +/* Called with tlb_lock held */ +static inline void tlb_set_dirty1_locked(CPUTLBEntry *tlb_entry, + target_ulong vaddr) { if (tlb_entry->addr_write =3D=3D (vaddr | TLB_NOTDIRTY)) { tlb_entry->addr_write =3D vaddr; @@ -562,16 +561,18 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) =20 vaddr &=3D TARGET_PAGE_MASK; i =3D (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + qemu_spin_lock(&env->tlb_lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr); + tlb_set_dirty1_locked(&env->tlb_table[mmu_idx][i], vaddr); } =20 for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { int k; for (k =3D 0; k < CPU_VTLB_SIZE; k++) { - tlb_set_dirty1(&env->tlb_v_table[mmu_idx][k], vaddr); + tlb_set_dirty1_locked(&env->tlb_v_table[mmu_idx][k], vaddr); } } + qemu_spin_unlock(&env->tlb_lock); } =20 /* Our TLB does not support large pages, so remember the area covered by @@ -658,9 +659,6 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, addend =3D (uintptr_t)memory_region_get_ram_ptr(section->mr) + xla= t; } =20 - /* Make sure there's no cached translation for the new page. */ - tlb_flush_vtlb_page(env, mmu_idx, vaddr_page); - code_address =3D address; iotlb =3D memory_region_section_get_iotlb(cpu, section, vaddr_page, paddr_page, xlat, prot, &addre= ss); @@ -668,6 +666,18 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulo= ng vaddr, index =3D (vaddr_page >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); te =3D &env->tlb_table[mmu_idx][index]; =20 + /* + * Hold the TLB lock for the rest of the function. We could acquire/re= lease + * the lock several times in the function, but it is faster to amortiz= e the + * acquisition cost by acquiring it just once. Note that this leads to + * a longer critical section, but this is not a concern since the TLB = lock + * is unlikely to be contended. + */ + qemu_spin_lock(&env->tlb_lock); + + /* Make sure there's no cached translation for the new page. */ + tlb_flush_vtlb_page_locked(env, mmu_idx, vaddr_page); + /* * Only evict the old entry to the victim tlb if it's for a * different page; otherwise just overwrite the stale data. @@ -677,7 +687,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, CPUTLBEntry *tv =3D &env->tlb_v_table[mmu_idx][vidx]; =20 /* Evict the old entry into the victim tlb. */ - copy_tlb_helper(tv, te, true); + copy_tlb_helper_locked(tv, te); env->iotlb_v[mmu_idx][vidx] =3D env->iotlb[mmu_idx][index]; } =20 @@ -729,9 +739,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, } } =20 - /* Pairs with flag setting in tlb_reset_dirty_range */ - copy_tlb_helper(te, &tn, true); - /* atomic_mb_set(&te->addr_write, write_address); */ + copy_tlb_helper_locked(te, &tn); + qemu_spin_unlock(&env->tlb_lock); } =20 /* Add a new TLB entry, but without specifying the memory @@ -895,6 +904,8 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mm= u_idx, size_t index, size_t elt_ofs, target_ulong page) { size_t vidx; + + assert_cpu_is_self(ENV_GET_CPU(env)); for (vidx =3D 0; vidx < CPU_VTLB_SIZE; ++vidx) { CPUTLBEntry *vtlb =3D &env->tlb_v_table[mmu_idx][vidx]; target_ulong cmp =3D *(target_ulong *)((uintptr_t)vtlb + elt_ofs); @@ -903,9 +914,11 @@ static bool victim_tlb_hit(CPUArchState *env, size_t m= mu_idx, size_t index, /* Found entry in victim tlb, swap tlb and iotlb. */ CPUTLBEntry tmptlb, *tlb =3D &env->tlb_table[mmu_idx][index]; =20 - copy_tlb_helper(&tmptlb, tlb, false); - copy_tlb_helper(tlb, vtlb, true); - copy_tlb_helper(vtlb, &tmptlb, true); + qemu_spin_lock(&env->tlb_lock); + copy_tlb_helper_locked(&tmptlb, tlb); + copy_tlb_helper_locked(tlb, vtlb); + copy_tlb_helper_locked(vtlb, &tmptlb); + qemu_spin_unlock(&env->tlb_lock); =20 CPUIOTLBEntry tmpio, *io =3D &env->iotlb[mmu_idx][index]; CPUIOTLBEntry *vio =3D &env->iotlb_v[mmu_idx][vidx]; --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539715020489427.8002917338338; Tue, 16 Oct 2018 11:37:00 -0700 (PDT) Received: from localhost ([::1]:59682 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCUDA-0003rb-Jm for importer@patchew.org; Tue, 16 Oct 2018 14:36:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59773) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTTQ-00047y-IQ for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCTTL-00010Q-1S for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:40 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:42978) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gCTTK-0000to-Gf for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:34 -0400 Received: by mail-pl1-x62d.google.com with SMTP id c8-v6so11353825plo.9 for ; Tue, 16 Oct 2018 10:49:32 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=o0Gn4P0MUk+NIJcPA0w+sPPaPE/w/HgOCjbNmj2ovC0=; b=IWTwThINiw9cANrZTA82yxfeHny8XcYLV74A3Z1QVHDkQN6ng+NaSWZPD2pPPis1mx eDY06ewDRCbKBRFPDR2eo9KpxEBZ9mGrQomwq3OH98coU14vLSncTHWCAA+CD7kSx/Po KClCVoKWHwFJypXHdcMJnAjf2mZrydn9MmIEc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o0Gn4P0MUk+NIJcPA0w+sPPaPE/w/HgOCjbNmj2ovC0=; b=Tor+1nHnizN+7ZB0642v+mp6CmRSkT3TPYkv64VlpOUe/yQLO3NpaYVZAPfKVtP5WH qeBe1V4kvaqewm88AhPdinuiYohaCb4aHcpbAHvOy1TUZkyegJj9t4ge3raQ1Abnjeuk SgaZeMRiDiUD5x3mnlzKg9u8MUpQcDCMSP96k01m2/bOourwLaI4rZQh+ENrvzRY4f37 XEZsikiEfrqQztE4LSalReEgkcib3JIh2w8JA1DUJdZiaG7Kb37PRts1MpoF6LJFWjf9 cyt+AJxu9QyCIIAXCMtb1i/3P+pFVK72TCv4e5Jk4KAL4IEmDkG2Y2g8Hds6Jm46TP8g HFyQ== X-Gm-Message-State: ABuFfohcxtXKEWbwPJEsK8DYZp1eRy8rizRksjiyN5F+gQ6Iv+MY+KEr LZ47WLdpEBKCUnpt8f45nDCM4h2He+o= X-Google-Smtp-Source: ACcGV61LejhlgTT4/ytHlZVgsR6bKB+l5rko3Xi1P8OScz7mNR9r0w5lqYQx/PU4mGA2pi217+Z3LA== X-Received: by 2002:a17:902:9a94:: with SMTP id w20-v6mr10238723plp.115.1539712170912; Tue, 16 Oct 2018 10:49:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:49:01 -0700 Message-Id: <20181016174911.9052-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62d Subject: [Qemu-devel] [PULL 11/21] tcg: Add tlb_index and tlb_entry helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G . Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Isolate the computation of an index from an address into a helper before we change that function. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson [ cota: convert tlb_vaddr_to_host; use atomic_read on addr_write ] Signed-off-by: Emilio G. Cota Message-Id: <20181009175129.17888-2-cota@braap.org> --- accel/tcg/softmmu_template.h | 64 +++++++++++++++++--------------- include/exec/cpu_ldst.h | 19 ++++++++-- include/exec/cpu_ldst_template.h | 25 +++++++------ accel/tcg/cputlb.c | 60 ++++++++++++++---------------- 4 files changed, 90 insertions(+), 78 deletions(-) diff --git a/accel/tcg/softmmu_template.h b/accel/tcg/softmmu_template.h index f060a693d4..09538b5349 100644 --- a/accel/tcg/softmmu_template.h +++ b/accel/tcg/softmmu_template.h @@ -111,9 +111,10 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchS= tate *env, WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - unsigned mmu_idx =3D get_mmuidx(oi); - int index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr =3D env->tlb_table[mmu_idx][index].ADDR_READ; + uintptr_t mmu_idx =3D get_mmuidx(oi); + uintptr_t index =3D tlb_index(env, mmu_idx, addr); + CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); + target_ulong tlb_addr =3D entry->ADDR_READ; unsigned a_bits =3D get_alignment_bits(get_memop(oi)); uintptr_t haddr; DATA_TYPE res; @@ -129,7 +130,7 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_u= long addr, tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE, mmu_idx, retaddr); } - tlb_addr =3D env->tlb_table[mmu_idx][index].ADDR_READ; + tlb_addr =3D entry->ADDR_READ; } =20 /* Handle an IO access. */ @@ -166,7 +167,7 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_u= long addr, return res; } =20 - haddr =3D addr + env->tlb_table[mmu_idx][index].addend; + haddr =3D addr + entry->addend; #if DATA_SIZE =3D=3D 1 res =3D glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr); #else @@ -179,9 +180,10 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_= ulong addr, WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - unsigned mmu_idx =3D get_mmuidx(oi); - int index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr =3D env->tlb_table[mmu_idx][index].ADDR_READ; + uintptr_t mmu_idx =3D get_mmuidx(oi); + uintptr_t index =3D tlb_index(env, mmu_idx, addr); + CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); + target_ulong tlb_addr =3D entry->ADDR_READ; unsigned a_bits =3D get_alignment_bits(get_memop(oi)); uintptr_t haddr; DATA_TYPE res; @@ -197,7 +199,7 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_u= long addr, tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE, mmu_idx, retaddr); } - tlb_addr =3D env->tlb_table[mmu_idx][index].ADDR_READ; + tlb_addr =3D entry->ADDR_READ; } =20 /* Handle an IO access. */ @@ -234,7 +236,7 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_u= long addr, return res; } =20 - haddr =3D addr + env->tlb_table[mmu_idx][index].addend; + haddr =3D addr + entry->addend; res =3D glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr); return res; } @@ -275,9 +277,10 @@ static inline void glue(io_write, SUFFIX)(CPUArchState= *env, void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) { - unsigned mmu_idx =3D get_mmuidx(oi); - int index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write; + uintptr_t mmu_idx =3D get_mmuidx(oi); + uintptr_t index =3D tlb_index(env, mmu_idx, addr); + CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); + target_ulong tlb_addr =3D entry->addr_write; unsigned a_bits =3D get_alignment_bits(get_memop(oi)); uintptr_t haddr; =20 @@ -292,7 +295,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, mmu_idx, retaddr); } - tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVA= LID_MASK; + tlb_addr =3D entry->addr_write & ~TLB_INVALID_MASK; } =20 /* Handle an IO access. */ @@ -313,16 +316,16 @@ void helper_le_st_name(CPUArchState *env, target_ulon= g addr, DATA_TYPE val, if (DATA_SIZE > 1 && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 >=3D TARGET_PAGE_SIZE)) { - int i, index2; - target_ulong page2, tlb_addr2; + int i; + target_ulong page2; + CPUTLBEntry *entry2; do_unaligned_access: /* Ensure the second page is in the TLB. Note that the first page is already guaranteed to be filled, and that the second page cannot evict the first. */ page2 =3D (addr + DATA_SIZE) & TARGET_PAGE_MASK; - index2 =3D (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - tlb_addr2 =3D env->tlb_table[mmu_idx][index2].addr_write; - if (!tlb_hit_page(tlb_addr2, page2) + entry2 =3D tlb_entry(env, mmu_idx, page2); + if (!tlb_hit_page(entry2->addr_write, page2) && !VICTIM_TLB_HIT(addr_write, page2)) { tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE, mmu_idx, retaddr); @@ -340,7 +343,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, return; } =20 - haddr =3D addr + env->tlb_table[mmu_idx][index].addend; + haddr =3D addr + entry->addend; #if DATA_SIZE =3D=3D 1 glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val); #else @@ -352,9 +355,10 @@ void helper_le_st_name(CPUArchState *env, target_ulong= addr, DATA_TYPE val, void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) { - unsigned mmu_idx =3D get_mmuidx(oi); - int index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write; + uintptr_t mmu_idx =3D get_mmuidx(oi); + uintptr_t index =3D tlb_index(env, mmu_idx, addr); + CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); + target_ulong tlb_addr =3D entry->addr_write; unsigned a_bits =3D get_alignment_bits(get_memop(oi)); uintptr_t haddr; =20 @@ -369,7 +373,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, mmu_idx, retaddr); } - tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVA= LID_MASK; + tlb_addr =3D entry->addr_write & ~TLB_INVALID_MASK; } =20 /* Handle an IO access. */ @@ -390,16 +394,16 @@ void helper_be_st_name(CPUArchState *env, target_ulon= g addr, DATA_TYPE val, if (DATA_SIZE > 1 && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 >=3D TARGET_PAGE_SIZE)) { - int i, index2; - target_ulong page2, tlb_addr2; + int i; + target_ulong page2; + CPUTLBEntry *entry2; do_unaligned_access: /* Ensure the second page is in the TLB. Note that the first page is already guaranteed to be filled, and that the second page cannot evict the first. */ page2 =3D (addr + DATA_SIZE) & TARGET_PAGE_MASK; - index2 =3D (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - tlb_addr2 =3D env->tlb_table[mmu_idx][index2].addr_write; - if (!tlb_hit_page(tlb_addr2, page2) + entry2 =3D tlb_entry(env, mmu_idx, page2); + if (!tlb_hit_page(entry2->addr_write, page2) && !VICTIM_TLB_HIT(addr_write, page2)) { tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE, mmu_idx, retaddr); @@ -417,7 +421,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, return; } =20 - haddr =3D addr + env->tlb_table[mmu_idx][index].addend; + haddr =3D addr + entry->addend; glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val); } #endif /* DATA_SIZE > 1 */ diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 41ed0526e2..f54d91ff68 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -126,6 +126,20 @@ extern __thread uintptr_t helper_retaddr; /* The memory helpers for tcg-generated code need tcg_target_long etc. */ #include "tcg.h" =20 +/* Find the TLB index corresponding to the mmu_idx + address pair. */ +static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx, + target_ulong addr) +{ + return (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); +} + +/* Find the TLB entry corresponding to the mmu_idx + address pair. */ +static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, + target_ulong addr) +{ + return &env->tlb_table[mmu_idx][tlb_index(env, mmu_idx, addr)]; +} + #ifdef MMU_MODE0_SUFFIX #define CPU_MMU_INDEX 0 #define MEMSUFFIX MMU_MODE0_SUFFIX @@ -416,8 +430,7 @@ static inline void *tlb_vaddr_to_host(CPUArchState *env= , abi_ptr addr, #if defined(CONFIG_USER_ONLY) return g2h(addr); #else - int index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - CPUTLBEntry *tlbentry =3D &env->tlb_table[mmu_idx][index]; + CPUTLBEntry *tlbentry =3D tlb_entry(env, mmu_idx, addr); abi_ptr tlb_addr; uintptr_t haddr; =20 @@ -445,7 +458,7 @@ static inline void *tlb_vaddr_to_host(CPUArchState *env= , abi_ptr addr, return NULL; } =20 - haddr =3D addr + env->tlb_table[mmu_idx][index].addend; + haddr =3D addr + tlbentry->addend; return (void *)haddr; #endif /* defined(CONFIG_USER_ONLY) */ } diff --git a/include/exec/cpu_ldst_template.h b/include/exec/cpu_ldst_templ= ate.h index 4db2302962..d21a0b59bf 100644 --- a/include/exec/cpu_ldst_template.h +++ b/include/exec/cpu_ldst_template.h @@ -81,7 +81,7 @@ glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArch= State *env, target_ulong ptr, uintptr_t retaddr) { - int page_index; + CPUTLBEntry *entry; RES_TYPE res; target_ulong addr; int mmu_idx; @@ -94,15 +94,15 @@ glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUAr= chState *env, #endif =20 addr =3D ptr; - page_index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx =3D CPU_MMU_INDEX; - if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=3D + entry =3D tlb_entry(env, mmu_idx, addr); + if (unlikely(entry->ADDR_READ !=3D (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) { oi =3D make_memop_idx(SHIFT, mmu_idx); res =3D glue(glue(helper_ret_ld, URETSUFFIX), MMUSUFFIX)(env, addr, oi, retaddr); } else { - uintptr_t hostaddr =3D addr + env->tlb_table[mmu_idx][page_index].= addend; + uintptr_t hostaddr =3D addr + entry->addend; res =3D glue(glue(ld, USUFFIX), _p)((uint8_t *)hostaddr); } return res; @@ -120,7 +120,8 @@ glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUAr= chState *env, target_ulong ptr, uintptr_t retaddr) { - int res, page_index; + CPUTLBEntry *entry; + int res; target_ulong addr; int mmu_idx; TCGMemOpIdx oi; @@ -132,15 +133,15 @@ glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPU= ArchState *env, #endif =20 addr =3D ptr; - page_index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx =3D CPU_MMU_INDEX; - if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=3D + entry =3D tlb_entry(env, mmu_idx, addr); + if (unlikely(entry->ADDR_READ !=3D (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) { oi =3D make_memop_idx(SHIFT, mmu_idx); res =3D (DATA_STYPE)glue(glue(helper_ret_ld, SRETSUFFIX), MMUSUFFIX)(env, addr, oi, retaddr); } else { - uintptr_t hostaddr =3D addr + env->tlb_table[mmu_idx][page_index].= addend; + uintptr_t hostaddr =3D addr + entry->addend; res =3D glue(glue(lds, SUFFIX), _p)((uint8_t *)hostaddr); } return res; @@ -162,7 +163,7 @@ glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArc= hState *env, target_ulong ptr, RES_TYPE v, uintptr_t ret= addr) { - int page_index; + CPUTLBEntry *entry; target_ulong addr; int mmu_idx; TCGMemOpIdx oi; @@ -174,15 +175,15 @@ glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUA= rchState *env, #endif =20 addr =3D ptr; - page_index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx =3D CPU_MMU_INDEX; - if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write !=3D + entry =3D tlb_entry(env, mmu_idx, addr); + if (unlikely(entry->addr_write !=3D (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) { oi =3D make_memop_idx(SHIFT, mmu_idx); glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(env, addr, v, oi, retaddr); } else { - uintptr_t hostaddr =3D addr + env->tlb_table[mmu_idx][page_index].= addend; + uintptr_t hostaddr =3D addr + entry->addend; glue(glue(st, SUFFIX), _p)((uint8_t *)hostaddr, v); } } diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c2a6190674..e4993d72fb 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -286,7 +286,6 @@ static void tlb_flush_page_async_work(CPUState *cpu, ru= n_on_cpu_data data) { CPUArchState *env =3D cpu->env_ptr; target_ulong addr =3D (target_ulong) data.target_ptr; - int i; int mmu_idx; =20 assert_cpu_is_self(cpu); @@ -304,10 +303,9 @@ static void tlb_flush_page_async_work(CPUState *cpu, r= un_on_cpu_data data) } =20 addr &=3D TARGET_PAGE_MASK; - i =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); qemu_spin_lock(&env->tlb_lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - tlb_flush_entry_locked(&env->tlb_table[mmu_idx][i], addr); + tlb_flush_entry_locked(tlb_entry(env, mmu_idx, addr), addr); tlb_flush_vtlb_page_locked(env, mmu_idx, addr); } qemu_spin_unlock(&env->tlb_lock); @@ -339,18 +337,17 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUSt= ate *cpu, target_ulong addr_and_mmuidx =3D (target_ulong) data.target_ptr; target_ulong addr =3D addr_and_mmuidx & TARGET_PAGE_MASK; unsigned long mmu_idx_bitmap =3D addr_and_mmuidx & ALL_MMUIDX_BITS; - int page =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); int mmu_idx; =20 assert_cpu_is_self(cpu); =20 - tlb_debug("page:%d addr:"TARGET_FMT_lx" mmu_idx:0x%lx\n", - page, addr, mmu_idx_bitmap); + tlb_debug("flush page addr:"TARGET_FMT_lx" mmu_idx:0x%lx\n", + addr, mmu_idx_bitmap); =20 qemu_spin_lock(&env->tlb_lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { if (test_bit(mmu_idx, &mmu_idx_bitmap)) { - tlb_flush_entry_locked(&env->tlb_table[mmu_idx][page], addr); + tlb_flush_entry_locked(tlb_entry(env, mmu_idx, addr), addr); tlb_flush_vtlb_page_locked(env, mmu_idx, addr); } } @@ -554,16 +551,14 @@ static inline void tlb_set_dirty1_locked(CPUTLBEntry = *tlb_entry, void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) { CPUArchState *env =3D cpu->env_ptr; - int i; int mmu_idx; =20 assert_cpu_is_self(cpu); =20 vaddr &=3D TARGET_PAGE_MASK; - i =3D (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); qemu_spin_lock(&env->tlb_lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - tlb_set_dirty1_locked(&env->tlb_table[mmu_idx][i], vaddr); + tlb_set_dirty1_locked(tlb_entry(env, mmu_idx, vaddr), vaddr); } =20 for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { @@ -663,8 +658,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, iotlb =3D memory_region_section_get_iotlb(cpu, section, vaddr_page, paddr_page, xlat, prot, &addre= ss); =20 - index =3D (vaddr_page >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - te =3D &env->tlb_table[mmu_idx][index]; + index =3D tlb_index(env, mmu_idx, vaddr_page); + te =3D tlb_entry(env, mmu_idx, vaddr_page); =20 /* * Hold the TLB lock for the rest of the function. We could acquire/re= lease @@ -786,16 +781,16 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBE= ntry *iotlbentry, * repeat the MMU check here. This tlb_fill() call might * longjump out if this access should cause a guest exception. */ - int index; + CPUTLBEntry *entry; target_ulong tlb_addr; =20 tlb_fill(cpu, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); =20 - index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - tlb_addr =3D env->tlb_table[mmu_idx][index].addr_read; + entry =3D tlb_entry(env, mmu_idx, addr); + tlb_addr =3D entry->addr_read; if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) { /* RAM access */ - uintptr_t haddr =3D addr + env->tlb_table[mmu_idx][index].adde= nd; + uintptr_t haddr =3D addr + entry->addend; =20 return ldn_p((void *)haddr, size); } @@ -853,16 +848,16 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntr= y *iotlbentry, * repeat the MMU check here. This tlb_fill() call might * longjump out if this access should cause a guest exception. */ - int index; + CPUTLBEntry *entry; target_ulong tlb_addr; =20 tlb_fill(cpu, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); =20 - index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write; + entry =3D tlb_entry(env, mmu_idx, addr); + tlb_addr =3D entry->addr_write; if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) { /* RAM access */ - uintptr_t haddr =3D addr + env->tlb_table[mmu_idx][index].adde= nd; + uintptr_t haddr =3D addr + entry->addend; =20 stn_p((void *)haddr, size, val); return; @@ -941,20 +936,19 @@ static bool victim_tlb_hit(CPUArchState *env, size_t = mmu_idx, size_t index, */ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) { - int mmu_idx, index; + uintptr_t mmu_idx =3D cpu_mmu_index(env, true); + uintptr_t index =3D tlb_index(env, mmu_idx, addr); + CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); void *p; =20 - index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - mmu_idx =3D cpu_mmu_index(env, true); - if (unlikely(!tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr))= ) { + if (unlikely(!tlb_hit(entry->addr_code, addr))) { if (!VICTIM_TLB_HIT(addr_code, addr)) { tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0= ); } - assert(tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr)); + assert(tlb_hit(entry->addr_code, addr)); } =20 - if (unlikely(env->tlb_table[mmu_idx][index].addr_code & - (TLB_RECHECK | TLB_MMIO))) { + if (unlikely(entry->addr_code & (TLB_RECHECK | TLB_MMIO))) { /* * Return -1 if we can't translate and execute from an entire * page of RAM here, which will cause us to execute by loading @@ -966,7 +960,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, ta= rget_ulong addr) return -1; } =20 - p =3D (void *)((uintptr_t)addr + env->tlb_table[mmu_idx][index].addend= ); + p =3D (void *)((uintptr_t)addr + entry->addend); return qemu_ram_addr_from_host_nofail(p); } =20 @@ -979,10 +973,10 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, = target_ulong addr) void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_i= dx, uintptr_t retaddr) { - int index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write; + uintptr_t index =3D tlb_index(env, mmu_idx, addr); + CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); =20 - if (!tlb_hit(tlb_addr, addr)) { + if (!tlb_hit(entry->addr_write, addr)) { /* TLB entry is for a different page */ if (!VICTIM_TLB_HIT(addr_write, addr)) { tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE, @@ -998,8 +992,8 @@ static void *atomic_mmu_lookup(CPUArchState *env, targe= t_ulong addr, NotDirtyInfo *ndi) { size_t mmu_idx =3D get_mmuidx(oi); - size_t index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - CPUTLBEntry *tlbe =3D &env->tlb_table[mmu_idx][index]; + uintptr_t index =3D tlb_index(env, mmu_idx, addr); + CPUTLBEntry *tlbe =3D tlb_entry(env, mmu_idx, addr); target_ulong tlb_addr =3D tlbe->addr_write; TCGMemOp mop =3D get_memop(oi); int a_bits =3D get_alignment_bits(mop); --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539713263350542.6282057519788; Tue, 16 Oct 2018 11:07:43 -0700 (PDT) Received: from localhost ([::1]:59484 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTkr-0002Ou-VB for importer@patchew.org; Tue, 16 Oct 2018 14:07:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59725) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTTP-00046x-M0 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCTTL-00010d-2e for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:39 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:38067) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gCTTK-0000wY-MJ for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:34 -0400 Received: by mail-pg1-x532.google.com with SMTP id f8-v6so11197880pgq.5 for ; Tue, 16 Oct 2018 10:49:33 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PCmtFGzAQFVJC59+lCU2eXtnA4WHfu0lUi+CVh16Ypc=; b=WpLJlpsojkBkNSvay18eMD8izL/tPtIJt1pIYwkh1JwuO19Ju0wUjBEvqiets3CyG5 4/TyCjyDY6TaYQTVgqOYGtIywS6hjZtnS+is0NHsF9H4gdxIX2UxNIuzPeo3fEJIOY2c I4elLMLKD3yP29X8ZGEVacMawajeOWGbLf8DM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PCmtFGzAQFVJC59+lCU2eXtnA4WHfu0lUi+CVh16Ypc=; b=lwmdQRJmdv0NkmfI4m2lSe8i/xic9xZ2P0bCLS072dhe3jR0CaWZqRWy6vpsbBDstR qagYoEgHgeGvUkGt9A9AuKcjpJJUvRcDaPGfDuhXlQlFiP8JsatBP2MlsEbGS+KzPuEW EhLEVeLpkFzbrJU17KAXhNkmK6ak8ZHrLfc4WkQZgtPMH1iSTBZTzdaoB2CDz6cof3aE oTNwszpGkg+1Cin+AwKUCpWhdTA5/WhgcAUEftRHpDx2TI1r+VXn98wBiA6zntFghYiD 5ChMwGFPu02KHH9jdDyKtv5ngROpMe0u99f/mDEKavGt19zglHz0Qofp/FJWlbf4jNMG pf9Q== X-Gm-Message-State: ABuFfoiBxlne4iEIMxQn6XQ1D4sfAcWfYEN9KqBw8HIYobSMdWr7CXkD ppe/ISQrgFVsZzu2MrHz2v+2j+X7YK4= X-Google-Smtp-Source: ACcGV61TemvBOIzVsjvzRlNuX5/UPUIglxZnxdB2zRXDuECTAyPl7ZU3euf3WizbHQqOa/yysi7qOQ== X-Received: by 2002:a63:a902:: with SMTP id u2-v6mr21177130pge.207.1539712172133; Tue, 16 Oct 2018 10:49:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:49:02 -0700 Message-Id: <20181016174911.9052-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::532 Subject: [Qemu-devel] [PULL 12/21] tcg: Split CONFIG_ATOMIC128 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" GCC7+ will no longer advertise support for 16-byte __atomic operations if only cmpxchg is supported, as for x86_64. Fortunately, x86_64 still has support for __sync_compare_and_swap_16 and we can make use of that. AArch64 does not have, nor ever has had such support, so open-code it. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 20 ++++- include/qemu/atomic128.h | 155 ++++++++++++++++++++++++++++++++++++ tcg/tcg.h | 16 ++-- accel/tcg/cputlb.c | 3 +- accel/tcg/user-exec.c | 5 +- configure | 19 +++++ 6 files changed, 204 insertions(+), 14 deletions(-) create mode 100644 include/qemu/atomic128.h diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index d751bcba48..efde12fdb2 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -100,19 +100,24 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, targ= et_ulong addr, DATA_TYPE ret; =20 ATOMIC_TRACE_RMW; +#if DATA_SIZE =3D=3D 16 + ret =3D atomic16_cmpxchg(haddr, cmpv, newv); +#else ret =3D atomic_cmpxchg__nocheck(haddr, cmpv, newv); +#endif ATOMIC_MMU_CLEANUP; return ret; } =20 #if DATA_SIZE >=3D 16 +#if HAVE_ATOMIC128 ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr EXTRA_ARGS) { ATOMIC_MMU_DECLS; DATA_TYPE val, *haddr =3D ATOMIC_MMU_LOOKUP; =20 ATOMIC_TRACE_LD; - __atomic_load(haddr, &val, __ATOMIC_RELAXED); + val =3D atomic16_read(haddr); ATOMIC_MMU_CLEANUP; return val; } @@ -124,9 +129,10 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong a= ddr, DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; =20 ATOMIC_TRACE_ST; - __atomic_store(haddr, &val, __ATOMIC_RELAXED); + atomic16_set(haddr, val); ATOMIC_MMU_CLEANUP; } +#endif #else ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val EXTRA_ARGS) @@ -228,19 +234,24 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, targ= et_ulong addr, DATA_TYPE ret; =20 ATOMIC_TRACE_RMW; +#if DATA_SIZE =3D=3D 16 + ret =3D atomic16_cmpxchg(haddr, BSWAP(cmpv), BSWAP(newv)); +#else ret =3D atomic_cmpxchg__nocheck(haddr, BSWAP(cmpv), BSWAP(newv)); +#endif ATOMIC_MMU_CLEANUP; return BSWAP(ret); } =20 #if DATA_SIZE >=3D 16 +#if HAVE_ATOMIC128 ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr EXTRA_ARGS) { ATOMIC_MMU_DECLS; DATA_TYPE val, *haddr =3D ATOMIC_MMU_LOOKUP; =20 ATOMIC_TRACE_LD; - __atomic_load(haddr, &val, __ATOMIC_RELAXED); + val =3D atomic16_read(haddr); ATOMIC_MMU_CLEANUP; return BSWAP(val); } @@ -253,9 +264,10 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong a= ddr, =20 ATOMIC_TRACE_ST; val =3D BSWAP(val); - __atomic_store(haddr, &val, __ATOMIC_RELAXED); + atomic16_set(haddr, val); ATOMIC_MMU_CLEANUP; } +#endif #else ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val EXTRA_ARGS) diff --git a/include/qemu/atomic128.h b/include/qemu/atomic128.h new file mode 100644 index 0000000000..fdea225132 --- /dev/null +++ b/include/qemu/atomic128.h @@ -0,0 +1,155 @@ +/* + * Simple interface for 128-bit atomic operations. + * + * Copyright (C) 2018 Linaro, Ltd. + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + * See docs/devel/atomics.txt for discussion about the guarantees each + * atomic primitive is meant to provide. + */ + +#ifndef QEMU_ATOMIC128_H +#define QEMU_ATOMIC128_H + +/* + * GCC is a house divided about supporting large atomic operations. + * + * For hosts that only have large compare-and-swap, a legalistic reading + * of the C++ standard means that one cannot implement __atomic_read on + * read-only memory, and thus all atomic operations must synchronize + * through libatomic. + * + * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D80878 + * + * This interpretation is not especially helpful for QEMU. + * For softmmu, all RAM is always read/write from the hypervisor. + * For user-only, if the guest doesn't implement such an __atomic_read + * then the host need not worry about it either. + * + * Moreover, using libatomic is not an option, because its interface is + * built for std::atomic, and requires that *all* accesses to such an + * object go through the library. In our case we do not have an object + * in the C/C++ sense, but a view of memory as seen by the guest. + * The guest may issue a large atomic operation and then access those + * pieces using word-sized accesses. From the hypervisor, we have no + * way to connect those two actions. + * + * Therefore, special case each platform. + */ + +#if defined(CONFIG_ATOMIC128) +static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) +{ + return atomic_cmpxchg__nocheck(ptr, cmp, new); +} +# define HAVE_CMPXCHG128 1 +#elif defined(CONFIG_CMPXCHG128) +static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) +{ + return __sync_val_compare_and_swap_16(ptr, cmp, new); +} +# define HAVE_CMPXCHG128 1 +#elif defined(__aarch64__) +/* Through gcc 8, aarch64 has no support for 128-bit at all. */ +static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) +{ + uint64_t cmpl =3D int128_getlo(cmp), cmph =3D int128_gethi(cmp); + uint64_t newl =3D int128_getlo(new), newh =3D int128_gethi(new); + uint64_t oldl, oldh; + uint32_t tmp; + + asm("0: ldaxp %[oldl], %[oldh], %[mem]\n\t" + "cmp %[oldl], %[cmpl]\n\t" + "ccmp %[oldh], %[cmph], #0, eq\n\t" + "b.ne 1f\n\t" + "stlxp %w[tmp], %[newl], %[newh], %[mem]\n\t" + "cbnz %w[tmp], 0b\n" + "1:" + : [mem] "+m"(*ptr), [tmp] "=3D&r"(tmp), + [oldl] "=3D&r"(oldl), [oldh] "=3Dr"(oldh) + : [cmpl] "r"(cmpl), [cmph] "r"(cmph), + [newl] "r"(newl), [newh] "r"(newh) + : "memory", "cc"); + + return int128_make128(oldl, oldh); +} +# define HAVE_CMPXCHG128 1 +#else +/* Fallback definition that must be optimized away, or error. */ +Int128 __attribute__((error("unsupported atomic"))) + atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new); +# define HAVE_CMPXCHG128 0 +#endif /* Some definition for HAVE_CMPXCHG128 */ + + +#if defined(CONFIG_ATOMIC128) +static inline Int128 atomic16_read(Int128 *ptr) +{ + return atomic_read__nocheck(ptr); +} + +static inline void atomic16_set(Int128 *ptr, Int128 val) +{ + atomic_set__nocheck(ptr, val); +} + +# define HAVE_ATOMIC128 1 +#elif !defined(CONFIG_USER_ONLY) && defined(__aarch64__) +/* We can do better than cmpxchg for AArch64. */ +static inline Int128 atomic16_read(Int128 *ptr) +{ + uint64_t l, h; + uint32_t tmp; + + /* The load must be paired with the store to guarantee not tearing. */ + asm("0: ldxp %[l], %[h], %[mem]\n\t" + "stxp %w[tmp], %[l], %[h], %[mem]\n\t" + "cbnz %w[tmp], 0b" + : [mem] "+m"(*ptr), [tmp] "=3Dr"(tmp), [l] "=3Dr"(l), [h] "=3Dr"(h= )); + + return int128_make128(l, h); +} + +static inline void atomic16_set(Int128 *ptr, Int128 val) +{ + uint64_t l =3D int128_getlo(val), h =3D int128_gethi(val); + uint64_t t1, t2; + + /* Load into temporaries to acquire the exclusive access lock. */ + asm("0: ldxp %[t1], %[t2], %[mem]\n\t" + "stxp %w[t1], %[l], %[h], %[mem]\n\t" + "cbnz %w[t1], 0b" + : [mem] "+m"(*ptr), [t1] "=3D&r"(t1), [t2] "=3D&r"(t2) + : [l] "r"(l), [h] "r"(h)); +} + +# define HAVE_ATOMIC128 1 +#elif !defined(CONFIG_USER_ONLY) && HAVE_CMPXCHG128 +static inline Int128 atomic16_read(Int128 *ptr) +{ + /* Maybe replace 0 with 0, returning the old value. */ + return atomic16_cmpxchg(ptr, 0, 0); +} + +static inline void atomic16_set(Int128 *ptr, Int128 val) +{ + Int128 old =3D *ptr, cmp; + do { + cmp =3D old; + old =3D atomic16_cmpxchg(ptr, cmp, val); + } while (old !=3D cmp); +} + +# define HAVE_ATOMIC128 1 +#else +/* Fallback definitions that must be optimized away, or error. */ +Int128 __attribute__((error("unsupported atomic"))) + atomic16_read(Int128 *ptr); +void __attribute__((error("unsupported atomic"))) + atomic16_set(Int128 *ptr, Int128 val); +# define HAVE_ATOMIC128 0 +#endif /* Some definition for HAVE_ATOMIC128 */ + +#endif /* QEMU_ATOMIC128_H */ diff --git a/tcg/tcg.h b/tcg/tcg.h index c59f254e27..f4efbaa680 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -32,6 +32,7 @@ #include "qemu/queue.h" #include "tcg-mo.h" #include "tcg-target.h" +#include "qemu/int128.h" =20 /* XXX: make safe guess about sizes */ #define MAX_OP_PER_INSTR 266 @@ -1456,11 +1457,14 @@ GEN_ATOMIC_HELPER_ALL(xchg) #undef GEN_ATOMIC_HELPER #endif /* CONFIG_SOFTMMU */ =20 -#ifdef CONFIG_ATOMIC128 -#include "qemu/int128.h" - -/* These aren't really a "proper" helpers because TCG cannot manage Int128. - However, use the same format as the others, for use by the backends. */ +/* + * These aren't really a "proper" helpers because TCG cannot manage Int128. + * However, use the same format as the others, for use by the backends. + * + * The cmpxchg functions are only defined if HAVE_CMPXCHG128; + * the ld/st functions are only defined if HAVE_ATOMIC128, + * as defined by . + */ Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr, Int128 cmpv, Int128 newv, TCGMemOpIdx oi, uintptr_t retaddr); @@ -1477,6 +1481,4 @@ void helper_atomic_sto_le_mmu(CPUArchState *env, targ= et_ulong addr, Int128 val, void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128= val, TCGMemOpIdx oi, uintptr_t retaddr); =20 -#endif /* CONFIG_ATOMIC128 */ - #endif /* TCG_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e4993d72fb..28b770a404 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -32,6 +32,7 @@ #include "exec/log.h" #include "exec/helper-proto.h" #include "qemu/atomic.h" +#include "qemu/atomic128.h" =20 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ @@ -1112,7 +1113,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, #include "atomic_template.h" #endif =20 -#ifdef CONFIG_ATOMIC128 +#if HAVE_CMPXCHG128 || HAVE_ATOMIC128 #define DATA_SIZE 16 #include "atomic_template.h" #endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 26a3ffbba1..cd75829cf2 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -25,6 +25,7 @@ #include "exec/cpu_ldst.h" #include "translate-all.h" #include "exec/helper-proto.h" +#include "qemu/atomic128.h" =20 #undef EAX #undef ECX @@ -615,7 +616,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, targe= t_ulong addr, /* The following is only callable from other helpers, and matches up with the softmmu version. */ =20 -#ifdef CONFIG_ATOMIC128 +#if HAVE_ATOMIC128 || HAVE_CMPXCHG128 =20 #undef EXTRA_ARGS #undef ATOMIC_NAME @@ -628,4 +629,4 @@ static void *atomic_mmu_lookup(CPUArchState *env, targe= t_ulong addr, =20 #define DATA_SIZE 16 #include "atomic_template.h" -#endif /* CONFIG_ATOMIC128 */ +#endif diff --git a/configure b/configure index 8af2be959f..03bf719ca7 100755 --- a/configure +++ b/configure @@ -5160,6 +5160,21 @@ EOF fi fi =20 +cmpxchg128=3Dno +if test "$int128" =3D yes -a "$atomic128" =3D no; then + cat > $TMPC << EOF +int main(void) +{ + unsigned __int128 x =3D 0, y =3D 0; + __sync_val_compare_and_swap_16(&x, y, x); + return 0; +} +EOF + if compile_prog "" "" ; then + cmpxchg128=3Dyes + fi +fi + ######################################### # See if 64-bit atomic operations are supported. # Note that without __atomic builtins, we can only @@ -6669,6 +6684,10 @@ if test "$atomic128" =3D "yes" ; then echo "CONFIG_ATOMIC128=3Dy" >> $config_host_mak fi =20 +if test "$cmpxchg128" =3D "yes" ; then + echo "CONFIG_CMPXCHG128=3Dy" >> $config_host_mak +fi + if test "$atomic64" =3D "yes" ; then echo "CONFIG_ATOMIC64=3Dy" >> $config_host_mak fi --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:4864:20::530 Subject: [Qemu-devel] [PULL 13/21] target/i386: Convert to HAVE_CMPXCHG128 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Reviewed-by: Emilio G. Cota Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/i386/mem_helper.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/i386/mem_helper.c b/target/i386/mem_helper.c index 30c26b9d9c..6cc53bcb40 100644 --- a/target/i386/mem_helper.c +++ b/target/i386/mem_helper.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "qemu/int128.h" +#include "qemu/atomic128.h" #include "tcg.h" =20 void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0) @@ -137,10 +138,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong = a0) =20 if ((a0 & 0xf) !=3D 0) { raise_exception_ra(env, EXCP0D_GPF, ra); - } else { -#ifndef CONFIG_ATOMIC128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else + } else if (HAVE_CMPXCHG128) { int eflags =3D cpu_cc_compute_all(env, CC_OP); =20 Int128 cmpv =3D int128_make128(env->regs[R_EAX], env->regs[R_EDX]); @@ -159,7 +157,8 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a= 0) eflags &=3D ~CC_Z; } CC_SRC =3D eflags; -#endif + } else { + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); } } #endif --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539714046010144.05844495207884; Tue, 16 Oct 2018 11:20:46 -0700 (PDT) Received: from localhost ([::1]:59558 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTxP-000757-IE for importer@patchew.org; Tue, 16 Oct 2018 14:20:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59750) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTTQ-00047O-4W for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCTTM-000146-RC for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:39 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:38069) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gCTTM-00011w-HI for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:36 -0400 Received: by mail-pg1-x534.google.com with SMTP id f8-v6so11197932pgq.5 for ; Tue, 16 Oct 2018 10:49:36 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::534 Subject: [Qemu-devel] [PULL 14/21] target/arm: Convert to HAVE_CMPXCHG128 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 259 +++++++++++++++++++++------------------- 1 file changed, 133 insertions(+), 126 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 7f6ad3000b..6e4e1b8a19 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -30,6 +30,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "qemu/int128.h" +#include "qemu/atomic128.h" #include "tcg.h" #include "fpu/softfloat.h" #include /* For crc32 */ @@ -509,189 +510,195 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t v= al, uint32_t bytes) return crc32c(acc, buf, bytes) ^ 0xffffffff; } =20 -/* Returns 0 on success; 1 otherwise. */ -static uint64_t do_paired_cmpxchg64_le(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi, - bool parallel, uintptr_t ra) +uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, + uint64_t new_lo, uint64_t new_hi) { - Int128 oldv, cmpv, newv; + Int128 cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high= ); + Int128 newv =3D int128_make128(new_lo, new_hi); + Int128 oldv; + uintptr_t ra =3D GETPC(); + uint64_t o0, o1; bool success; =20 - cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); - newv =3D int128_make128(new_lo, new_hi); - - if (parallel) { -#ifndef CONFIG_ATOMIC128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); - oldv =3D helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, = ra); - success =3D int128_eq(oldv, cmpv); -#endif - } else { - uint64_t o0, o1; - #ifdef CONFIG_USER_ONLY - /* ??? Enforce alignment. */ - uint64_t *haddr =3D g2h(addr); + /* ??? Enforce alignment. */ + uint64_t *haddr =3D g2h(addr); =20 - helper_retaddr =3D ra; - o0 =3D ldq_le_p(haddr + 0); - o1 =3D ldq_le_p(haddr + 1); - oldv =3D int128_make128(o0, o1); + helper_retaddr =3D ra; + o0 =3D ldq_le_p(haddr + 0); + o1 =3D ldq_le_p(haddr + 1); + oldv =3D int128_make128(o0, o1); =20 - success =3D int128_eq(oldv, cmpv); - if (success) { - stq_le_p(haddr + 0, int128_getlo(newv)); - stq_le_p(haddr + 1, int128_gethi(newv)); - } - helper_retaddr =3D 0; -#else - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi0 =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); - TCGMemOpIdx oi1 =3D make_memop_idx(MO_LEQ, mem_idx); - - o0 =3D helper_le_ldq_mmu(env, addr + 0, oi0, ra); - o1 =3D helper_le_ldq_mmu(env, addr + 8, oi1, ra); - oldv =3D int128_make128(o0, o1); - - success =3D int128_eq(oldv, cmpv); - if (success) { - helper_le_stq_mmu(env, addr + 0, int128_getlo(newv), oi1, ra); - helper_le_stq_mmu(env, addr + 8, int128_gethi(newv), oi1, ra); - } -#endif + success =3D int128_eq(oldv, cmpv); + if (success) { + stq_le_p(haddr + 0, int128_getlo(newv)); + stq_le_p(haddr + 1, int128_gethi(newv)); } + helper_retaddr =3D 0; +#else + int mem_idx =3D cpu_mmu_index(env, false); + TCGMemOpIdx oi0 =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); + TCGMemOpIdx oi1 =3D make_memop_idx(MO_LEQ, mem_idx); + + o0 =3D helper_le_ldq_mmu(env, addr + 0, oi0, ra); + o1 =3D helper_le_ldq_mmu(env, addr + 8, oi1, ra); + oldv =3D int128_make128(o0, o1); + + success =3D int128_eq(oldv, cmpv); + if (success) { + helper_le_stq_mmu(env, addr + 0, int128_getlo(newv), oi1, ra); + helper_le_stq_mmu(env, addr + 8, int128_gethi(newv), oi1, ra); + } +#endif =20 return !success; } =20 -uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t ne= w_hi) -{ - return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, false, GETPC(= )); -} - uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t a= ddr, uint64_t new_lo, uint64_t ne= w_hi) -{ - return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, true, GETPC()= ); -} - -static uint64_t do_paired_cmpxchg64_be(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi, - bool parallel, uintptr_t ra) { Int128 oldv, cmpv, newv; + uintptr_t ra =3D GETPC(); bool success; + int mem_idx; + TCGMemOpIdx oi; =20 - /* high and low need to be switched here because this is not actually a - * 128bit store but two doublewords stored consecutively - */ - cmpv =3D int128_make128(env->exclusive_high, env->exclusive_val); - newv =3D int128_make128(new_hi, new_lo); - - if (parallel) { -#ifndef CONFIG_ATOMIC128 + if (!HAVE_CMPXCHG128) { cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); - oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, = ra); - success =3D int128_eq(oldv, cmpv); -#endif - } else { - uint64_t o0, o1; - -#ifdef CONFIG_USER_ONLY - /* ??? Enforce alignment. */ - uint64_t *haddr =3D g2h(addr); - - helper_retaddr =3D ra; - o1 =3D ldq_be_p(haddr + 0); - o0 =3D ldq_be_p(haddr + 1); - oldv =3D int128_make128(o0, o1); - - success =3D int128_eq(oldv, cmpv); - if (success) { - stq_be_p(haddr + 0, int128_gethi(newv)); - stq_be_p(haddr + 1, int128_getlo(newv)); - } - helper_retaddr =3D 0; -#else - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi0 =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); - TCGMemOpIdx oi1 =3D make_memop_idx(MO_BEQ, mem_idx); - - o1 =3D helper_be_ldq_mmu(env, addr + 0, oi0, ra); - o0 =3D helper_be_ldq_mmu(env, addr + 8, oi1, ra); - oldv =3D int128_make128(o0, o1); - - success =3D int128_eq(oldv, cmpv); - if (success) { - helper_be_stq_mmu(env, addr + 0, int128_gethi(newv), oi1, ra); - helper_be_stq_mmu(env, addr + 8, int128_getlo(newv), oi1, ra); - } -#endif } =20 + mem_idx =3D cpu_mmu_index(env, false); + oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); + + cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); + newv =3D int128_make128(new_lo, new_hi); + oldv =3D helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra); + + success =3D int128_eq(oldv, cmpv); return !success; } =20 uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, uint64_t new_lo, uint64_t new_hi) { - return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, false, GETPC(= )); + /* + * High and low need to be switched here because this is not actually a + * 128bit store but two doublewords stored consecutively + */ + Int128 cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high= ); + Int128 newv =3D int128_make128(new_lo, new_hi); + Int128 oldv; + uintptr_t ra =3D GETPC(); + uint64_t o0, o1; + bool success; + +#ifdef CONFIG_USER_ONLY + /* ??? Enforce alignment. */ + uint64_t *haddr =3D g2h(addr); + + helper_retaddr =3D ra; + o1 =3D ldq_be_p(haddr + 0); + o0 =3D ldq_be_p(haddr + 1); + oldv =3D int128_make128(o0, o1); + + success =3D int128_eq(oldv, cmpv); + if (success) { + stq_be_p(haddr + 0, int128_gethi(newv)); + stq_be_p(haddr + 1, int128_getlo(newv)); + } + helper_retaddr =3D 0; +#else + int mem_idx =3D cpu_mmu_index(env, false); + TCGMemOpIdx oi0 =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); + TCGMemOpIdx oi1 =3D make_memop_idx(MO_BEQ, mem_idx); + + o1 =3D helper_be_ldq_mmu(env, addr + 0, oi0, ra); + o0 =3D helper_be_ldq_mmu(env, addr + 8, oi1, ra); + oldv =3D int128_make128(o0, o1); + + success =3D int128_eq(oldv, cmpv); + if (success) { + helper_be_stq_mmu(env, addr + 0, int128_gethi(newv), oi1, ra); + helper_be_stq_mmu(env, addr + 8, int128_getlo(newv), oi1, ra); + } +#endif + + return !success; } =20 uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t a= ddr, - uint64_t new_lo, uint64_t new_hi) + uint64_t new_lo, uint64_t ne= w_hi) { - return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true, GETPC()= ); + Int128 oldv, cmpv, newv; + uintptr_t ra =3D GETPC(); + bool success; + int mem_idx; + TCGMemOpIdx oi; + + if (!HAVE_CMPXCHG128) { + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + } + + mem_idx =3D cpu_mmu_index(env, false); + oi =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); + + /* + * High and low need to be switched here because this is not actually a + * 128bit store but two doublewords stored consecutively + */ + cmpv =3D int128_make128(env->exclusive_high, env->exclusive_val); + newv =3D int128_make128(new_hi, new_lo); + oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); + + success =3D int128_eq(oldv, cmpv); + return !success; } =20 /* Writes back the old data into Rs. */ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, uint64_t new_lo, uint64_t new_hi) { - uintptr_t ra =3D GETPC(); -#ifndef CONFIG_ATOMIC128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else Int128 oldv, cmpv, newv; + uintptr_t ra =3D GETPC(); + int mem_idx; + TCGMemOpIdx oi; + + if (!HAVE_CMPXCHG128) { + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + } + + mem_idx =3D cpu_mmu_index(env, false); + oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); =20 cmpv =3D int128_make128(env->xregs[rs], env->xregs[rs + 1]); newv =3D int128_make128(new_lo, new_hi); - - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); oldv =3D helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra); =20 env->xregs[rs] =3D int128_getlo(oldv); env->xregs[rs + 1] =3D int128_gethi(oldv); -#endif } =20 void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, uint64_t new_hi, uint64_t new_lo) { - uintptr_t ra =3D GETPC(); -#ifndef CONFIG_ATOMIC128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else Int128 oldv, cmpv, newv; + uintptr_t ra =3D GETPC(); + int mem_idx; + TCGMemOpIdx oi; + + if (!HAVE_CMPXCHG128) { + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + } + + mem_idx =3D cpu_mmu_index(env, false); + oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); =20 cmpv =3D int128_make128(env->xregs[rs + 1], env->xregs[rs]); newv =3D int128_make128(new_lo, new_hi); - - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); =20 env->xregs[rs + 1] =3D int128_getlo(oldv); env->xregs[rs] =3D int128_gethi(oldv); -#endif } =20 /* --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539714873537847.7558138663411; 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[174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zVQf3itjUOUB22zOcMjuOXnhRpsEU/kH0zSYaIqDkiI=; b=ishDYMSXQq/dO608xbkqhC7bI6QqyEkCadBty/7+Fgnkp8fMs/FlE7iM2JVEWvKS/W a412x/VCpNaV5sD6PQ/5OfWHpo3quFKdkniezpE/JJNiBOU81yRpDNvVg55VNi94wqJo bt4T2CBuL95QRtObTtTBoF+dThO5beYWqeHyw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zVQf3itjUOUB22zOcMjuOXnhRpsEU/kH0zSYaIqDkiI=; b=m42/nxOkhFfOtRlbgXDJCSscQfGLdH7SAtxgKycIDxxnmJOjCfmWhwxhe2KCoOqKu2 u0kG2issTK9/xMH9IWdCLzLMn2ukUhr3DBc3DxG4x1kgKDgnTQZxISsp0AJroUcnA+ii ZISecOlIxyV9N/E6nOrs7d28+5jI9fhKyuBDZ0yUUSSAOc3I+n/QzqTaCReYsQSdxOUA ycDLjyEdnVY2Wa/PtUt5Qhjqc230tklMpjshK6idvWQgWRy9MWL1XoT6RSAlBa2qRKC9 7ZYFHkMLY611Ig9L4ZCQzbKt1qqU50KH62E/OsT/x0P+K+iXFl6H5i4HltvLwhIN4HdX 3bOQ== X-Gm-Message-State: ABuFfoie0hM1SmtnUn8wWNRwrnfbFtH6Or3c6KtGjd4lSLsjb548axr0 Fu3cbT3kjzLBp9lFomMt2zXeRJZ1xiI= X-Google-Smtp-Source: ACcGV60TO8I1+jaDgfT1IC20ixyp31HUa9ViDO0KGEUZ9iygzdN9ztI5JwoY1PdaPEa7H5Sn05/q5Q== X-Received: by 2002:a17:902:5a89:: with SMTP id r9-v6mr22123619pli.95.1539712176682; Tue, 16 Oct 2018 10:49:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:49:05 -0700 Message-Id: <20181016174911.9052-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::635 Subject: [Qemu-devel] [PULL 15/21] target/arm: Check HAVE_CMPXCHG128 at translate time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Reviewed-by: Emilio G. Cota Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 16 ++++------------ target/arm/translate-a64.c | 38 ++++++++++++++++++++++---------------- 2 files changed, 26 insertions(+), 28 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 6e4e1b8a19..61799d20e1 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -563,9 +563,7 @@ uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMSta= te *env, uint64_t addr, int mem_idx; TCGMemOpIdx oi; =20 - if (!HAVE_CMPXCHG128) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } + assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); @@ -635,9 +633,7 @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMSta= te *env, uint64_t addr, int mem_idx; TCGMemOpIdx oi; =20 - if (!HAVE_CMPXCHG128) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } + assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); oi =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); @@ -663,9 +659,7 @@ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_= t rs, uint64_t addr, int mem_idx; TCGMemOpIdx oi; =20 - if (!HAVE_CMPXCHG128) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } + assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); @@ -686,9 +680,7 @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_= t rs, uint64_t addr, int mem_idx; TCGMemOpIdx oi; =20 - if (!HAVE_CMPXCHG128) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } + assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8a24278d79..bb9c4d8ac7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -37,6 +37,7 @@ =20 #include "trace-tcg.h" #include "translate-a64.h" +#include "qemu/atomic128.h" =20 static TCGv_i64 cpu_X[32]; static TCGv_i64 cpu_pc; @@ -2086,26 +2087,27 @@ static void gen_store_exclusive(DisasContext *s, in= t rd, int rt, int rt2, get_mem_index(s), MO_64 | MO_ALIGN | s->be_data); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); - } else if (s->be_data =3D=3D MO_LE) { - if (tb_cflags(s->base.tb) & CF_PARALLEL) { + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { + if (!HAVE_CMPXCHG128) { + gen_helper_exit_atomic(cpu_env); + s->base.is_jmp =3D DISAS_NORETURN; + } else if (s->be_data =3D=3D MO_LE) { gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env, cpu_exclusive_addr, cpu_reg(s, rt), cpu_reg(s, rt2)); } else { - gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive= _addr, - cpu_reg(s, rt), cpu_reg(s, = rt2)); - } - } else { - if (tb_cflags(s->base.tb) & CF_PARALLEL) { gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env, cpu_exclusive_addr, cpu_reg(s, rt), cpu_reg(s, rt2)); - } else { - gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive= _addr, - cpu_reg(s, rt), cpu_reg(s, = rt2)); } + } else if (s->be_data =3D=3D MO_LE) { + gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_add= r, + cpu_reg(s, rt), cpu_reg(s, rt2)= ); + } else { + gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_add= r, + cpu_reg(s, rt), cpu_reg(s, rt2)= ); } } else { tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_= val, @@ -2175,14 +2177,18 @@ static void gen_compare_and_swap_pair(DisasContext = *s, int rs, int rt, } tcg_temp_free_i64(cmp); } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { - TCGv_i32 tcg_rs =3D tcg_const_i32(rs); - - if (s->be_data =3D=3D MO_LE) { - gen_helper_casp_le_parallel(cpu_env, tcg_rs, addr, t1, t2); + if (HAVE_CMPXCHG128) { + TCGv_i32 tcg_rs =3D tcg_const_i32(rs); + if (s->be_data =3D=3D MO_LE) { + gen_helper_casp_le_parallel(cpu_env, tcg_rs, addr, t1, t2); + } else { + gen_helper_casp_be_parallel(cpu_env, tcg_rs, addr, t1, t2); + } + tcg_temp_free_i32(tcg_rs); } else { - gen_helper_casp_be_parallel(cpu_env, tcg_rs, addr, t1, t2); + gen_helper_exit_atomic(cpu_env); + s->base.is_jmp =3D DISAS_NORETURN; } - tcg_temp_free_i32(tcg_rs); } else { TCGv_i64 d1 =3D tcg_temp_new_i64(); TCGv_i64 d2 =3D tcg_temp_new_i64(); --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539714235643949.1776605235917; Tue, 16 Oct 2018 11:23:55 -0700 (PDT) Received: from localhost ([::1]:59582 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCU0K-0002Ax-4i for importer@patchew.org; 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[174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tINqnC7t3qpYIlQwdR+JK2i1hWmQ6SSYgNbVSBX0E60=; b=jQDXOa8Fu11CHwRfmU8SjGmIqyWuFJDgHEZzXxXuN1uRcc5uqPXOrjVZDRVbVsEYPp ayGAtgX2FmWvGJrXeJgL5PlUKI610mBt9TMAY+mempn/mtUIk1oFalmMmiSZ2ygs56ZI vgdHSL6zsp8b2a4Fb77ovbDlKfREs0D82qY/A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tINqnC7t3qpYIlQwdR+JK2i1hWmQ6SSYgNbVSBX0E60=; b=hGShJqP7PZ8BdkXGR8a6+tYOGr0zBmamwD1SCsrYXr8+qC2jrol+OjUtG+xAb9IsFl emf7FVvajOYCEhR5L01xgdkwgmC4zwwV2me74rJw2T1zSAHs3OwlYVd7vHj+LqjSUrsv juEJ5J82iKRGKL3TB5EMvp6xOL95tfEP1xNNlCr7gwzac/mZHekcn7ov6RsXDpsXRXUq y4gAsoJEAAI6XCP+Q2NSe3VJPjzBK3VBJFOuKJzkUsok+qU+w4m4DQhpQPGelVWWPZl9 gNzHtTir600LQdgnks5huLB044C7/sDCvL8SfCaUtIu20xR+DCPJeJ0sVRKgSvzfIsAh yRCg== X-Gm-Message-State: ABuFfojkXDcbUvCZQrcduDjoRzqTKM64VWsLRUMOkyiwzC0RWoy4BFPD x2M4QL+zX7Upm/e7JgjzFlQPvDmbesk= X-Google-Smtp-Source: ACcGV63fXwaearMC6qupif8HiywpvBU/9FtTA0k+17ICGHCYdpbt5RbTHVPDvOZpEhf7sghddLoT0w== X-Received: by 2002:a17:902:6a8b:: with SMTP id n11-v6mr21960925plk.16.1539712178073; Tue, 16 Oct 2018 10:49:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:49:06 -0700 Message-Id: <20181016174911.9052-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62c Subject: [Qemu-devel] [PULL 16/21] target/ppc: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/ppc/helper.h | 2 +- target/ppc/mem_helper.c | 33 ++++++++++-- target/ppc/translate.c | 115 +++++++++++++++++++++------------------- 3 files changed, 88 insertions(+), 62 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index ef64248bc4..7a1481fd0b 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -800,7 +800,7 @@ DEF_HELPER_4(dscliq, void, env, fprp, fprp, i32) DEF_HELPER_1(tbegin, void, env) DEF_HELPER_FLAGS_1(fixup_thrm, TCG_CALL_NO_RWG, void, env) =20 -#if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128) +#ifdef TARGET_PPC64 DEF_HELPER_FLAGS_3(lq_le_parallel, TCG_CALL_NO_WG, i64, env, tl, i32) DEF_HELPER_FLAGS_3(lq_be_parallel, TCG_CALL_NO_WG, i64, env, tl, i32) DEF_HELPER_FLAGS_5(stq_le_parallel, TCG_CALL_NO_WG, diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 8f0d86d104..a1485fad9b 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -25,6 +25,7 @@ #include "exec/cpu_ldst.h" #include "tcg.h" #include "internal.h" +#include "qemu/atomic128.h" =20 //#define DEBUG_OP =20 @@ -215,11 +216,15 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ul= ong addr, uint32_t reg, return i; } =20 -#if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128) +#ifdef TARGET_PPC64 uint64_t helper_lq_le_parallel(CPUPPCState *env, target_ulong addr, uint32_t opidx) { - Int128 ret =3D helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC()); + Int128 ret; + + /* We will have raised EXCP_ATOMIC from the translator. */ + assert(HAVE_ATOMIC128); + ret =3D helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC()); env->retxh =3D int128_gethi(ret); return int128_getlo(ret); } @@ -227,7 +232,11 @@ uint64_t helper_lq_le_parallel(CPUPPCState *env, targe= t_ulong addr, uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr, uint32_t opidx) { - Int128 ret =3D helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC()); + Int128 ret; + + /* We will have raised EXCP_ATOMIC from the translator. */ + assert(HAVE_ATOMIC128); + ret =3D helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC()); env->retxh =3D int128_gethi(ret); return int128_getlo(ret); } @@ -235,14 +244,22 @@ uint64_t helper_lq_be_parallel(CPUPPCState *env, targ= et_ulong addr, void helper_stq_le_parallel(CPUPPCState *env, target_ulong addr, uint64_t lo, uint64_t hi, uint32_t opidx) { - Int128 val =3D int128_make128(lo, hi); + Int128 val; + + /* We will have raised EXCP_ATOMIC from the translator. */ + assert(HAVE_ATOMIC128); + val =3D int128_make128(lo, hi); helper_atomic_sto_le_mmu(env, addr, val, opidx, GETPC()); } =20 void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr, uint64_t lo, uint64_t hi, uint32_t opidx) { - Int128 val =3D int128_make128(lo, hi); + Int128 val; + + /* We will have raised EXCP_ATOMIC from the translator. */ + assert(HAVE_ATOMIC128); + val =3D int128_make128(lo, hi); helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC()); } =20 @@ -252,6 +269,9 @@ uint32_t helper_stqcx_le_parallel(CPUPPCState *env, tar= get_ulong addr, { bool success =3D false; =20 + /* We will have raised EXCP_ATOMIC from the translator. */ + assert(HAVE_CMPXCHG128); + if (likely(addr =3D=3D env->reserve_addr)) { Int128 oldv, cmpv, newv; =20 @@ -271,6 +291,9 @@ uint32_t helper_stqcx_be_parallel(CPUPPCState *env, tar= get_ulong addr, { bool success =3D false; =20 + /* We will have raised EXCP_ATOMIC from the translator. */ + assert(HAVE_CMPXCHG128); + if (likely(addr =3D=3D env->reserve_addr)) { Int128 oldv, cmpv, newv; =20 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 881743571b..4e59dd5f42 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -33,6 +33,7 @@ #include "trace-tcg.h" #include "exec/translator.h" #include "exec/log.h" +#include "qemu/atomic128.h" =20 =20 #define CPU_SINGLE_STEP 0x1 @@ -2654,22 +2655,22 @@ static void gen_lq(DisasContext *ctx) hi =3D cpu_gpr[rd]; =20 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { -#ifdef CONFIG_ATOMIC128 - TCGv_i32 oi =3D tcg_temp_new_i32(); - if (ctx->le_mode) { - tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); - gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); + if (HAVE_ATOMIC128) { + TCGv_i32 oi =3D tcg_temp_new_i32(); + if (ctx->le_mode) { + tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); + gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); + } else { + tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); + gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); + } + tcg_temp_free_i32(oi); + tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); } else { - tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); - gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; } - tcg_temp_free_i32(oi); - tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); -#else - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; -#endif } else if (ctx->le_mode) { tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); gen_addr_add(ctx, EA, EA, 8); @@ -2805,21 +2806,21 @@ static void gen_std(DisasContext *ctx) hi =3D cpu_gpr[rs]; =20 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { -#ifdef CONFIG_ATOMIC128 - TCGv_i32 oi =3D tcg_temp_new_i32(); - if (ctx->le_mode) { - tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); - gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); + if (HAVE_ATOMIC128) { + TCGv_i32 oi =3D tcg_temp_new_i32(); + if (ctx->le_mode) { + tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_i= dx)); + gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); + } else { + tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_i= dx)); + gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); + } + tcg_temp_free_i32(oi); } else { - tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); - gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; } - tcg_temp_free_i32(oi); -#else - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; -#endif } else if (ctx->le_mode) { tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); gen_addr_add(ctx, EA, EA, 8); @@ -3404,26 +3405,26 @@ static void gen_lqarx(DisasContext *ctx) hi =3D cpu_gpr[rd]; =20 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { -#ifdef CONFIG_ATOMIC128 - TCGv_i32 oi =3D tcg_temp_new_i32(); - if (ctx->le_mode) { - tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, - ctx->mem_idx)); - gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); + if (HAVE_ATOMIC128) { + TCGv_i32 oi =3D tcg_temp_new_i32(); + if (ctx->le_mode) { + tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, + ctx->mem_idx)); + gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); + } else { + tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, + ctx->mem_idx)); + gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); + } + tcg_temp_free_i32(oi); + tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); } else { - tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, - ctx->mem_idx)); - gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; + tcg_temp_free(EA); + return; } - tcg_temp_free_i32(oi); - tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); -#else - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - tcg_temp_free(EA); - return; -#endif } else if (ctx->le_mode) { tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); tcg_gen_mov_tl(cpu_reserve, EA); @@ -3461,20 +3462,22 @@ static void gen_stqcx_(DisasContext *ctx) hi =3D cpu_gpr[rs]; =20 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - TCGv_i32 oi =3D tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); -#ifdef CONFIG_ATOMIC128 - if (ctx->le_mode) { - gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, = oi); + if (HAVE_CMPXCHG128) { + TCGv_i32 oi =3D tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); + if (ctx->le_mode) { + gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, + EA, lo, hi, oi); + } else { + gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, + EA, lo, hi, oi); + } + tcg_temp_free_i32(oi); } else { - gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, = oi); + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; } -#else - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; -#endif tcg_temp_free(EA); - tcg_temp_free_i32(oi); } else { TCGLabel *lab_fail =3D gen_new_label(); TCGLabel *lab_over =3D gen_new_label(); --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539715166148618.192357800486; Tue, 16 Oct 2018 11:39:26 -0700 (PDT) Received: from localhost ([::1]:59691 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCUFV-0005qT-Q0 for importer@patchew.org; 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[174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=o+dgHPD7vn5MSQoXXXAwqx0gYM5oyfE8kduesNuHmck=; b=BAk+n0bxV7mUWbCWVBDVswWQ7qRgYBiw06rC+bUtN6Cvla62sySozVQbi/nN7kt+50 8Gq6Vaxi/saKuLmwlTMhJw78xbe7Kq+sZmkegWCS1dO98olHBn6+PWnQPmvbG4gAT0Nx 26MnOV4zCH93kZKW2+lroKOpZPMFX8BoWYnSE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=o+dgHPD7vn5MSQoXXXAwqx0gYM5oyfE8kduesNuHmck=; b=AFp8L8AUKiDTchBtIESZdDttX+Cfj5ZVjcdhWvG30J6v49a1rJS0PUSWEf+zQzzTlZ bb9NmGqtMwzKeQV9K1oUSWOAYm4KKvLIxvty93ug5+6UVG3QfDEZYz0o+kV5eqiyTb6f +QBTSQeYCH9Ea13Nj1hCvKkI6q9mzgzZ/qupVysxfL3ShMelaoXJGyurYv8rHFlJPCwn wcVq/sJk1aRDs8PCknU7xLD6N7DnkDhr2huqu4or+pc0RqwIWqkAXDr3jzzrT9TlPi3o fNsITrXpPqkEUj2ftKafdAnTelbFmH/qwMYyGYcWEOmuaDEhFRzvN/a+uLhzGgYHZgbB LbGA== X-Gm-Message-State: ABuFfogEEpVzurJb+0njjGOZ2E43R0BX2n+ijJENEdI4xyXBybMqTj2+ TKEZoFMZhMXyLreIpORH/p8dzYtkY+w= X-Google-Smtp-Source: ACcGV61LmHddLzmsqrGzpQOMS6FkaV9wbZ3c/9kVi79CeY1HtMPR2lhQpqtTN1ko6LlvlwLoD0SuYg== X-Received: by 2002:a17:902:5a45:: with SMTP id f5-v6mr22705982plm.26.1539712179564; Tue, 16 Oct 2018 10:49:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:49:07 -0700 Message-Id: <20181016174911.9052-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::630 Subject: [Qemu-devel] [PULL 17/21] target/s390x: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/mem_helper.c | 92 +++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 51 deletions(-) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index bacae4f503..e106f61b4e 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -25,6 +25,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "qemu/int128.h" +#include "qemu/atomic128.h" =20 #if !defined(CONFIG_USER_ONLY) #include "hw/s390x/storage-keys.h" @@ -1389,7 +1390,7 @@ static void do_cdsg(CPUS390XState *env, uint64_t addr, bool fail; =20 if (parallel) { -#ifndef CONFIG_ATOMIC128 +#if !HAVE_CMPXCHG128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else int mem_idx =3D cpu_mmu_index(env, false); @@ -1435,9 +1436,7 @@ void HELPER(cdsg_parallel)(CPUS390XState *env, uint64= _t addr, static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2, bool parallel) { -#if !defined(CONFIG_USER_ONLY) || defined(CONFIG_ATOMIC128) uint32_t mem_idx =3D cpu_mmu_index(env, false); -#endif uintptr_t ra =3D GETPC(); uint32_t fc =3D extract32(env->regs[0], 0, 8); uint32_t sc =3D extract32(env->regs[0], 8, 8); @@ -1465,18 +1464,20 @@ static uint32_t do_csst(CPUS390XState *env, uint32_= t r3, uint64_t a1, probe_write(env, a2, 0, mem_idx, ra); #endif =20 - /* Note that the compare-and-swap is atomic, and the store is atomic, = but - the complete operation is not. Therefore we do not need to assert = serial - context in order to implement this. That said, restart early if we= can't - support either operation that is supposed to be atomic. */ + /* + * Note that the compare-and-swap is atomic, and the store is atomic, + * but the complete operation is not. Therefore we do not need to + * assert serial context in order to implement this. That said, + * restart early if we can't support either operation that is supposed + * to be atomic. + */ if (parallel) { - int mask =3D 0; -#if !defined(CONFIG_ATOMIC64) - mask =3D -8; -#elif !defined(CONFIG_ATOMIC128) - mask =3D -16; + uint32_t max =3D 2; +#ifdef CONFIG_ATOMIC64 + max =3D 3; #endif - if (((4 << fc) | (1 << sc)) & mask) { + if ((HAVE_CMPXCHG128 ? 0 : fc + 2 > max) || + (HAVE_ATOMIC128 ? 0 : sc > max)) { cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); } } @@ -1546,16 +1547,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t= r3, uint64_t a1, Int128 cv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); Int128 ov; =20 - if (parallel) { -#ifdef CONFIG_ATOMIC128 - TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, me= m_idx); - ov =3D helper_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, = ra); - cc =3D !int128_eq(ov, cv); -#else - /* Note that we asserted !parallel above. */ - g_assert_not_reached(); -#endif - } else { + if (!parallel) { uint64_t oh =3D cpu_ldq_data_ra(env, a1 + 0, ra); uint64_t ol =3D cpu_ldq_data_ra(env, a1 + 8, ra); =20 @@ -1567,6 +1559,13 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t= r3, uint64_t a1, =20 cpu_stq_data_ra(env, a1 + 0, int128_gethi(nv), ra); cpu_stq_data_ra(env, a1 + 8, int128_getlo(nv), ra); + } else if (HAVE_CMPXCHG128) { + TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, me= m_idx); + ov =3D helper_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, = ra); + cc =3D !int128_eq(ov, cv); + } else { + /* Note that we asserted !parallel above. */ + g_assert_not_reached(); } =20 env->regs[r3 + 0] =3D int128_gethi(ov); @@ -1596,18 +1595,16 @@ static uint32_t do_csst(CPUS390XState *env, uint32_= t r3, uint64_t a1, cpu_stq_data_ra(env, a2, svh, ra); break; case 4: - if (parallel) { -#ifdef CONFIG_ATOMIC128 + if (!parallel) { + cpu_stq_data_ra(env, a2 + 0, svh, ra); + cpu_stq_data_ra(env, a2 + 8, svl, ra); + } else if (HAVE_ATOMIC128) { TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, me= m_idx); Int128 sv =3D int128_make128(svl, svh); helper_atomic_sto_be_mmu(env, a2, sv, oi, ra); -#else + } else { /* Note that we asserted !parallel above. */ g_assert_not_reached(); -#endif - } else { - cpu_stq_data_ra(env, a2 + 0, svh, ra); - cpu_stq_data_ra(env, a2 + 8, svl, ra); } break; default: @@ -2105,21 +2102,18 @@ static uint64_t do_lpq(CPUS390XState *env, uint64_t= addr, bool parallel) uintptr_t ra =3D GETPC(); uint64_t hi, lo; =20 - if (parallel) { -#ifndef CONFIG_ATOMIC128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else + if (!parallel) { + check_alignment(env, addr, 16, ra); + hi =3D cpu_ldq_data_ra(env, addr + 0, ra); + lo =3D cpu_ldq_data_ra(env, addr + 8, ra); + } else if (HAVE_ATOMIC128) { int mem_idx =3D cpu_mmu_index(env, false); TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); Int128 v =3D helper_atomic_ldo_be_mmu(env, addr, oi, ra); hi =3D int128_gethi(v); lo =3D int128_getlo(v); -#endif } else { - check_alignment(env, addr, 16, ra); - - hi =3D cpu_ldq_data_ra(env, addr + 0, ra); - lo =3D cpu_ldq_data_ra(env, addr + 8, ra); + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); } =20 env->retxl =3D lo; @@ -2142,21 +2136,17 @@ static void do_stpq(CPUS390XState *env, uint64_t ad= dr, { uintptr_t ra =3D GETPC(); =20 - if (parallel) { -#ifndef CONFIG_ATOMIC128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); - - Int128 v =3D int128_make128(low, high); - helper_atomic_sto_be_mmu(env, addr, v, oi, ra); -#endif - } else { + if (!parallel) { check_alignment(env, addr, 16, ra); - cpu_stq_data_ra(env, addr + 0, high, ra); cpu_stq_data_ra(env, addr + 8, low, ra); + } else if (HAVE_ATOMIC128) { + int mem_idx =3D cpu_mmu_index(env, false); + TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + Int128 v =3D int128_make128(low, high); + helper_atomic_sto_be_mmu(env, addr, v, oi, ra); + } else { + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); } } =20 --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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[174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=co7JbT0NTKhwEIVbXq3uW8PxRjMU/VzANbjq0dvGlrg=; b=bYojRkeB5hPXYmRNZGoaYPvL/25CT6cdfoAIefIoDy0UOzFo/0kCA82/xssUIaZUF3 rT7JJLigJUA0OmonwnbhZUlLlrlgmZ7BrfnkGnAXKA70TfZ3uYBGjgHikXCtRj0JvD7Z gXi/Ln6SJeHphSPYMxkqCAS6YjH8tuSB8Bbbs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=co7JbT0NTKhwEIVbXq3uW8PxRjMU/VzANbjq0dvGlrg=; b=VvNZosTCubdpJXuJ3pQ/lhAW9z3lWl+5cjTABDWr9/9LaVU28TxpyswNvJoRq1ELHo Bd8RSWbIo39hqXvn6GFeTSCN21fM/Z0JEJHx9vb0BMlF1pUzuFiPy/cPahECH9siepdf 3JdifT5Pfzjpa19/cPo+xeb4ccEM38/QXWzDRbOT1ZR6f/tt6sYN8G0LQgEcY2OEgSuz 1/RuyVCV9bORdaZ+qKgM7gKCD5Vbb1Wjylal45l2GiYkCo+ry4nleqAERlgQ0HYz2YLz lnkP0GoDTds/yw2MSavl6iqh4BUf5rpdroty1XrIcFV/BjnpO3xQ8ksRbDqFanqMZgKL kJPA== X-Gm-Message-State: ABuFfoiZseEuHaBSzufrA/GDh3+kJ+hMIMxVs8TQGoeyLuUK1z/XJHEN Cp/lR4mcbr+FMaOdmWXbwR9rMFhgnoo= X-Google-Smtp-Source: ACcGV63F+hH19FRaktntvE36duSZLTN2tN6aDaiNpNwhNuBJ1vQUExPohC5vCuONDmpeYu9t4LboTw== X-Received: by 2002:a62:fd0b:: with SMTP id p11-v6mr22662777pfh.167.1539712180701; Tue, 16 Oct 2018 10:49:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:49:08 -0700 Message-Id: <20181016174911.9052-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42a Subject: [Qemu-devel] [PULL 18/21] target/s390x: Split do_cdsg, do_lpq, do_stpq X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/mem_helper.c | 128 ++++++++++++++++++-------------------- 1 file changed, 61 insertions(+), 67 deletions(-) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index e106f61b4e..b5858d2fa2 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1380,57 +1380,58 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t = r1, uint32_t r2, return cc; } =20 -static void do_cdsg(CPUS390XState *env, uint64_t addr, - uint32_t r1, uint32_t r3, bool parallel) +void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, + uint32_t r1, uint32_t r3) { uintptr_t ra =3D GETPC(); Int128 cmpv =3D int128_make128(env->regs[r1 + 1], env->regs[r1]); Int128 newv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); Int128 oldv; + uint64_t oldh, oldl; bool fail; =20 - if (parallel) { -#if !HAVE_CMPXCHG128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); - oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, = ra); - fail =3D !int128_eq(oldv, cmpv); -#endif - } else { - uint64_t oldh, oldl; + check_alignment(env, addr, 16, ra); =20 - check_alignment(env, addr, 16, ra); + oldh =3D cpu_ldq_data_ra(env, addr + 0, ra); + oldl =3D cpu_ldq_data_ra(env, addr + 8, ra); =20 - oldh =3D cpu_ldq_data_ra(env, addr + 0, ra); - oldl =3D cpu_ldq_data_ra(env, addr + 8, ra); - - oldv =3D int128_make128(oldl, oldh); - fail =3D !int128_eq(oldv, cmpv); - if (fail) { - newv =3D oldv; - } - - cpu_stq_data_ra(env, addr + 0, int128_gethi(newv), ra); - cpu_stq_data_ra(env, addr + 8, int128_getlo(newv), ra); + oldv =3D int128_make128(oldl, oldh); + fail =3D !int128_eq(oldv, cmpv); + if (fail) { + newv =3D oldv; } =20 + cpu_stq_data_ra(env, addr + 0, int128_gethi(newv), ra); + cpu_stq_data_ra(env, addr + 8, int128_getlo(newv), ra); + env->cc_op =3D fail; env->regs[r1] =3D int128_gethi(oldv); env->regs[r1 + 1] =3D int128_getlo(oldv); } =20 -void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, - uint32_t r1, uint32_t r3) -{ - do_cdsg(env, addr, r1, r3, false); -} - void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr, uint32_t r1, uint32_t r3) { - do_cdsg(env, addr, r1, r3, true); + uintptr_t ra =3D GETPC(); + Int128 cmpv =3D int128_make128(env->regs[r1 + 1], env->regs[r1]); + Int128 newv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); + int mem_idx; + TCGMemOpIdx oi; + Int128 oldv; + bool fail; + + if (!HAVE_CMPXCHG128) { + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + } + + mem_idx =3D cpu_mmu_index(env, false); + oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); + fail =3D !int128_eq(oldv, cmpv); + + env->cc_op =3D fail; + env->regs[r1] =3D int128_gethi(oldv); + env->regs[r1 + 1] =3D int128_getlo(oldv); } =20 static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, @@ -2097,16 +2098,25 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t a= ddr) #endif =20 /* load pair from quadword */ -static uint64_t do_lpq(CPUS390XState *env, uint64_t addr, bool parallel) +uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t addr) { uintptr_t ra =3D GETPC(); uint64_t hi, lo; =20 - if (!parallel) { - check_alignment(env, addr, 16, ra); - hi =3D cpu_ldq_data_ra(env, addr + 0, ra); - lo =3D cpu_ldq_data_ra(env, addr + 8, ra); - } else if (HAVE_ATOMIC128) { + check_alignment(env, addr, 16, ra); + hi =3D cpu_ldq_data_ra(env, addr + 0, ra); + lo =3D cpu_ldq_data_ra(env, addr + 8, ra); + + env->retxl =3D lo; + return hi; +} + +uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uint64_t addr) +{ + uintptr_t ra =3D GETPC(); + uint64_t hi, lo; + + if (HAVE_ATOMIC128) { int mem_idx =3D cpu_mmu_index(env, false); TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); Int128 v =3D helper_atomic_ldo_be_mmu(env, addr, oi, ra); @@ -2120,27 +2130,23 @@ static uint64_t do_lpq(CPUS390XState *env, uint64_t= addr, bool parallel) return hi; } =20 -uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t addr) -{ - return do_lpq(env, addr, false); -} - -uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uint64_t addr) -{ - return do_lpq(env, addr, true); -} - /* store pair to quadword */ -static void do_stpq(CPUS390XState *env, uint64_t addr, - uint64_t low, uint64_t high, bool parallel) +void HELPER(stpq)(CPUS390XState *env, uint64_t addr, + uint64_t low, uint64_t high) { uintptr_t ra =3D GETPC(); =20 - if (!parallel) { - check_alignment(env, addr, 16, ra); - cpu_stq_data_ra(env, addr + 0, high, ra); - cpu_stq_data_ra(env, addr + 8, low, ra); - } else if (HAVE_ATOMIC128) { + check_alignment(env, addr, 16, ra); + cpu_stq_data_ra(env, addr + 0, high, ra); + cpu_stq_data_ra(env, addr + 8, low, ra); +} + +void HELPER(stpq_parallel)(CPUS390XState *env, uint64_t addr, + uint64_t low, uint64_t high) +{ + uintptr_t ra =3D GETPC(); + + if (HAVE_ATOMIC128) { int mem_idx =3D cpu_mmu_index(env, false); TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); Int128 v =3D int128_make128(low, high); @@ -2150,18 +2156,6 @@ static void do_stpq(CPUS390XState *env, uint64_t add= r, } } =20 -void HELPER(stpq)(CPUS390XState *env, uint64_t addr, - uint64_t low, uint64_t high) -{ - do_stpq(env, addr, low, high, false); -} - -void HELPER(stpq_parallel)(CPUS390XState *env, uint64_t addr, - uint64_t low, uint64_t high) -{ - do_stpq(env, addr, low, high, true); -} - /* Execute instruction. This instruction executes an insn modified with the contents of r1. It does not change the executed instruction in mem= ory; it does not change the program counter. --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539715290077636.6724758623652; Tue, 16 Oct 2018 11:41:30 -0700 (PDT) Received: from localhost ([::1]:59712 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCUHY-0007jU-NZ for importer@patchew.org; Tue, 16 Oct 2018 14:41:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59956) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTTZ-0004EU-3d for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCTTT-0001EW-W8 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:48 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:41141) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gCTTT-0001Ds-OS for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:43 -0400 Received: by mail-pf1-x42d.google.com with SMTP id m77-v6so11819454pfi.8 for ; Tue, 16 Oct 2018 10:49:43 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=d0dyaKvSPopezwzsfmkll4fXI/kC81rwwkatVdVGoD8=; b=Cpo7JPOZd6YsZHXlS3c0n2gDspD0BliR55ClOs5tw87xOKcbWIuyLbfhQgmheKakcZ n8yeoCCtwc9v1Jz5AggPwR0DuEQQw3WosrbchcKIdWndr1PI3guDTvLNALD63be14+V6 Dt4ytOD3ZtkRcDbKj8TzMPh39KvK5R0nrHV50= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=d0dyaKvSPopezwzsfmkll4fXI/kC81rwwkatVdVGoD8=; b=HrgwnXyiHDuQCLpYat16i13xrWeBAyUC6NLjwRi89FdcAqSJ33X18WFg7xNlYDKMXP rsonmryYvykrwRP0/SLctpYRzj6m6OnPdgJ5EY38cHyfXgfYvUdyaMC1ngXWD2SqJLIS d08PnG3w887xzpQDGZ6EqEk/OJij64IIxg/ukSQigKzTlPTGZxbVsdw1RVO+SMYVGbSq ybg4QO+7hW8j6oDf6OFtxEJrhN/D+AK0IDniSE7jVdZRcEOS6z65zmE8IEH3OjDl6T0e vDHN2AxD7Fc98dNf/NyPYZOxlHLqDtd1Hslb8xbcO+q68p1Na3EGqQtwwAhRlBhtRN0n 7eAQ== X-Gm-Message-State: ABuFfog2n/6rSjvL0P3GQMSHjGnaEsE4toELEaEdpYryAH00DU1CCRTi aJSJBHdvm2pmcjfZxVsj0cVg1OCOzas= X-Google-Smtp-Source: ACcGV632nqno+hl1mWHqOc3wsTlZjjYfoCbiChFmbWv7kEg4TKy56lr7pWG5f1LoygK/PXF7OtUJsw== X-Received: by 2002:a63:fd58:: with SMTP id m24-v6mr21494300pgj.132.1539712182372; Tue, 16 Oct 2018 10:49:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:49:09 -0700 Message-Id: <20181016174911.9052-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42d Subject: [Qemu-devel] [PULL 19/21] target/s390x: Skip wout, cout helpers if op helper does not return X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When op raises an exception, it may not have initialized the output temps that would be written back by wout or cout. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/translate.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 18861cd186..a7bd689337 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -1128,11 +1128,19 @@ struct DisasInsn { =20 const char *name; =20 + /* Pre-process arguments before HELP_OP. */ void (*help_in1)(DisasContext *, DisasFields *, DisasOps *); void (*help_in2)(DisasContext *, DisasFields *, DisasOps *); void (*help_prep)(DisasContext *, DisasFields *, DisasOps *); + + /* + * Post-process output after HELP_OP. + * Note that these are not called if HELP_OP returns DISAS_NORETURN. + */ void (*help_wout)(DisasContext *, DisasFields *, DisasOps *); void (*help_cout)(DisasContext *, DisasOps *); + + /* Implement the operation itself. */ DisasJumpType (*help_op)(DisasContext *, DisasOps *); =20 uint64_t data; @@ -6125,11 +6133,13 @@ static DisasJumpType translate_one(CPUS390XState *e= nv, DisasContext *s) if (insn->help_op) { ret =3D insn->help_op(s, &o); } - if (insn->help_wout) { - insn->help_wout(s, &f, &o); - } - if (insn->help_cout) { - insn->help_cout(s, &o); + if (ret !=3D DISAS_NORETURN) { + if (insn->help_wout) { + insn->help_wout(s, &f, &o); + } + if (insn->help_cout) { + insn->help_cout(s, &o); + } } =20 /* Free any temporaries created by the helpers. */ --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539713459540709.7148369083013; Tue, 16 Oct 2018 11:10:59 -0700 (PDT) Received: from localhost ([::1]:59501 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTnn-0005hd-5C for importer@patchew.org; Tue, 16 Oct 2018 14:10:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59959) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTTZ-0004EW-4X for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCTTV-0001Gt-T8 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:49 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:38879) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gCTTV-0001FR-Ho for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:45 -0400 Received: by mail-pf1-x431.google.com with SMTP id f29-v6so11828620pff.5 for ; Tue, 16 Oct 2018 10:49:45 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xbiOv5TcJ4wgSOcnZ3lHtDhz8sB5I99xM4Z83wc2zVg=; b=aSUO7UXGl5URVC7X2cqIEVrrrzLFHp38bU1S4TqWXMtSo43mXt0pzrtId5v1KIbqXg FQ0BjBIDKRt4Be1kkcgrt3TFAmByr903d4PLnw/kZOGDuG+LEFsEGCupfob1+for+eqx V9DC2Kh6gcF6somsa3+oeKKwDj3s9K4TxCH4I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xbiOv5TcJ4wgSOcnZ3lHtDhz8sB5I99xM4Z83wc2zVg=; b=ixwizc1d5FmuCv4mlbwtBH2JZKIp2LX/l9JD7tZzJPk+Z0toZeRy/OxtPEtIS7h0Ut Fj44SCZdNnkECUaGB0jhWUwQrbQMcToZ7KKCn4FxEwtJfudedC5Pa3zC2s64szu1mQOE 7mJn0yOqkVHwzKsHdoP50KFLngXx8QU+/qD+K28xaB2BQ2p4dMSF7xGrqnBrmgvgD7lT jrTLohRHO32Kv0P+n068bQpDWIoxPozStFPicRjgjqjPThsonJG3XMMzlYNs+YoUk6ka frp4xIeMiyrjqvWSWgmdgjY9+oBaxi3tT3GRiNrxFtvUzXmv86qE+4t3N2FJZYudD4XM NMKw== X-Gm-Message-State: ABuFfoi5T0FAbwzFhaGHNhRNO3lxn1bP8jCuHyOa+oKXOtZcxOKIQBce j55KgUIxl1JFPvCdVjBjBG0rPUqGaeY= X-Google-Smtp-Source: ACcGV62Uf9NpqBcnhtw+t0gFe7R+MWKLyEbrEpDocdwoFyCURz5YIgfKwNFzdwfy3og3ifis+3YU/Q== X-Received: by 2002:a63:4f4f:: with SMTP id p15-v6mr20943185pgl.71.1539712184101; Tue, 16 Oct 2018 10:49:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:49:10 -0700 Message-Id: <20181016174911.9052-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::431 Subject: [Qemu-devel] [PULL 20/21] target/s390x: Check HAVE_ATOMIC128 and HAVE_CMPXCHG128 at translate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/mem_helper.c | 40 +++++++++++++++++++-------------------- target/s390x/translate.c | 25 +++++++++++++++++------- 2 files changed, 38 insertions(+), 27 deletions(-) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index b5858d2fa2..490c43e6e6 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1420,9 +1420,7 @@ void HELPER(cdsg_parallel)(CPUS390XState *env, uint64= _t addr, Int128 oldv; bool fail; =20 - if (!HAVE_CMPXCHG128) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } + assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); @@ -2115,16 +2113,17 @@ uint64_t HELPER(lpq_parallel)(CPUS390XState *env, u= int64_t addr) { uintptr_t ra =3D GETPC(); uint64_t hi, lo; + int mem_idx; + TCGMemOpIdx oi; + Int128 v; =20 - if (HAVE_ATOMIC128) { - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); - Int128 v =3D helper_atomic_ldo_be_mmu(env, addr, oi, ra); - hi =3D int128_gethi(v); - lo =3D int128_getlo(v); - } else { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } + assert(HAVE_ATOMIC128); + + mem_idx =3D cpu_mmu_index(env, false); + oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + v =3D helper_atomic_ldo_be_mmu(env, addr, oi, ra); + hi =3D int128_gethi(v); + lo =3D int128_getlo(v); =20 env->retxl =3D lo; return hi; @@ -2145,15 +2144,16 @@ void HELPER(stpq_parallel)(CPUS390XState *env, uint= 64_t addr, uint64_t low, uint64_t high) { uintptr_t ra =3D GETPC(); + int mem_idx; + TCGMemOpIdx oi; + Int128 v; =20 - if (HAVE_ATOMIC128) { - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); - Int128 v =3D int128_make128(low, high); - helper_atomic_sto_be_mmu(env, addr, v, oi, ra); - } else { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } + assert(HAVE_ATOMIC128); + + mem_idx =3D cpu_mmu_index(env, false); + oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + v =3D int128_make128(low, high); + helper_atomic_sto_be_mmu(env, addr, v, oi, ra); } =20 /* Execute instruction. This instruction executes an insn modified with diff --git a/target/s390x/translate.c b/target/s390x/translate.c index a7bd689337..b5bd56b7ee 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -44,6 +44,7 @@ #include "trace-tcg.h" #include "exec/translator.h" #include "exec/log.h" +#include "qemu/atomic128.h" =20 =20 /* Information that (most) every instruction needs to manipulate. */ @@ -2040,6 +2041,7 @@ static DisasJumpType op_cdsg(DisasContext *s, DisasOp= s *o) int r3 =3D get_field(s->fields, r3); int d2 =3D get_field(s->fields, d2); int b2 =3D get_field(s->fields, b2); + DisasJumpType ret =3D DISAS_NEXT; TCGv_i64 addr; TCGv_i32 t_r1, t_r3; =20 @@ -2047,17 +2049,20 @@ static DisasJumpType op_cdsg(DisasContext *s, Disas= Ops *o) addr =3D get_address(s, 0, b2, d2); t_r1 =3D tcg_const_i32(r1); t_r3 =3D tcg_const_i32(r3); - if (tb_cflags(s->base.tb) & CF_PARALLEL) { + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_helper_cdsg(cpu_env, addr, t_r1, t_r3); + } else if (HAVE_CMPXCHG128) { gen_helper_cdsg_parallel(cpu_env, addr, t_r1, t_r3); } else { - gen_helper_cdsg(cpu_env, addr, t_r1, t_r3); + gen_helper_exit_atomic(cpu_env); + ret =3D DISAS_NORETURN; } tcg_temp_free_i64(addr); tcg_temp_free_i32(t_r1); tcg_temp_free_i32(t_r3); =20 set_cc_static(s); - return DISAS_NEXT; + return ret; } =20 static DisasJumpType op_csst(DisasContext *s, DisasOps *o) @@ -3034,10 +3039,13 @@ static DisasJumpType op_lpd(DisasContext *s, DisasO= ps *o) =20 static DisasJumpType op_lpq(DisasContext *s, DisasOps *o) { - if (tb_cflags(s->base.tb) & CF_PARALLEL) { + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_helper_lpq(o->out, cpu_env, o->in2); + } else if (HAVE_ATOMIC128) { gen_helper_lpq_parallel(o->out, cpu_env, o->in2); } else { - gen_helper_lpq(o->out, cpu_env, o->in2); + gen_helper_exit_atomic(cpu_env); + return DISAS_NORETURN; } return_low128(o->out2); return DISAS_NEXT; @@ -4414,10 +4422,13 @@ static DisasJumpType op_stmh(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_stpq(DisasContext *s, DisasOps *o) { - if (tb_cflags(s->base.tb) & CF_PARALLEL) { + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_helper_stpq(cpu_env, o->in2, o->out2, o->out); + } else if (HAVE_ATOMIC128) { gen_helper_stpq_parallel(cpu_env, o->in2, o->out2, o->out); } else { - gen_helper_stpq(cpu_env, o->in2, o->out2, o->out); + gen_helper_exit_atomic(cpu_env); + return DISAS_NORETURN; } return DISAS_NEXT; } --=20 2.17.2 From nobody Tue Apr 8 22:25:09 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539714380834299.14016381558315; Tue, 16 Oct 2018 11:26:20 -0700 (PDT) Received: from localhost ([::1]:59600 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCU2t-0004Yi-AT for importer@patchew.org; Tue, 16 Oct 2018 14:26:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59958) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCTTZ-0004EV-4T for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCTTX-0001Ip-Ak for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:49 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:39644) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gCTTW-0001Hf-Vg for qemu-devel@nongnu.org; Tue, 16 Oct 2018 13:49:47 -0400 Received: by mail-pl1-x631.google.com with SMTP id e67-v6so2385881plb.6 for ; Tue, 16 Oct 2018 10:49:46 -0700 (PDT) Received: from cloudburst.twiddle.net (174-21-9-133.tukw.qwest.net. [174.21.9.133]) by smtp.gmail.com with ESMTPSA id 6-v6sm17441210pgl.6.2018.10.16.10.49.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Oct 2018 10:49:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UaQoW0X3h57lcIqJE5IM63G9fD5eqtJkNjrcpKzJ3Eo=; b=da6er6zZUBzMXAJjJ6VlSmoCVZvsF6Jf7fu3/bnMHc8oQGwOCmlYoHk6CuAgFdRagd 2i39PGiCC/LKPKha/OupH42MKBg2i8N+G8JaRBuRt8aF2tgcoOEkmVzR3zNNya/jWHab d/uBpZvfDBf0RWJXtoQlMjetljym+j3reTGNE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UaQoW0X3h57lcIqJE5IM63G9fD5eqtJkNjrcpKzJ3Eo=; b=j999uTVeZEVlkmHbPzoO0oYKcEFPZYcCZO1QH7MCyzt3KnPtUdbskNZ1BntA5DksZY u75U7ZzB+5p4yeY6W7OLw8XVBFHTAcywHJTN02bn0NpNawL080OO/qbNcSx+Qb9b4sEE NPscAnQrF3J7SP87owuYJ3zoXqUYXmAE5BfuKtLj+kd7MIc0B2bhw8QAwhhcDuPHFUje ErBzi/xREw/GC0p4eGhih6OPUX+ynvxAJvvceADjGKaclIEGDmypploUTCuuQaktLQ3W +Gtz5HL4YNgjrFPZ9ckD/pkRSwy0PlwZSUBAYB3Nvl/aUGT5TbdadtYlNsPhXnFzJuAJ tNmA== X-Gm-Message-State: ABuFfoiPnW7ZdbCOXfTHIdipSbKcwL/QgxRKaYikczKOylnL+FW+D07g vq9Ko2yPg3UGtSQzIog/SxzslUmYlGE= X-Google-Smtp-Source: ACcGV62fh2db1v0bOIRat/mvHr4zP3nD8kMXFks/4O8GiPCObQg0/9FUJCfslsRJSPxvJ92Lwno1yg== X-Received: by 2002:a17:902:b104:: with SMTP id q4-v6mr22440679plr.238.1539712185513; Tue, 16 Oct 2018 10:49:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 10:49:11 -0700 Message-Id: <20181016174911.9052-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181016174911.9052-1-richard.henderson@linaro.org> References: <20181016174911.9052-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::631 Subject: [Qemu-devel] [PULL 21/21] cputlb: read CPUTLBEntry.addr_write atomically X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "Emilio G. Cota" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Updates can come from other threads, so readers that do not take tlb_lock must use atomic_read to avoid undefined behaviour (UB). This completes the conversion to tlb_lock. This conversion results on average in no performance loss, as the following experiments (run on an Intel i7-6700K CPU @ 4.00GHz) show. 1. aarch64 bootup+shutdown test: - Before: Performance counter stats for 'taskset -c 0 ../img/aarch64/die.sh' (10 run= s): 7487.087786 task-clock (msec) # 0.998 CPUs utilized = ( +- 0.12% ) 31,574,905,303 cycles # 4.217 GHz = ( +- 0.12% ) 57,097,908,812 instructions # 1.81 insns per cycl= e ( +- 0.08% ) 10,255,415,367 branches # 1369.747 M/sec = ( +- 0.08% ) 173,278,962 branch-misses # 1.69% of all branche= s ( +- 0.18% ) 7.504481349 seconds time elapsed = ( +- 0.14% ) - After: Performance counter stats for 'taskset -c 0 ../img/aarch64/die.sh' (10 run= s): 7462.441328 task-clock (msec) # 0.998 CPUs utilized = ( +- 0.07% ) 31,478,476,520 cycles # 4.218 GHz = ( +- 0.07% ) 57,017,330,084 instructions # 1.81 insns per cycl= e ( +- 0.05% ) 10,251,929,667 branches # 1373.804 M/sec = ( +- 0.05% ) 173,023,787 branch-misses # 1.69% of all branche= s ( +- 0.11% ) 7.474970463 seconds time elapsed = ( +- 0.07% ) 2. SPEC06int: SPEC06int (test set) [Y axis: Speedup over master] 1.15 +-+----+------+------+------+------+------+-------+------+------+---= ---+------+------+------+----+-+ | = | 1.1 +-+.................................+++.............................= + tlb-lock-v2 (m+++x) +-+ | +++ | +++ = tlb-lock-v3 (spinl|ck) | | +++ | | +++ +++ | = | | 1.05 +-+....+++...........####.........|####.+++.|......|.....###....+++.= ..........+++....###.........+-+ | ### ++#| # |# |# ***### +++### +++#+# | = +++ | #|# ### | 1 +-+++***+#++++####+++#++#++++++++++#++#+*+*++#++++#+#+****+#++++###+= +++###++++###++++#+#++++#+#+++-+ | *+* # #++# *** # #### *** # * *++# ****+# *| * # ****|# = |# # #|# #+# # # | 0.95 +-+..*.*.#....#..#.*|*..#...#..#.*|*..#.*.*..#.*|.*.#.*++*.#.*++*+#.= ****.#....#+#....#.#..++#.#..+-+ | * * # # # *|* # # # *|* # * * # *++* # * * # * * # = * |* # ++# # # # *** # | | * * # ++# # *+* # # # *|* # * * # * * # * * # * * # = *++* # **** # ++# # * * # | 0.9 +-+..*.*.#...|#..#.*.*..#.++#..#.*|*..#.*.*..#.*..*.#.*..*.#.*..*.#.= *..*.#.*.|*.#...|#.#..*.*.#..+-+ | * * # *** # * * # |# # *+* # * * # * * # * * # * * # = * * # *++* # |# # * * # | 0.85 +-+..*.*.#..*|*..#.*.*..#.***..#.*.*..#.*.*..#.*..*.#.*..*.#.*..*.#.= *..*.#.*..*.#.****.#..*.*.#..+-+ | * * # *+* # * * # *|* # * * # * * # * * # * * # * * # = * * # * * # * |* # * * # | | * * # * * # * * # *+* # * * # * * # * * # * * # * * # = * * # * * # * |* # * * # | 0.8 +-+..*.*.#..*.*..#.*.*..#.*.*..#.*.*..#.*.*..#.*..*.#.*..*.#.*..*.#.= *..*.#.*..*.#.*++*.#..*.*.#..+-+ | * * # * * # * * # * * # * * # * * # * * # * * # * * # = * * # * * # * * # * * # | 0.75 +-+--***##--***###-***###-***###-***###-***###-****##-****##-****##-= ****##-****##-****##--***##--+-+ 400.perlben401.bzip2403.gcc429.m445.gob456.hmme45462.libqua464.h26471.omne= t473483.xalancbmkgeomean png: https://imgur.com/a/BHzpPTW Notes: - tlb-lock-v2 corresponds to an implementation with a mutex. - tlb-lock-v3 corresponds to the current implementation, i.e. a spinlock and a single lock acquisition in tlb_set_page_with_attrs. Signed-off-by: Emilio G. Cota Message-Id: <20181016153840.25877-1-cota@braap.org> Signed-off-by: Richard Henderson --- accel/tcg/softmmu_template.h | 12 ++++++------ include/exec/cpu_ldst.h | 11 ++++++++++- include/exec/cpu_ldst_template.h | 2 +- accel/tcg/cputlb.c | 19 +++++++++++++------ 4 files changed, 30 insertions(+), 14 deletions(-) diff --git a/accel/tcg/softmmu_template.h b/accel/tcg/softmmu_template.h index 09538b5349..b0adea045e 100644 --- a/accel/tcg/softmmu_template.h +++ b/accel/tcg/softmmu_template.h @@ -280,7 +280,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, uintptr_t mmu_idx =3D get_mmuidx(oi); uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr =3D entry->addr_write; + target_ulong tlb_addr =3D tlb_addr_write(entry); unsigned a_bits =3D get_alignment_bits(get_memop(oi)); uintptr_t haddr; =20 @@ -295,7 +295,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, mmu_idx, retaddr); } - tlb_addr =3D entry->addr_write & ~TLB_INVALID_MASK; + tlb_addr =3D tlb_addr_write(entry) & ~TLB_INVALID_MASK; } =20 /* Handle an IO access. */ @@ -325,7 +325,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, cannot evict the first. */ page2 =3D (addr + DATA_SIZE) & TARGET_PAGE_MASK; entry2 =3D tlb_entry(env, mmu_idx, page2); - if (!tlb_hit_page(entry2->addr_write, page2) + if (!tlb_hit_page(tlb_addr_write(entry2), page2) && !VICTIM_TLB_HIT(addr_write, page2)) { tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE, mmu_idx, retaddr); @@ -358,7 +358,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, uintptr_t mmu_idx =3D get_mmuidx(oi); uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr =3D entry->addr_write; + target_ulong tlb_addr =3D tlb_addr_write(entry); unsigned a_bits =3D get_alignment_bits(get_memop(oi)); uintptr_t haddr; =20 @@ -373,7 +373,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, mmu_idx, retaddr); } - tlb_addr =3D entry->addr_write & ~TLB_INVALID_MASK; + tlb_addr =3D tlb_addr_write(entry) & ~TLB_INVALID_MASK; } =20 /* Handle an IO access. */ @@ -403,7 +403,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, cannot evict the first. */ page2 =3D (addr + DATA_SIZE) & TARGET_PAGE_MASK; entry2 =3D tlb_entry(env, mmu_idx, page2); - if (!tlb_hit_page(entry2->addr_write, page2) + if (!tlb_hit_page(tlb_addr_write(entry2), page2) && !VICTIM_TLB_HIT(addr_write, page2)) { tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE, mmu_idx, retaddr); diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index f54d91ff68..959068495a 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -126,6 +126,15 @@ extern __thread uintptr_t helper_retaddr; /* The memory helpers for tcg-generated code need tcg_target_long etc. */ #include "tcg.h" =20 +static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry) +{ +#if TCG_OVERSIZED_GUEST + return entry->addr_write; +#else + return atomic_read(&entry->addr_write); +#endif +} + /* Find the TLB index corresponding to the mmu_idx + address pair. */ static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx, target_ulong addr) @@ -439,7 +448,7 @@ static inline void *tlb_vaddr_to_host(CPUArchState *env= , abi_ptr addr, tlb_addr =3D tlbentry->addr_read; break; case 1: - tlb_addr =3D tlbentry->addr_write; + tlb_addr =3D tlb_addr_write(tlbentry); break; case 2: tlb_addr =3D tlbentry->addr_code; diff --git a/include/exec/cpu_ldst_template.h b/include/exec/cpu_ldst_templ= ate.h index d21a0b59bf..0f061d47ef 100644 --- a/include/exec/cpu_ldst_template.h +++ b/include/exec/cpu_ldst_template.h @@ -177,7 +177,7 @@ glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArc= hState *env, addr =3D ptr; mmu_idx =3D CPU_MMU_INDEX; entry =3D tlb_entry(env, mmu_idx, addr); - if (unlikely(entry->addr_write !=3D + if (unlikely(tlb_addr_write(entry) !=3D (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) { oi =3D make_memop_idx(SHIFT, mmu_idx); glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(env, addr, v, oi, diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 28b770a404..af57aca5e4 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -258,7 +258,7 @@ static inline bool tlb_hit_page_anyprot(CPUTLBEntry *tl= b_entry, target_ulong page) { return tlb_hit_page(tlb_entry->addr_read, page) || - tlb_hit_page(tlb_entry->addr_write, page) || + tlb_hit_page(tlb_addr_write(tlb_entry), page) || tlb_hit_page(tlb_entry->addr_code, page); } =20 @@ -855,7 +855,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry = *iotlbentry, tlb_fill(cpu, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); =20 entry =3D tlb_entry(env, mmu_idx, addr); - tlb_addr =3D entry->addr_write; + tlb_addr =3D tlb_addr_write(entry); if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) { /* RAM access */ uintptr_t haddr =3D addr + entry->addend; @@ -904,7 +904,14 @@ static bool victim_tlb_hit(CPUArchState *env, size_t m= mu_idx, size_t index, assert_cpu_is_self(ENV_GET_CPU(env)); for (vidx =3D 0; vidx < CPU_VTLB_SIZE; ++vidx) { CPUTLBEntry *vtlb =3D &env->tlb_v_table[mmu_idx][vidx]; - target_ulong cmp =3D *(target_ulong *)((uintptr_t)vtlb + elt_ofs); + target_ulong cmp; + + /* elt_ofs might correspond to .addr_write, so use atomic_read */ +#if TCG_OVERSIZED_GUEST + cmp =3D *(target_ulong *)((uintptr_t)vtlb + elt_ofs); +#else + cmp =3D atomic_read((target_ulong *)((uintptr_t)vtlb + elt_ofs)); +#endif =20 if (cmp =3D=3D page) { /* Found entry in victim tlb, swap tlb and iotlb. */ @@ -977,7 +984,7 @@ void probe_write(CPUArchState *env, target_ulong addr, = int size, int mmu_idx, uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); =20 - if (!tlb_hit(entry->addr_write, addr)) { + if (!tlb_hit(tlb_addr_write(entry), addr)) { /* TLB entry is for a different page */ if (!VICTIM_TLB_HIT(addr_write, addr)) { tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE, @@ -995,7 +1002,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, targ= et_ulong addr, size_t mmu_idx =3D get_mmuidx(oi); uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *tlbe =3D tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr =3D tlbe->addr_write; + target_ulong tlb_addr =3D tlb_addr_write(tlbe); TCGMemOp mop =3D get_memop(oi); int a_bits =3D get_alignment_bits(mop); int s_bits =3D mop & MO_SIZE; @@ -1026,7 +1033,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_STORE, mmu_idx, retaddr); } - tlb_addr =3D tlbe->addr_write & ~TLB_INVALID_MASK; + tlb_addr =3D tlb_addr_write(tlbe) & ~TLB_INVALID_MASK; } =20 /* Notice an IO access or a needs-MMU-lookup access */ --=20 2.17.2