From nobody Wed Apr 16 23:25:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539703712584992.3314351144628; Tue, 16 Oct 2018 08:28:32 -0700 (PDT) Received: from localhost ([::1]:58678 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRGh-0004WX-C5 for importer@patchew.org; Tue, 16 Oct 2018 11:28:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42919) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRC7-0000eI-O3 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRC6-0007so-LK for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:39 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51900) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRC6-0007ll-7F for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:38 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRC5-0003nv-3A for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:37 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:14 +0100 Message-Id: <20181016152325.31367-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 08/19] net: cadence_gem: Use uint32_t for 32bit descriptor words X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 From: "Edgar E. Iglesias" Use uint32_t instead of unsigned to describe 32bit descriptor words. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Edgar E. Iglesias Message-id: 20181011021931.4249-4-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- include/hw/net/cadence_gem.h | 2 +- hw/net/cadence_gem.c | 42 ++++++++++++++++++------------------ 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h index 35de622063e..633d564dc3b 100644 --- a/include/hw/net/cadence_gem.h +++ b/include/hw/net/cadence_gem.h @@ -74,7 +74,7 @@ typedef struct CadenceGEMState { =20 uint8_t can_rx_state; /* Debug only */ =20 - unsigned rx_desc[MAX_PRIORITY_QUEUES][2]; + uint32_t rx_desc[MAX_PRIORITY_QUEUES][2]; =20 bool sar_active[4]; } CadenceGEMState; diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 901c1739709..31f3fe0e816 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -302,42 +302,42 @@ =20 #define GEM_MODID_VALUE 0x00020118 =20 -static inline unsigned tx_desc_get_buffer(unsigned *desc) +static inline unsigned tx_desc_get_buffer(uint32_t *desc) { return desc[0]; } =20 -static inline unsigned tx_desc_get_used(unsigned *desc) +static inline unsigned tx_desc_get_used(uint32_t *desc) { return (desc[1] & DESC_1_USED) ? 1 : 0; } =20 -static inline void tx_desc_set_used(unsigned *desc) +static inline void tx_desc_set_used(uint32_t *desc) { desc[1] |=3D DESC_1_USED; } =20 -static inline unsigned tx_desc_get_wrap(unsigned *desc) +static inline unsigned tx_desc_get_wrap(uint32_t *desc) { return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; } =20 -static inline unsigned tx_desc_get_last(unsigned *desc) +static inline unsigned tx_desc_get_last(uint32_t *desc) { return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; } =20 -static inline void tx_desc_set_last(unsigned *desc) +static inline void tx_desc_set_last(uint32_t *desc) { desc[1] |=3D DESC_1_TX_LAST; } =20 -static inline unsigned tx_desc_get_length(unsigned *desc) +static inline unsigned tx_desc_get_length(uint32_t *desc) { return desc[1] & DESC_1_LENGTH; } =20 -static inline void print_gem_tx_desc(unsigned *desc, uint8_t queue) +static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) { DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); DB_PRINT("bufaddr: 0x%08x\n", *desc); @@ -347,58 +347,58 @@ static inline void print_gem_tx_desc(unsigned *desc, = uint8_t queue) DB_PRINT("length: %d\n", tx_desc_get_length(desc)); } =20 -static inline unsigned rx_desc_get_buffer(unsigned *desc) +static inline unsigned rx_desc_get_buffer(uint32_t *desc) { return desc[0] & ~0x3UL; } =20 -static inline unsigned rx_desc_get_wrap(unsigned *desc) +static inline unsigned rx_desc_get_wrap(uint32_t *desc) { return desc[0] & DESC_0_RX_WRAP ? 1 : 0; } =20 -static inline unsigned rx_desc_get_ownership(unsigned *desc) +static inline unsigned rx_desc_get_ownership(uint32_t *desc) { return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; } =20 -static inline void rx_desc_set_ownership(unsigned *desc) +static inline void rx_desc_set_ownership(uint32_t *desc) { desc[0] |=3D DESC_0_RX_OWNERSHIP; } =20 -static inline void rx_desc_set_sof(unsigned *desc) +static inline void rx_desc_set_sof(uint32_t *desc) { desc[1] |=3D DESC_1_RX_SOF; } =20 -static inline void rx_desc_set_eof(unsigned *desc) +static inline void rx_desc_set_eof(uint32_t *desc) { desc[1] |=3D DESC_1_RX_EOF; } =20 -static inline void rx_desc_set_length(unsigned *desc, unsigned len) +static inline void rx_desc_set_length(uint32_t *desc, unsigned len) { desc[1] &=3D ~DESC_1_LENGTH; desc[1] |=3D len; } =20 -static inline void rx_desc_set_broadcast(unsigned *desc) +static inline void rx_desc_set_broadcast(uint32_t *desc) { desc[1] |=3D R_DESC_1_RX_BROADCAST; } =20 -static inline void rx_desc_set_unicast_hash(unsigned *desc) +static inline void rx_desc_set_unicast_hash(uint32_t *desc) { desc[1] |=3D R_DESC_1_RX_UNICAST_HASH; } =20 -static inline void rx_desc_set_multicast_hash(unsigned *desc) +static inline void rx_desc_set_multicast_hash(uint32_t *desc) { desc[1] |=3D R_DESC_1_RX_MULTICAST_HASH; } =20 -static inline void rx_desc_set_sar(unsigned *desc, int sar_idx) +static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) { desc[1] =3D deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_= LENGTH, sar_idx); @@ -1042,7 +1042,7 @@ static void gem_transmit_updatestats(CadenceGEMState = *s, const uint8_t *packet, */ static void gem_transmit(CadenceGEMState *s) { - unsigned desc[2]; + uint32_t desc[2]; hwaddr packet_desc_addr; uint8_t tx_packet[2048]; uint8_t *p; @@ -1108,7 +1108,7 @@ static void gem_transmit(CadenceGEMState *s) =20 /* Last descriptor for this packet; hand the whole thing off */ if (tx_desc_get_last(desc)) { - unsigned desc_first[2]; + uint32_t desc_first[2]; =20 /* Modify the 1st descriptor of this packet to be owned by * the processor. --=20 2.19.0