From nobody Wed Apr 16 22:41:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539704524386625.8492308546316; Tue, 16 Oct 2018 08:42:04 -0700 (PDT) Received: from localhost ([::1]:58761 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRTq-0008E4-9I for importer@patchew.org; Tue, 16 Oct 2018 11:41:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43306) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRD2-0001T8-KF for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRD1-0000oh-PN for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:36 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51906) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRD1-000803-Du for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:35 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRCC-0003pb-9U for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:44 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:20 +0100 Message-Id: <20181016152325.31367-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 14/19] target-arm: powerctl: Enable HVC when starting CPUs to EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" When QEMU provides the equivalent of the EL3 firmware, we need to enable HVCs in scr_el3 when turning on CPUs that target EL2. Reviewed-by: Peter Maydell Signed-off-by: Edgar E. Iglesias Message-id: 20181011021931.4249-10-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- target/arm/arm-powerctl.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index ce55eeb682b..2b856930fb7 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -103,6 +103,16 @@ static void arm_set_cpu_on_async_work(CPUState *target= _cpu_state, } else { /* Processor is not in secure mode */ target_cpu->env.cp15.scr_el3 |=3D SCR_NS; + + /* + * If QEMU is providing the equivalent of EL3 firmware, then we ne= ed + * to make sure a CPU targeting EL2 comes out of reset with a + * functional HVC insn. + */ + if (arm_feature(&target_cpu->env, ARM_FEATURE_EL3) + && info->target_el =3D=3D 2) { + target_cpu->env.cp15.scr_el3 |=3D SCR_HCE; + } } =20 /* We check if the started CPU is now at the correct level */ --=20 2.19.0