From nobody Wed Apr 16 23:23:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539704077012804.9327597588912; Tue, 16 Oct 2018 08:34:37 -0700 (PDT) Received: from localhost ([::1]:58714 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRMe-0001xf-2d for importer@patchew.org; Tue, 16 Oct 2018 11:34:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43029) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRCE-0000lq-AN for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRC8-0007wS-AM for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:46 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51902) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRC8-0007sS-2f for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:40 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRBy-0003mG-DT for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:30 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:07 +0100 Message-Id: <20181016152325.31367-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 01/19] hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Jerome Forissier Bindings for /secure-chosen and /secure-chosen/stdout-path have been proposed 1.5 years ago [1] and implemented in OP-TEE at the same time [2]. They've now been officially agreed on, so we can implement them in QEMU. This patch creates the property when the machine is secure. [1] https://patchwork.kernel.org/patch/9602401/ [2] https://github.com/OP-TEE/optee_os/commit/4dc31c52544a Signed-off-by: Jerome Forissier Message-id: 20181005080729.6480-1-jerome.forissier@linaro.org Reviewed-by: Peter Maydell [PMM: commit message tweak] Signed-off-by: Peter Maydell --- hw/arm/virt.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 96dd4ef10c5..9f677825f9f 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -712,6 +712,10 @@ static void create_uart(const VirtMachineState *vms, q= emu_irq *pic, int uart, /* Mark as not usable by the normal world */ qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay= "); + + qemu_fdt_add_subnode(vms->fdt, "/secure-chosen"); + qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", + nodename); } =20 g_free(nodename); --=20 2.19.0 From nobody Wed Apr 16 23:23:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539703870013851.748198980899; Tue, 16 Oct 2018 08:31:10 -0700 (PDT) Received: from localhost ([::1]:58700 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRJM-0007Wa-Ph for importer@patchew.org; Tue, 16 Oct 2018 11:31:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42966) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRC9-0000fp-69 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRC8-0007w3-34 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:41 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51898) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRC7-0007PR-OJ for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:39 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRBz-0003mU-Bf for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:31 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:08 +0100 Message-Id: <20181016152325.31367-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 02/19] target/arm: Fix aarch64_sve_change_el wrt EL0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson At present we assert: arm_el_is_aa64: Assertion `el >=3D 1 && el <=3D 3' failed. The comment in arm_el_is_aa64 explains why asking about EL0 without extra information is impossible. Add an extra argument to provide it from the surrounding context. Fixes: 0ab5953b00b3 Signed-off-by: Richard Henderson Message-id: 20181008212205.17752-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 7 +++++-- target/arm/helper.c | 16 ++++++++++++---- target/arm/op_helper.c | 6 +++++- 3 files changed, 22 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3a2aff11928..54362ddce81 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -911,10 +911,13 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f,= CPUState *cs, int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); -void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el); +void aarch64_sve_change_el(CPUARMState *env, int old_el, + int new_el, bool el0_a64); #else static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } -static inline void aarch64_sve_change_el(CPUARMState *env, int o, int n) {= } +static inline void aarch64_sve_change_el(CPUARMState *env, int o, + int n, bool a) +{ } #endif =20 target_ulong do_arm_semihosting(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index c83f7c1109c..0efbb5c76ce 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8374,7 +8374,11 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *c= s) unsigned int new_mode =3D aarch64_pstate_mode(new_el, true); unsigned int cur_el =3D arm_current_el(env); =20 - aarch64_sve_change_el(env, cur_el, new_el); + /* + * Note that new_el can never be 0. If cur_el is 0, then + * el0_a64 is is_a64(), else el0_a64 is ignored. + */ + aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); =20 if (cur_el < new_el) { /* Entry vector offset depends on whether the implemented EL @@ -12791,9 +12795,11 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsig= ned vq) /* * Notice a change in SVE vector size when changing EL. */ -void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el) +void aarch64_sve_change_el(CPUARMState *env, int old_el, + int new_el, bool el0_a64) { int old_len, new_len; + bool old_a64, new_a64; =20 /* Nothing to do if no SVE. */ if (!arm_feature(env, ARM_FEATURE_SVE)) { @@ -12817,9 +12823,11 @@ void aarch64_sve_change_el(CPUARMState *env, int o= ld_el, int new_el) * we already have the correct register contents when encountering the * vq0->vq0 transition between EL0->EL1. */ - old_len =3D (arm_el_is_aa64(env, old_el) && !sve_exception_el(env, old= _el) + old_a64 =3D old_el ? arm_el_is_aa64(env, old_el) : el0_a64; + old_len =3D (old_a64 && !sve_exception_el(env, old_el) ? sve_zcr_len_for_el(env, old_el) : 0); - new_len =3D (arm_el_is_aa64(env, new_el) && !sve_exception_el(env, new= _el) + new_a64 =3D new_el ? arm_el_is_aa64(env, new_el) : el0_a64; + new_len =3D (new_a64 && !sve_exception_el(env, new_el) ? sve_zcr_len_for_el(env, new_el) : 0); =20 /* When changing vector length, clear inaccessible state. */ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index fb15a13e6c9..d9155797126 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -1101,7 +1101,11 @@ void HELPER(exception_return)(CPUARMState *env) "AArch64 EL%d PC 0x%" PRIx64 "\n", cur_el, new_el, env->pc); } - aarch64_sve_change_el(env, cur_el, new_el); + /* + * Note that cur_el can never be 0. If new_el is 0, then + * el0_a64 is return_to_aa64, else el0_a64 is ignored. + */ + aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); =20 qemu_mutex_lock_iothread(); arm_call_el_change_hook(arm_env_get_cpu(env)); --=20 2.19.0 From nobody Wed Apr 16 23:23:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539704063864235.94645174604614; Tue, 16 Oct 2018 08:34:23 -0700 (PDT) Received: from localhost ([::1]:58713 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRMU-0001qf-Gh for importer@patchew.org; Tue, 16 Oct 2018 11:34:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42952) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRC8-0000fK-N3 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRC7-0007un-NF for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:40 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51900) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRC7-0007ll-EH for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:39 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRC0-0003mi-9E for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:32 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:09 +0100 Message-Id: <20181016152325.31367-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 03/19] target/arm: Define fields of ISAR registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 From: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-id: 20181008212205.17752-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 88 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 54362ddce81..f00c0444c48 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1443,6 +1443,94 @@ FIELD(V7M_CSSELR, LEVEL, 1, 3) */ FIELD(V7M_CSSELR, INDEX, 0, 4) =20 +/* + * System register ID fields. + */ +FIELD(ID_ISAR0, SWAP, 0, 4) +FIELD(ID_ISAR0, BITCOUNT, 4, 4) +FIELD(ID_ISAR0, BITFIELD, 8, 4) +FIELD(ID_ISAR0, CMPBRANCH, 12, 4) +FIELD(ID_ISAR0, COPROC, 16, 4) +FIELD(ID_ISAR0, DEBUG, 20, 4) +FIELD(ID_ISAR0, DIVIDE, 24, 4) + +FIELD(ID_ISAR1, ENDIAN, 0, 4) +FIELD(ID_ISAR1, EXCEPT, 4, 4) +FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) +FIELD(ID_ISAR1, EXTEND, 12, 4) +FIELD(ID_ISAR1, IFTHEN, 16, 4) +FIELD(ID_ISAR1, IMMEDIATE, 20, 4) +FIELD(ID_ISAR1, INTERWORK, 24, 4) +FIELD(ID_ISAR1, JAZELLE, 28, 4) + +FIELD(ID_ISAR2, LOADSTORE, 0, 4) +FIELD(ID_ISAR2, MEMHINT, 4, 4) +FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) +FIELD(ID_ISAR2, MULT, 12, 4) +FIELD(ID_ISAR2, MULTS, 16, 4) +FIELD(ID_ISAR2, MULTU, 20, 4) +FIELD(ID_ISAR2, PSR_AR, 24, 4) +FIELD(ID_ISAR2, REVERSAL, 28, 4) + +FIELD(ID_ISAR3, SATURATE, 0, 4) +FIELD(ID_ISAR3, SIMD, 4, 4) +FIELD(ID_ISAR3, SVC, 8, 4) +FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) +FIELD(ID_ISAR3, TABBRANCH, 16, 4) +FIELD(ID_ISAR3, T32COPY, 20, 4) +FIELD(ID_ISAR3, TRUENOP, 24, 4) +FIELD(ID_ISAR3, T32EE, 28, 4) + +FIELD(ID_ISAR4, UNPRIV, 0, 4) +FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) +FIELD(ID_ISAR4, WRITEBACK, 8, 4) +FIELD(ID_ISAR4, SMC, 12, 4) +FIELD(ID_ISAR4, BARRIER, 16, 4) +FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) +FIELD(ID_ISAR4, PSR_M, 24, 4) +FIELD(ID_ISAR4, SWP_FRAC, 28, 4) + +FIELD(ID_ISAR5, SEVL, 0, 4) +FIELD(ID_ISAR5, AES, 4, 4) +FIELD(ID_ISAR5, SHA1, 8, 4) +FIELD(ID_ISAR5, SHA2, 12, 4) +FIELD(ID_ISAR5, CRC32, 16, 4) +FIELD(ID_ISAR5, RDM, 24, 4) +FIELD(ID_ISAR5, VCMA, 28, 4) + +FIELD(ID_ISAR6, JSCVT, 0, 4) +FIELD(ID_ISAR6, DP, 4, 4) +FIELD(ID_ISAR6, FHM, 8, 4) +FIELD(ID_ISAR6, SB, 12, 4) +FIELD(ID_ISAR6, SPECRES, 16, 4) + +FIELD(ID_AA64ISAR0, AES, 4, 4) +FIELD(ID_AA64ISAR0, SHA1, 8, 4) +FIELD(ID_AA64ISAR0, SHA2, 12, 4) +FIELD(ID_AA64ISAR0, CRC32, 16, 4) +FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) +FIELD(ID_AA64ISAR0, RDM, 28, 4) +FIELD(ID_AA64ISAR0, SHA3, 32, 4) +FIELD(ID_AA64ISAR0, SM3, 36, 4) +FIELD(ID_AA64ISAR0, SM4, 40, 4) +FIELD(ID_AA64ISAR0, DP, 44, 4) +FIELD(ID_AA64ISAR0, FHM, 48, 4) +FIELD(ID_AA64ISAR0, TS, 52, 4) +FIELD(ID_AA64ISAR0, TLB, 56, 4) +FIELD(ID_AA64ISAR0, RNDR, 60, 4) + +FIELD(ID_AA64ISAR1, DPB, 0, 4) +FIELD(ID_AA64ISAR1, APA, 4, 4) +FIELD(ID_AA64ISAR1, API, 8, 4) +FIELD(ID_AA64ISAR1, JSCVT, 12, 4) +FIELD(ID_AA64ISAR1, FCMA, 16, 4) +FIELD(ID_AA64ISAR1, LRCPC, 20, 4) +FIELD(ID_AA64ISAR1, GPA, 24, 4) +FIELD(ID_AA64ISAR1, GPI, 28, 4) +FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) +FIELD(ID_AA64ISAR1, SB, 36, 4) +FIELD(ID_AA64ISAR1, SPECRES, 40, 4) + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=3D R_V7M_CSSELR_INDE= X_MASK); =20 /* If adding a feature bit which corresponds to a Linux ELF --=20 2.19.0 From nobody Wed Apr 16 23:23:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539703714005323.7319225754667; Tue, 16 Oct 2018 08:28:34 -0700 (PDT) Received: from localhost ([::1]:58679 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRGl-0004at-MM for importer@patchew.org; Tue, 16 Oct 2018 11:28:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42923) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRC8-0000eU-0K for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRC6-0007tW-W4 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:39 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51898) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRC6-0007PR-MK for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:38 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRC1-0003mw-6v for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:33 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:10 +0100 Message-Id: <20181016152325.31367-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 04/19] target/arm: Align cortex-r5 id_isar0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 From: Richard Henderson The missing nibble made it more difficult to read. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-id: 20181008212205.17752-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b5e61cc1775..7ea7e4c1316 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1397,7 +1397,7 @@ static void cortex_r5_initfn(Object *obj) cpu->id_mmfr1 =3D 0x00000000; cpu->id_mmfr2 =3D 0x01200000; cpu->id_mmfr3 =3D 0x0211; - cpu->id_isar0 =3D 0x2101111; + cpu->id_isar0 =3D 0x02101111; cpu->id_isar1 =3D 0x13112111; cpu->id_isar2 =3D 0x21232141; cpu->id_isar3 =3D 0x01112131; --=20 2.19.0 From nobody Wed Apr 16 23:23:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539703714595815.4804666185437; Tue, 16 Oct 2018 08:28:34 -0700 (PDT) Received: from localhost ([::1]:58677 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRGh-0004VS-0h for importer@patchew.org; Tue, 16 Oct 2018 11:28:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42890) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRC6-0000dj-MC for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRC5-0007qC-Rg for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:38 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51898) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRC5-0007PR-I2 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:37 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRC2-0003nA-9a for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:34 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:11 +0100 Message-Id: <20181016152325.31367-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 05/19] target/arm: Fix cortex-a7 id_isar0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 From: Richard Henderson The incorrect value advertised only thumb2 div without arm div. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-id: 20181008212205.17752-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7ea7e4c1316..cd48ad42d87 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1587,7 +1587,10 @@ static void cortex_a7_initfn(Object *obj) cpu->id_mmfr1 =3D 0x40000000; cpu->id_mmfr2 =3D 0x01240000; cpu->id_mmfr3 =3D 0x02102211; - cpu->id_isar0 =3D 0x01101110; + /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but + * table 4-41 gives 0x02101110, which includes the arm div insns. + */ + cpu->id_isar0 =3D 0x02101110; cpu->id_isar1 =3D 0x13112111; cpu->id_isar2 =3D 0x21232041; cpu->id_isar3 =3D 0x11112131; --=20 2.19.0 From nobody Wed Apr 16 23:23:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539703538295480.14034854550846; Tue, 16 Oct 2018 08:25:38 -0700 (PDT) Received: from localhost ([::1]:58662 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRE1-0001th-1Z for importer@patchew.org; Tue, 16 Oct 2018 11:25:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42851) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRC5-0000dR-M3 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRC4-0007mH-QE for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:37 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51898) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRC4-0007PR-JA for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:36 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRC3-0003nO-87 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:35 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:12 +0100 Message-Id: <20181016152325.31367-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 06/19] net: cadence_gem: Disable TSU feature bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Disable the Timestamping Unit feature bit since QEMU does not yet support it. This allows guest SW to correctly probe for its existance. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias Message-id: 20181011021931.4249-2-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 0fa4b0dc440..e560b7a142e 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1228,7 +1228,7 @@ static void gem_reset(DeviceState *d) s->regs[GEM_MODID] =3D s->revision; s->regs[GEM_DESCONF] =3D 0x02500111; s->regs[GEM_DESCONF2] =3D 0x2ab13fff; - s->regs[GEM_DESCONF5] =3D 0x002f2145; + s->regs[GEM_DESCONF5] =3D 0x002f2045; s->regs[GEM_DESCONF6] =3D 0x00000200; =20 /* Set MAC address */ --=20 2.19.0 From nobody Wed Apr 16 23:23:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539703535421515.4304022026979; Tue, 16 Oct 2018 08:25:35 -0700 (PDT) Received: from localhost ([::1]:58660 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRDx-0001pz-W2 for importer@patchew.org; Tue, 16 Oct 2018 11:25:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42871) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRC6-0000de-72 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRC5-0007nj-C8 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:38 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51900) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRC5-0007ll-3d for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:37 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRC4-0003ne-5P for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:36 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:13 +0100 Message-Id: <20181016152325.31367-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 07/19] net: cadence_gem: Announce availability of priority queues X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Announce the availability of the various priority queues. This fixes an issue where guest kernels would miss to configure secondary queues due to inproper feature bits. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias Message-id: 20181011021931.4249-3-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index e560b7a142e..901c1739709 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1213,6 +1213,7 @@ static void gem_reset(DeviceState *d) int i; CadenceGEMState *s =3D CADENCE_GEM(d); const uint8_t *a; + uint32_t queues_mask; =20 DB_PRINT("\n"); =20 @@ -1229,7 +1230,10 @@ static void gem_reset(DeviceState *d) s->regs[GEM_DESCONF] =3D 0x02500111; s->regs[GEM_DESCONF2] =3D 0x2ab13fff; s->regs[GEM_DESCONF5] =3D 0x002f2045; - s->regs[GEM_DESCONF6] =3D 0x00000200; + s->regs[GEM_DESCONF6] =3D 0x0; + + queues_mask =3D MAKE_64BIT_MASK(1, s->num_priority_queues - 1); + s->regs[GEM_DESCONF6] |=3D queues_mask; =20 /* Set MAC address */ a =3D &s->conf.macaddr.a[0]; --=20 2.19.0 From nobody Wed Apr 16 23:23:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539703712584992.3314351144628; Tue, 16 Oct 2018 08:28:32 -0700 (PDT) Received: from localhost ([::1]:58678 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRGh-0004WX-C5 for importer@patchew.org; Tue, 16 Oct 2018 11:28:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42919) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRC7-0000eI-O3 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRC6-0007so-LK for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:39 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51900) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRC6-0007ll-7F for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:38 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRC5-0003nv-3A for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:37 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:14 +0100 Message-Id: <20181016152325.31367-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 08/19] net: cadence_gem: Use uint32_t for 32bit descriptor words X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 From: "Edgar E. Iglesias" Use uint32_t instead of unsigned to describe 32bit descriptor words. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Edgar E. Iglesias Message-id: 20181011021931.4249-4-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- include/hw/net/cadence_gem.h | 2 +- hw/net/cadence_gem.c | 42 ++++++++++++++++++------------------ 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h index 35de622063e..633d564dc3b 100644 --- a/include/hw/net/cadence_gem.h +++ b/include/hw/net/cadence_gem.h @@ -74,7 +74,7 @@ typedef struct CadenceGEMState { =20 uint8_t can_rx_state; /* Debug only */ =20 - unsigned rx_desc[MAX_PRIORITY_QUEUES][2]; + uint32_t rx_desc[MAX_PRIORITY_QUEUES][2]; =20 bool sar_active[4]; } CadenceGEMState; diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 901c1739709..31f3fe0e816 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -302,42 +302,42 @@ =20 #define GEM_MODID_VALUE 0x00020118 =20 -static inline unsigned tx_desc_get_buffer(unsigned *desc) +static inline unsigned tx_desc_get_buffer(uint32_t *desc) { return desc[0]; } =20 -static inline unsigned tx_desc_get_used(unsigned *desc) +static inline unsigned tx_desc_get_used(uint32_t *desc) { return (desc[1] & DESC_1_USED) ? 1 : 0; } =20 -static inline void tx_desc_set_used(unsigned *desc) +static inline void tx_desc_set_used(uint32_t *desc) { desc[1] |=3D DESC_1_USED; } =20 -static inline unsigned tx_desc_get_wrap(unsigned *desc) +static inline unsigned tx_desc_get_wrap(uint32_t *desc) { return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; } =20 -static inline unsigned tx_desc_get_last(unsigned *desc) +static inline unsigned tx_desc_get_last(uint32_t *desc) { return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; } =20 -static inline void tx_desc_set_last(unsigned *desc) +static inline void tx_desc_set_last(uint32_t *desc) { desc[1] |=3D DESC_1_TX_LAST; } =20 -static inline unsigned tx_desc_get_length(unsigned *desc) +static inline unsigned tx_desc_get_length(uint32_t *desc) { return desc[1] & DESC_1_LENGTH; } =20 -static inline void print_gem_tx_desc(unsigned *desc, uint8_t queue) +static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) { DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); DB_PRINT("bufaddr: 0x%08x\n", *desc); @@ -347,58 +347,58 @@ static inline void print_gem_tx_desc(unsigned *desc, = uint8_t queue) DB_PRINT("length: %d\n", tx_desc_get_length(desc)); } =20 -static inline unsigned rx_desc_get_buffer(unsigned *desc) +static inline unsigned rx_desc_get_buffer(uint32_t *desc) { return desc[0] & ~0x3UL; } =20 -static inline unsigned rx_desc_get_wrap(unsigned *desc) +static inline unsigned rx_desc_get_wrap(uint32_t *desc) { return desc[0] & DESC_0_RX_WRAP ? 1 : 0; } =20 -static inline unsigned rx_desc_get_ownership(unsigned *desc) +static inline unsigned rx_desc_get_ownership(uint32_t *desc) { return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; } =20 -static inline void rx_desc_set_ownership(unsigned *desc) +static inline void rx_desc_set_ownership(uint32_t *desc) { desc[0] |=3D DESC_0_RX_OWNERSHIP; } =20 -static inline void rx_desc_set_sof(unsigned *desc) +static inline void rx_desc_set_sof(uint32_t *desc) { desc[1] |=3D DESC_1_RX_SOF; } =20 -static inline void rx_desc_set_eof(unsigned *desc) +static inline void rx_desc_set_eof(uint32_t *desc) { desc[1] |=3D DESC_1_RX_EOF; } =20 -static inline void rx_desc_set_length(unsigned *desc, unsigned len) +static inline void rx_desc_set_length(uint32_t *desc, unsigned len) { desc[1] &=3D ~DESC_1_LENGTH; desc[1] |=3D len; } =20 -static inline void rx_desc_set_broadcast(unsigned *desc) +static inline void rx_desc_set_broadcast(uint32_t *desc) { desc[1] |=3D R_DESC_1_RX_BROADCAST; } =20 -static inline void rx_desc_set_unicast_hash(unsigned *desc) +static inline void rx_desc_set_unicast_hash(uint32_t *desc) { desc[1] |=3D R_DESC_1_RX_UNICAST_HASH; } =20 -static inline void rx_desc_set_multicast_hash(unsigned *desc) +static inline void rx_desc_set_multicast_hash(uint32_t *desc) { desc[1] |=3D R_DESC_1_RX_MULTICAST_HASH; } =20 -static inline void rx_desc_set_sar(unsigned *desc, int sar_idx) +static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) { desc[1] =3D deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_= LENGTH, sar_idx); @@ -1042,7 +1042,7 @@ static void gem_transmit_updatestats(CadenceGEMState = *s, const uint8_t *packet, */ static void gem_transmit(CadenceGEMState *s) { - unsigned desc[2]; + uint32_t desc[2]; hwaddr packet_desc_addr; uint8_t tx_packet[2048]; uint8_t *p; @@ -1108,7 +1108,7 @@ static void gem_transmit(CadenceGEMState *s) =20 /* Last descriptor for this packet; hand the whole thing off */ if (tx_desc_get_last(desc)) { - unsigned desc_first[2]; + uint32_t desc_first[2]; =20 /* Modify the 1st descriptor of this packet to be owned by * the processor. --=20 2.19.0 From nobody Wed Apr 16 23:23:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539703871095725.9544868151609; Tue, 16 Oct 2018 08:31:11 -0700 (PDT) Received: from localhost ([::1]:58701 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRJO-0007Xl-0I for importer@patchew.org; Tue, 16 Oct 2018 11:31:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42929) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRC8-0000ec-41 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRC7-0007uB-8b for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:40 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51902) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRC7-0007sS-0x for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:39 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRC6-0003oD-2T for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:38 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:15 +0100 Message-Id: <20181016152325.31367-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 09/19] net: cadence_gem: Add macro with max number of descriptor words X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 From: "Edgar E. Iglesias" Add macro with max number of DMA descriptor words. No functional change. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Edgar E. Iglesias Message-id: 20181011021931.4249-5-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- include/hw/net/cadence_gem.h | 5 ++++- hw/net/cadence_gem.c | 4 ++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h index 633d564dc3b..b33ef6513b9 100644 --- a/include/hw/net/cadence_gem.h +++ b/include/hw/net/cadence_gem.h @@ -32,6 +32,9 @@ =20 #define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM addre= ss */ =20 +/* Max number of words in a DMA descriptor. */ +#define DESC_MAX_NUM_WORDS 2 + #define MAX_PRIORITY_QUEUES 8 #define MAX_TYPE1_SCREENERS 16 #define MAX_TYPE2_SCREENERS 16 @@ -74,7 +77,7 @@ typedef struct CadenceGEMState { =20 uint8_t can_rx_state; /* Debug only */ =20 - uint32_t rx_desc[MAX_PRIORITY_QUEUES][2]; + uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS]; =20 bool sar_active[4]; } CadenceGEMState; diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 31f3fe0e816..4d769b02440 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1042,7 +1042,7 @@ static void gem_transmit_updatestats(CadenceGEMState = *s, const uint8_t *packet, */ static void gem_transmit(CadenceGEMState *s) { - uint32_t desc[2]; + uint32_t desc[DESC_MAX_NUM_WORDS]; hwaddr packet_desc_addr; uint8_t tx_packet[2048]; uint8_t *p; @@ -1108,7 +1108,7 @@ static void gem_transmit(CadenceGEMState *s) =20 /* Last descriptor for this packet; hand the whole thing off */ if (tx_desc_get_last(desc)) { - uint32_t desc_first[2]; + uint32_t desc_first[DESC_MAX_NUM_WORDS]; =20 /* Modify the 1st descriptor of this packet to be owned by * the processor. --=20 2.19.0 From nobody Wed Apr 16 23:23:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539703880231979.2186848947905; Tue, 16 Oct 2018 08:31:20 -0700 (PDT) Received: from localhost ([::1]:58702 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRJX-0007gY-0H for importer@patchew.org; Tue, 16 Oct 2018 11:31:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43000) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRCB-0000ht-1I for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRC9-0007yr-Rx for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:42 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51904) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRC9-0007xg-HF for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:41 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRC8-0003od-IH for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:40 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:16 +0100 Message-Id: <20181016152325.31367-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 10/19] net: cadence_gem: Add support for extended descriptors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Add support for extended descriptors with optional 64bit addressing and timestamping. QEMU will not yet provide timestamps (always leaving the valid timestamp bit as zero). Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias Message-id: 20181011021931.4249-6-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- include/hw/net/cadence_gem.h | 2 +- hw/net/cadence_gem.c | 69 ++++++++++++++++++++++++++---------- 2 files changed, 52 insertions(+), 19 deletions(-) diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h index b33ef6513b9..00dbf4f72e3 100644 --- a/include/hw/net/cadence_gem.h +++ b/include/hw/net/cadence_gem.h @@ -33,7 +33,7 @@ #define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM addre= ss */ =20 /* Max number of words in a DMA descriptor. */ -#define DESC_MAX_NUM_WORDS 2 +#define DESC_MAX_NUM_WORDS 6 =20 #define MAX_PRIORITY_QUEUES 8 #define MAX_TYPE1_SCREENERS 16 diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 4d769b02440..759c1d71e02 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -207,6 +207,9 @@ #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ =20 +#define GEM_DMACFG_ADDR_64B (1U << 30) +#define GEM_DMACFG_TX_BD_EXT (1U << 29) +#define GEM_DMACFG_RX_BD_EXT (1U << 28) #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier= */ @@ -302,9 +305,14 @@ =20 #define GEM_MODID_VALUE 0x00020118 =20 -static inline unsigned tx_desc_get_buffer(uint32_t *desc) +static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *de= sc) { - return desc[0]; + uint64_t ret =3D desc[0]; + + if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { + ret |=3D (uint64_t)desc[2] << 32; + } + return ret; } =20 static inline unsigned tx_desc_get_used(uint32_t *desc) @@ -347,9 +355,30 @@ static inline void print_gem_tx_desc(uint32_t *desc, u= int8_t queue) DB_PRINT("length: %d\n", tx_desc_get_length(desc)); } =20 -static inline unsigned rx_desc_get_buffer(uint32_t *desc) +static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *de= sc) { - return desc[0] & ~0x3UL; + uint64_t ret =3D desc[0] & ~0x3UL; + + if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { + ret |=3D (uint64_t)desc[2] << 32; + } + return ret; +} + +static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) +{ + int ret =3D 2; + + if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { + ret +=3D 2; + } + if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT + : GEM_DMACFG_TX_BD_EXT)) { + ret +=3D 2; + } + + assert(ret <=3D DESC_MAX_NUM_WORDS); + return ret; } =20 static inline unsigned rx_desc_get_wrap(uint32_t *desc) @@ -419,7 +448,7 @@ static void gem_init_register_masks(CadenceGEMState *s) memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); s->regs_ro[GEM_NWCTRL] =3D 0xFFF80000; s->regs_ro[GEM_NWSTATUS] =3D 0xFFFFFFFF; - s->regs_ro[GEM_DMACFG] =3D 0xFE00F000; + s->regs_ro[GEM_DMACFG] =3D 0x8E00F000; s->regs_ro[GEM_TXSTATUS] =3D 0xFFFFFE08; s->regs_ro[GEM_RXQBASE] =3D 0x00000003; s->regs_ro[GEM_TXQBASE] =3D 0x00000003; @@ -807,7 +836,8 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q) DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]); /* read current descriptor */ cpu_physical_memory_read(s->rx_desc_addr[q], - (uint8_t *)s->rx_desc[q], sizeof(s->rx_desc[q= ])); + (uint8_t *)s->rx_desc[q], + sizeof(uint32_t) * gem_get_desc_len(s, true)); =20 /* Descriptor owned by software ? */ if (rx_desc_get_ownership(s->rx_desc[q]) =3D=3D 1) { @@ -926,9 +956,10 @@ static ssize_t gem_receive(NetClientState *nc, const u= int8_t *buf, size_t size) rx_desc_get_buffer(s->rx_desc[q])); =20 /* Copy packet data to emulated DMA buffer */ - cpu_physical_memory_write(rx_desc_get_buffer(s->rx_desc[q]) + - rxbuf_off= set, - rxbuf_ptr, MIN(bytes_to_copy, rxbufsize)= ); + cpu_physical_memory_write(rx_desc_get_buffer(s, s->rx_desc[q]) + + rxbuf_of= fset, + rxbuf_ptr, + MIN(bytes_to_copy, rxbufsize)); rxbuf_ptr +=3D MIN(bytes_to_copy, rxbufsize); bytes_to_copy -=3D MIN(bytes_to_copy, rxbufsize); =20 @@ -964,7 +995,7 @@ static ssize_t gem_receive(NetClientState *nc, const ui= nt8_t *buf, size_t size) /* Descriptor write-back. */ cpu_physical_memory_write(s->rx_desc_addr[q], (uint8_t *)s->rx_desc[q], - sizeof(s->rx_desc[q])); + sizeof(uint32_t) * gem_get_desc_len(s, t= rue)); =20 /* Next descriptor */ if (rx_desc_get_wrap(s->rx_desc[q])) { @@ -972,7 +1003,7 @@ static ssize_t gem_receive(NetClientState *nc, const u= int8_t *buf, size_t size) s->rx_desc_addr[q] =3D s->regs[GEM_RXQBASE]; } else { DB_PRINT("incrementing RX descriptor list\n"); - s->rx_desc_addr[q] +=3D 8; + s->rx_desc_addr[q] +=3D 4 * gem_get_desc_len(s, true); } =20 gem_get_rx_desc(s, q); @@ -1069,7 +1100,8 @@ static void gem_transmit(CadenceGEMState *s) =20 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); cpu_physical_memory_read(packet_desc_addr, - (uint8_t *)desc, sizeof(desc)); + (uint8_t *)desc, + sizeof(uint32_t) * gem_get_desc_len(s, fa= lse)); /* Handle all descriptors owned by hardware */ while (tx_desc_get_used(desc) =3D=3D 0) { =20 @@ -1082,7 +1114,7 @@ static void gem_transmit(CadenceGEMState *s) /* The real hardware would eat this (and possibly crash). * For QEMU let's lend a helping hand. */ - if ((tx_desc_get_buffer(desc) =3D=3D 0) || + if ((tx_desc_get_buffer(s, desc) =3D=3D 0) || (tx_desc_get_length(desc) =3D=3D 0)) { DB_PRINT("Invalid TX descriptor @ 0x%x\n", (unsigned)packet_desc_addr); @@ -1101,7 +1133,7 @@ static void gem_transmit(CadenceGEMState *s) /* Gather this fragment of the packet from "dma memory" to our * contig buffer. */ - cpu_physical_memory_read(tx_desc_get_buffer(desc), p, + cpu_physical_memory_read(tx_desc_get_buffer(s, desc), p, tx_desc_get_length(desc)); p +=3D tx_desc_get_length(desc); total_bytes +=3D tx_desc_get_length(desc); @@ -1124,7 +1156,8 @@ static void gem_transmit(CadenceGEMState *s) if (tx_desc_get_wrap(desc)) { s->tx_desc_addr[q] =3D s->regs[GEM_TXQBASE]; } else { - s->tx_desc_addr[q] =3D packet_desc_addr + 8; + s->tx_desc_addr[q] =3D packet_desc_addr + + 4 * gem_get_desc_len(s, false); } DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q= ]); =20 @@ -1168,11 +1201,11 @@ static void gem_transmit(CadenceGEMState *s) tx_desc_set_last(desc); packet_desc_addr =3D s->regs[GEM_TXQBASE]; } else { - packet_desc_addr +=3D 8; + packet_desc_addr +=3D 4 * gem_get_desc_len(s, false); } DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_a= ddr); - cpu_physical_memory_read(packet_desc_addr, - (uint8_t *)desc, sizeof(desc)); + cpu_physical_memory_read(packet_desc_addr, (uint8_t *)desc, + sizeof(uint32_t) * gem_get_desc_len(s, fal= se)); } =20 if (tx_desc_get_used(desc)) { --=20 2.19.0 From nobody Wed Apr 16 23:23:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539703557517888.8626068375521; Tue, 16 Oct 2018 08:25:57 -0700 (PDT) Received: from localhost ([::1]:58668 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCREK-0002Ad-6s for importer@patchew.org; Tue, 16 Oct 2018 11:25:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43064) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRCM-0000pz-5D for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRCL-0008ID-0h for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:54 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51904) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRCK-0007xg-LK for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:52 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRC9-0003or-FO for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:41 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:17 +0100 Message-Id: <20181016152325.31367-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 11/19] net: cadence_gem: Add support for selecting the DMA MemoryRegion X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Add support for selecting the Memory Region that the GEM will do DMA to. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Message-id: 20181011021931.4249-7-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- include/hw/net/cadence_gem.h | 2 ++ hw/net/cadence_gem.c | 59 ++++++++++++++++++++++-------------- 2 files changed, 39 insertions(+), 22 deletions(-) diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h index 00dbf4f72e3..5426961d91b 100644 --- a/include/hw/net/cadence_gem.h +++ b/include/hw/net/cadence_gem.h @@ -45,6 +45,8 @@ typedef struct CadenceGEMState { =20 /*< public >*/ MemoryRegion iomem; + MemoryRegion *dma_mr; + AddressSpace dma_as; NICState *nic; NICConf conf; qemu_irq irq[MAX_PRIORITY_QUEUES]; diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 759c1d71e02..a40f1362850 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -28,6 +28,7 @@ #include "hw/net/cadence_gem.h" #include "qapi/error.h" #include "qemu/log.h" +#include "sysemu/dma.h" #include "net/checksum.h" =20 #ifdef CADENCE_GEM_ERR_DEBUG @@ -835,9 +836,9 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q) { DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]); /* read current descriptor */ - cpu_physical_memory_read(s->rx_desc_addr[q], - (uint8_t *)s->rx_desc[q], - sizeof(uint32_t) * gem_get_desc_len(s, true)); + address_space_read(&s->dma_as, s->rx_desc_addr[q], MEMTXATTRS_UNSPECIF= IED, + (uint8_t *)s->rx_desc[q], + sizeof(uint32_t) * gem_get_desc_len(s, true)); =20 /* Descriptor owned by software ? */ if (rx_desc_get_ownership(s->rx_desc[q]) =3D=3D 1) { @@ -956,10 +957,10 @@ static ssize_t gem_receive(NetClientState *nc, const = uint8_t *buf, size_t size) rx_desc_get_buffer(s->rx_desc[q])); =20 /* Copy packet data to emulated DMA buffer */ - cpu_physical_memory_write(rx_desc_get_buffer(s, s->rx_desc[q]) + + address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q= ]) + rxbuf_of= fset, - rxbuf_ptr, - MIN(bytes_to_copy, rxbufsize)); + MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, + MIN(bytes_to_copy, rxbufsize)); rxbuf_ptr +=3D MIN(bytes_to_copy, rxbufsize); bytes_to_copy -=3D MIN(bytes_to_copy, rxbufsize); =20 @@ -993,9 +994,10 @@ static ssize_t gem_receive(NetClientState *nc, const u= int8_t *buf, size_t size) } =20 /* Descriptor write-back. */ - cpu_physical_memory_write(s->rx_desc_addr[q], - (uint8_t *)s->rx_desc[q], - sizeof(uint32_t) * gem_get_desc_len(s, t= rue)); + address_space_write(&s->dma_as, s->rx_desc_addr[q], + MEMTXATTRS_UNSPECIFIED, + (uint8_t *)s->rx_desc[q], + sizeof(uint32_t) * gem_get_desc_len(s, true)); =20 /* Next descriptor */ if (rx_desc_get_wrap(s->rx_desc[q])) { @@ -1099,9 +1101,9 @@ static void gem_transmit(CadenceGEMState *s) packet_desc_addr =3D s->tx_desc_addr[q]; =20 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); - cpu_physical_memory_read(packet_desc_addr, - (uint8_t *)desc, - sizeof(uint32_t) * gem_get_desc_len(s, fa= lse)); + address_space_read(&s->dma_as, packet_desc_addr, + MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, + sizeof(uint32_t) * gem_get_desc_len(s, false)); /* Handle all descriptors owned by hardware */ while (tx_desc_get_used(desc) =3D=3D 0) { =20 @@ -1133,8 +1135,9 @@ static void gem_transmit(CadenceGEMState *s) /* Gather this fragment of the packet from "dma memory" to our * contig buffer. */ - cpu_physical_memory_read(tx_desc_get_buffer(s, desc), p, - tx_desc_get_length(desc)); + address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), + MEMTXATTRS_UNSPECIFIED, + p, tx_desc_get_length(desc)); p +=3D tx_desc_get_length(desc); total_bytes +=3D tx_desc_get_length(desc); =20 @@ -1145,13 +1148,15 @@ static void gem_transmit(CadenceGEMState *s) /* Modify the 1st descriptor of this packet to be owned by * the processor. */ - cpu_physical_memory_read(s->tx_desc_addr[q], - (uint8_t *)desc_first, - sizeof(desc_first)); + address_space_read(&s->dma_as, s->tx_desc_addr[q], + MEMTXATTRS_UNSPECIFIED, + (uint8_t *)desc_first, + sizeof(desc_first)); tx_desc_set_used(desc_first); - cpu_physical_memory_write(s->tx_desc_addr[q], - (uint8_t *)desc_first, - sizeof(desc_first)); + address_space_write(&s->dma_as, s->tx_desc_addr[q], + MEMTXATTRS_UNSPECIFIED, + (uint8_t *)desc_first, + sizeof(desc_first)); /* Advance the hardware current descriptor past this packe= t */ if (tx_desc_get_wrap(desc)) { s->tx_desc_addr[q] =3D s->regs[GEM_TXQBASE]; @@ -1204,8 +1209,9 @@ static void gem_transmit(CadenceGEMState *s) packet_desc_addr +=3D 4 * gem_get_desc_len(s, false); } DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_a= ddr); - cpu_physical_memory_read(packet_desc_addr, (uint8_t *)desc, - sizeof(uint32_t) * gem_get_desc_len(s, fal= se)); + address_space_read(&s->dma_as, packet_desc_addr, + MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, + sizeof(uint32_t) * gem_get_desc_len(s, false= )); } =20 if (tx_desc_get_used(desc)) { @@ -1500,6 +1506,9 @@ static void gem_realize(DeviceState *dev, Error **err= p) CadenceGEMState *s =3D CADENCE_GEM(dev); int i; =20 + address_space_init(&s->dma_as, + s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); + if (s->num_priority_queues =3D=3D 0 || s->num_priority_queues > MAX_PRIORITY_QUEUES) { error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, @@ -1537,6 +1546,12 @@ static void gem_init(Object *obj) "enet", sizeof(s->regs)); =20 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); + + object_property_add_link(obj, "dma", TYPE_MEMORY_REGION, + (Object **)&s->dma_mr, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG, + &error_abort); } =20 static const VMStateDescription vmstate_cadence_gem =3D { --=20 2.19.0 From nobody Wed Apr 16 23:23:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539703722506511.94373990349334; Tue, 16 Oct 2018 08:28:42 -0700 (PDT) Received: from localhost ([::1]:58681 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRGz-0004qU-7n for importer@patchew.org; Tue, 16 Oct 2018 11:28:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43067) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRCM-0000qD-Fu for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRCL-0008L8-Jr for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:54 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51906) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRCL-000803-BU for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:23:53 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRCA-0003p9-Dv for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:42 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:18 +0100 Message-Id: <20181016152325.31367-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 12/19] net: cadence_gem: Implement support for 64bit descriptor addresses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Implement support for 64bit descriptor addresses. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias Message-id: 20181011021931.4249-8-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 47 ++++++++++++++++++++++++++++++++++++-------- 1 file changed, 39 insertions(+), 8 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index a40f1362850..550225c15be 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -153,6 +153,9 @@ #define GEM_RECEIVE_Q1_PTR (0x00000480 / 4) #define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6) =20 +#define GEM_TBQPH (0x000004C8 / 4) +#define GEM_RBQPH (0x000004D4 / 4) + #define GEM_INT_Q1_ENABLE (0x00000600 / 4) #define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6) =20 @@ -832,18 +835,42 @@ static int get_queue_from_screen(CadenceGEMState *s, = uint8_t *rxbuf_ptr, return 0; } =20 +static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) +{ + hwaddr desc_addr =3D 0; + + if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { + desc_addr =3D s->regs[tx ? GEM_TBQPH : GEM_RBQPH]; + } + desc_addr <<=3D 32; + desc_addr |=3D tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; + return desc_addr; +} + +static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q) +{ + return gem_get_desc_addr(s, true, q); +} + +static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q) +{ + return gem_get_desc_addr(s, false, q); +} + static void gem_get_rx_desc(CadenceGEMState *s, int q) { - DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]); + hwaddr desc_addr =3D gem_get_rx_desc_addr(s, q); + + DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); + /* read current descriptor */ - address_space_read(&s->dma_as, s->rx_desc_addr[q], MEMTXATTRS_UNSPECIF= IED, + address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->rx_desc[q], sizeof(uint32_t) * gem_get_desc_len(s, true)); =20 /* Descriptor owned by software ? */ if (rx_desc_get_ownership(s->rx_desc[q]) =3D=3D 1) { - DB_PRINT("descriptor 0x%x owned by sw.\n", - (unsigned)s->rx_desc_addr[q]); + DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr= ); s->regs[GEM_RXSTATUS] |=3D GEM_RXSTATUS_NOBUF; s->regs[GEM_ISR] |=3D GEM_INT_RXUSED & ~(s->regs[GEM_IMR]); /* Handle interrupt consequences */ @@ -947,6 +974,8 @@ static ssize_t gem_receive(NetClientState *nc, const ui= nt8_t *buf, size_t size) q =3D get_queue_from_screen(s, rxbuf_ptr, rxbufsize); =20 while (bytes_to_copy) { + hwaddr desc_addr; + /* Do nothing if receive is not enabled. */ if (!gem_can_receive(nc)) { assert(!first_desc); @@ -994,7 +1023,8 @@ static ssize_t gem_receive(NetClientState *nc, const u= int8_t *buf, size_t size) } =20 /* Descriptor write-back. */ - address_space_write(&s->dma_as, s->rx_desc_addr[q], + desc_addr =3D gem_get_rx_desc_addr(s, q); + address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->rx_desc[q], sizeof(uint32_t) * gem_get_desc_len(s, true)); @@ -1098,7 +1128,7 @@ static void gem_transmit(CadenceGEMState *s) =20 for (q =3D s->num_priority_queues - 1; q >=3D 0; q--) { /* read current descriptor */ - packet_desc_addr =3D s->tx_desc_addr[q]; + packet_desc_addr =3D gem_get_tx_desc_addr(s, q); =20 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); address_space_read(&s->dma_as, packet_desc_addr, @@ -1144,16 +1174,17 @@ static void gem_transmit(CadenceGEMState *s) /* Last descriptor for this packet; hand the whole thing off */ if (tx_desc_get_last(desc)) { uint32_t desc_first[DESC_MAX_NUM_WORDS]; + hwaddr desc_addr =3D gem_get_tx_desc_addr(s, q); =20 /* Modify the 1st descriptor of this packet to be owned by * the processor. */ - address_space_read(&s->dma_as, s->tx_desc_addr[q], + address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc_first, sizeof(desc_first)); tx_desc_set_used(desc_first); - address_space_write(&s->dma_as, s->tx_desc_addr[q], + address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc_first, sizeof(desc_first)); --=20 2.19.0 From nobody Wed Apr 16 23:23:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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Tue, 16 Oct 2018 11:24:37 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51904) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRD2-0007xg-63 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:36 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRCB-0003pN-CF for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:43 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:19 +0100 Message-Id: <20181016152325.31367-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 13/19] net: cadence_gem: Announce 64bit addressing support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Announce 64bit addressing support. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias Message-id: 20181011021931.4249-9-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 550225c15be..7f96de4affa 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -142,6 +142,7 @@ #define GEM_DESCONF4 (0x0000028C/4) #define GEM_DESCONF5 (0x00000290/4) #define GEM_DESCONF6 (0x00000294/4) +#define GEM_DESCONF6_64B_MASK (1U << 23) #define GEM_DESCONF7 (0x00000298/4) =20 #define GEM_INT_Q1_STATUS (0x00000400 / 4) @@ -1300,7 +1301,7 @@ static void gem_reset(DeviceState *d) s->regs[GEM_DESCONF] =3D 0x02500111; s->regs[GEM_DESCONF2] =3D 0x2ab13fff; s->regs[GEM_DESCONF5] =3D 0x002f2045; - s->regs[GEM_DESCONF6] =3D 0x0; + s->regs[GEM_DESCONF6] =3D GEM_DESCONF6_64B_MASK; =20 queues_mask =3D MAKE_64BIT_MASK(1, s->num_priority_queues - 1); s->regs[GEM_DESCONF6] |=3D queues_mask; --=20 2.19.0 From nobody Wed Apr 16 23:23:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539704524386625.8492308546316; Tue, 16 Oct 2018 08:42:04 -0700 (PDT) Received: from localhost ([::1]:58761 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRTq-0008E4-9I for importer@patchew.org; Tue, 16 Oct 2018 11:41:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43306) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRD2-0001T8-KF for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRD1-0000oh-PN for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:36 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51906) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRD1-000803-Du for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:35 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRCC-0003pb-9U for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:44 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:20 +0100 Message-Id: <20181016152325.31367-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 14/19] target-arm: powerctl: Enable HVC when starting CPUs to EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" When QEMU provides the equivalent of the EL3 firmware, we need to enable HVCs in scr_el3 when turning on CPUs that target EL2. Reviewed-by: Peter Maydell Signed-off-by: Edgar E. Iglesias Message-id: 20181011021931.4249-10-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- target/arm/arm-powerctl.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index ce55eeb682b..2b856930fb7 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -103,6 +103,16 @@ static void arm_set_cpu_on_async_work(CPUState *target= _cpu_state, } else { /* Processor is not in secure mode */ target_cpu->env.cp15.scr_el3 |=3D SCR_NS; + + /* + * If QEMU is providing the equivalent of EL3 firmware, then we ne= ed + * to make sure a CPU targeting EL2 comes out of reset with a + * functional HVC insn. + */ + if (arm_feature(&target_cpu->env, ARM_FEATURE_EL3) + && info->target_el =3D=3D 2) { + target_cpu->env.cp15.scr_el3 |=3D SCR_HCE; + } } =20 /* We check if the started CPU is now at the correct level */ --=20 2.19.0 From nobody Wed Apr 16 23:23:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539704398139211.46298561363017; Tue, 16 Oct 2018 08:39:58 -0700 (PDT) Received: from localhost ([::1]:58746 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRRo-0006SW-Qh for importer@patchew.org; Tue, 16 Oct 2018 11:39:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43300) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRD2-0001Su-CA for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRD1-0000o7-CX for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:36 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51904) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRCx-0007xg-GF for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:33 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRCD-0003pp-6q for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:45 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:21 +0100 Message-Id: <20181016152325.31367-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 15/19] target/arm: Add the Cortex-A72 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Add the ARM Cortex-A72. Signed-off-by: Edgar E. Iglesias Message-id: 20181011021931.4249-11-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 66 +++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 63 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index db71504cb5c..44fdf0f6fa2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -51,7 +51,7 @@ static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, con= st ARMCPRegInfo *ri) } #endif =20 -static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] =3D { +static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] =3D { #ifndef CONFIG_USER_ONLY { .name =3D "L2CTLR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 2, @@ -156,7 +156,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } =20 static void aarch64_a53_initfn(Object *obj) @@ -215,7 +215,66 @@ static void aarch64_a53_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); +} + +static void aarch64_a72_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a72"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_V8_AES); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); + set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x410fd083; + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034080; + cpu->mvfr0 =3D 0x10110222; + cpu->mvfr1 =3D 0x12111111; + cpu->mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x8444c004; + cpu->reset_sctlr =3D 0x00c50838; + cpu->id_pfr0 =3D 0x00000131; + cpu->id_pfr1 =3D 0x00011011; + cpu->id_dfr0 =3D 0x03010066; + cpu->id_afr0 =3D 0x00000000; + cpu->id_mmfr0 =3D 0x10201105; + cpu->id_mmfr1 =3D 0x40000000; + cpu->id_mmfr2 =3D 0x01260000; + cpu->id_mmfr3 =3D 0x02102211; + cpu->id_isar0 =3D 0x02101110; + cpu->id_isar1 =3D 0x13112111; + cpu->id_isar2 =3D 0x21232042; + cpu->id_isar3 =3D 0x01112131; + cpu->id_isar4 =3D 0x00011142; + cpu->id_isar5 =3D 0x00011121; + cpu->id_aa64pfr0 =3D 0x00002222; + cpu->id_aa64dfr0 =3D 0x10305106; + cpu->pmceid0 =3D 0x00000000; + cpu->pmceid1 =3D 0x00000000; + cpu->id_aa64isar0 =3D 0x00011120; + cpu->id_aa64mmfr0 =3D 0x00001124; + cpu->dbgdidr =3D 0x3516d000; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] =3D 0x707fe07a; /* 1MB L2 cache */ + cpu->dcz_blocksize =3D 4; /* 64 bytes */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } =20 static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, @@ -293,6 +352,7 @@ typedef struct ARMCPUInfo { static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, + { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, { .name =3D NULL } }; --=20 2.19.0 From nobody Wed Apr 16 23:23:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 153970439814270.85636370855548; Tue, 16 Oct 2018 08:39:58 -0700 (PDT) Received: from localhost ([::1]:58745 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRRe-0006KR-Si for importer@patchew.org; Tue, 16 Oct 2018 11:39:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43222) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRCk-0001Cu-QY for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRCh-0000SY-RK for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:17 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51906) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRCh-000803-ER for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:15 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRCE-0003q3-6E for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:46 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:22 +0100 Message-Id: <20181016152325.31367-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 16/19] target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Aaron Lindsay I previously fixed this for PMINTENSET_EL1, but missed these. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson Message-id: 20181010203735.27918-2-aclindsa@gmail.com Signed-off-by: Peter Maydell --- target/arm/helper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0efbb5c76ce..138a1f15405 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1423,12 +1423,14 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .writefn =3D pmintenset_write, .raw_writefn =3D raw_write, .resetvalue =3D 0x0 }, { .name =3D "PMINTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tpm, .type =3D ARM_CP_ALIAS, + .access =3D PL1_RW, .accessfn =3D access_tpm, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), .writefn =3D pmintenclr_write, }, { .name =3D "PMINTENCLR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tpm, .type =3D ARM_CP_ALIAS, + .access =3D PL1_RW, .accessfn =3D access_tpm, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), .writefn =3D pmintenclr_write }, { .name =3D "CCSIDR", .state =3D ARM_CP_STATE_BOTH, --=20 2.19.0 From nobody Wed Apr 16 23:23:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539704250532205.36155671469203; Tue, 16 Oct 2018 08:37:30 -0700 (PDT) Received: from localhost ([::1]:58734 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRPV-0004LO-Aj for importer@patchew.org; Tue, 16 Oct 2018 11:37:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43214) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRCj-0001Bp-NN for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRCh-0000Rb-5I for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:16 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51904) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRCg-0007xg-UK for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:15 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRCF-0003qH-4g for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:47 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:23 +0100 Message-Id: <20181016152325.31367-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 17/19] target/arm: Mask PMOVSR writes based on supported counters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Aaron Lindsay This is an amendment to my earlier patch: commit 7ece99b17e832065236c07a158dfac62619ef99b Author: Aaron Lindsay Date: Thu Apr 26 11:04:39 2018 +0100 target/arm: Mask PMU register writes based on PMCR_EL0.N Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson Message-id: 20181010203735.27918-3-aclindsa@gmail.com Signed-off-by: Peter Maydell --- target/arm/helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 138a1f15405..7a53098888d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1179,6 +1179,7 @@ static void pmcntenclr_write(CPUARMState *env, const = ARMCPRegInfo *ri, static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + value &=3D pmu_counter_mask(env); env->cp15.c9_pmovsr &=3D ~value; } =20 --=20 2.19.0 From nobody Wed Apr 16 23:23:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153970423856216.887281466631748; Tue, 16 Oct 2018 08:37:18 -0700 (PDT) Received: from localhost ([::1]:58733 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRPJ-0004AF-33 for importer@patchew.org; Tue, 16 Oct 2018 11:37:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43175) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRCX-0000z7-CQ for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRCW-0000Aj-Lx for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:05 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51906) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRCW-000803-DL for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:04 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRCG-0003qV-1y for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:48 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:24 +0100 Message-Id: <20181016152325.31367-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 18/19] target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The get_phys_addr() functions take a pointer to an ARMMMUFaultInfo struct, which they fill in only if a fault occurs. This means that the caller must always zero-initialize the struct before passing it in. We forgot to do this in v7m_stack_read() and v7m_stack_write(). Correct the error. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20181011172057.9466-1-peter.maydell@linaro.org --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7a53098888d..e3946562aa1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6472,7 +6472,7 @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t add= r, uint32_t value, target_ulong page_size; hwaddr physaddr; int prot; - ARMMMUFaultInfo fi; + ARMMMUFaultInfo fi =3D {}; bool secure =3D mmu_idx & ARM_MMU_IDX_M_S; int exc; bool exc_secure; @@ -6534,7 +6534,7 @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *des= t, uint32_t addr, target_ulong page_size; hwaddr physaddr; int prot; - ARMMMUFaultInfo fi; + ARMMMUFaultInfo fi =3D {}; bool secure =3D mmu_idx & ARM_MMU_IDX_M_S; int exc; bool exc_secure; --=20 2.19.0 From nobody Wed Apr 16 23:23:32 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539704062087964.6183006867765; Tue, 16 Oct 2018 08:34:22 -0700 (PDT) Received: from localhost ([::1]:58712 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRMP-0001mt-ME for importer@patchew.org; Tue, 16 Oct 2018 11:34:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43168) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gCRCW-0000yh-T6 for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gCRCW-0000A4-4P for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:04 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51904) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gCRCV-0007xg-Re for qemu-devel@nongnu.org; Tue, 16 Oct 2018 11:24:04 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gCRCH-0003qj-0Q for qemu-devel@nongnu.org; Tue, 16 Oct 2018 16:23:49 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2018 16:23:25 +0100 Message-Id: <20181016152325.31367-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181016152325.31367-1-peter.maydell@linaro.org> References: <20181016152325.31367-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 19/19] coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add a new Coccinelle script which replaces uses of the inplace byteswapping functions *_to_cpus() and cpu_to_*s() with their not-in-place equivalents. This is useful for where the swapping is done on members of a packed struct -- taking the address of the member to pass it to an inplace function is undefined behaviour in C. Signed-off-by: Peter Maydell Reviewed-by: Eric Blake Reviewed-by: Richard Henderson Message-id: 20181009181612.10633-1-peter.maydell@linaro.org --- scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci diff --git a/scripts/coccinelle/inplace-byteswaps.cocci b/scripts/coccinell= e/inplace-byteswaps.cocci new file mode 100644 index 00000000000..a869a90cbfd --- /dev/null +++ b/scripts/coccinelle/inplace-byteswaps.cocci @@ -0,0 +1,65 @@ +// Replace uses of in-place byteswapping functions with calls to the +// equivalent not-in-place functions. This is necessary to avoid +// undefined behaviour if the expression being swapped is a field in a +// packed struct. + +@@ +expression E; +@@ +-be16_to_cpus(&E); ++E =3D be16_to_cpu(E); +@@ +expression E; +@@ +-be32_to_cpus(&E); ++E =3D be32_to_cpu(E); +@@ +expression E; +@@ +-be64_to_cpus(&E); ++E =3D be64_to_cpu(E); +@@ +expression E; +@@ +-cpu_to_be16s(&E); ++E =3D cpu_to_be16(E); +@@ +expression E; +@@ +-cpu_to_be32s(&E); ++E =3D cpu_to_be32(E); +@@ +expression E; +@@ +-cpu_to_be64s(&E); ++E =3D cpu_to_be64(E); +@@ +expression E; +@@ +-le16_to_cpus(&E); ++E =3D le16_to_cpu(E); +@@ +expression E; +@@ +-le32_to_cpus(&E); ++E =3D le32_to_cpu(E); +@@ +expression E; +@@ +-le64_to_cpus(&E); ++E =3D le64_to_cpu(E); +@@ +expression E; +@@ +-cpu_to_le16s(&E); ++E =3D cpu_to_le16(E); +@@ +expression E; +@@ +-cpu_to_le32s(&E); ++E =3D cpu_to_le32(E); +@@ +expression E; +@@ +-cpu_to_le64s(&E); ++E =3D cpu_to_le64(E); --=20 2.19.0