Switched to a new branch '20181016152325.31367-1-peter.maydell@linaro.org'
Applying: hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
Applying: target/arm: Fix aarch64_sve_change_el wrt EL0
Applying: target/arm: Define fields of ISAR registers
Applying: target/arm: Align cortex-r5 id_isar0
Applying: target/arm: Fix cortex-a7 id_isar0
Applying: net: cadence_gem: Disable TSU feature bit
Applying: net: cadence_gem: Announce availability of priority queues
Applying: net: cadence_gem: Use uint32_t for 32bit descriptor words
Applying: net: cadence_gem: Add macro with max number of descriptor words
Applying: net: cadence_gem: Add support for extended descriptors
Applying: net: cadence_gem: Add support for selecting the DMA MemoryRegion
Applying: net: cadence_gem: Implement support for 64bit descriptor addresses
Applying: net: cadence_gem: Announce 64bit addressing support
Applying: target-arm: powerctl: Enable HVC when starting CPUs to EL2
Applying: target/arm: Add the Cortex-A72
Applying: target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
Applying: target/arm: Mask PMOVSR writes based on supported counters
Applying: target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
Applying: coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
To https://github.com/patchew-project/qemu
 * [new tag]               patchew/20181016152325.31367-1-peter.maydell@linaro.org -> patchew/20181016152325.31367-1-peter.maydell@linaro.org