From nobody Mon Feb 9 19:30:37 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539473317570554.9660503344707; Sat, 13 Oct 2018 16:28:37 -0700 (PDT) Received: from localhost ([::1]:46579 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gBTKd-0000Fs-Mn for importer@patchew.org; Sat, 13 Oct 2018 19:28:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57941) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gBTCn-0002fO-Kt for qemu-devel@nongnu.org; Sat, 13 Oct 2018 19:20:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gBTCd-0007xa-81 for qemu-devel@nongnu.org; Sat, 13 Oct 2018 19:20:16 -0400 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:41721) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gBTCd-0007wO-0a for qemu-devel@nongnu.org; Sat, 13 Oct 2018 19:20:11 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 265B821A29; Sat, 13 Oct 2018 19:20:09 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Sat, 13 Oct 2018 19:20:09 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id A8697102A0; Sat, 13 Oct 2018 19:20:08 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h= from:to:cc:subject:date:message-id:in-reply-to:references; s= mesmtp; bh=QQHyvpjd7NFW2KQnJQFoSPenvfKqrNScxjJXfUrF0kA=; b=em6/P VO0qHng82zosZY644H67THJzf54UFyebO7pmf9BAl7JTXGGjC9LtBUvDqjJgSRUQ oMEBCDQGcTvk6lis7YHQSl/zZYN6rmmS5vbecdwPmFaSt+Zf8MaFwXp6BPifUMvg Eb19KhwtqVZV2tYkm6f8S3P3jfD9D11xapqwWw= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-proxy:x-me-proxy:x-me-sender :x-me-sender:x-sasl-enc; s=fm1; bh=QQHyvpjd7NFW2KQnJQFoSPenvfKqr NScxjJXfUrF0kA=; b=FBjSnmCVJ06BLq7q+D8t2sAhVCzThKCsKSjawY0USNubg z3ThjF2dan7OHJRJyRF6ttvospuzLsVujb3RBEHGl0RxRCwLqy29W5wVEhlkt6yD /aKC/l+gl3/KcKX2YJ8YMyPEFoXXecmAOdfe7ZaKKKl8aASPuEapDHJSXMU9v38/ dN93dalSOkV1Wy6Y2hnDih9DucZ9Al+SbHh8f5wah3tFpQ5DIyAtWRuF1jLTHCW4 ZjNhfaCNEZGyyz2ydK6vsfj6q1YTedPmH5jet6MlEq3qtzZmliTkltH/bs9IjmM1 ctSwPngTMsflp0htcWw0mZkKewfLnQXrKbEAgJ8oA== X-ME-Sender: X-ME-Proxy: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sat, 13 Oct 2018 19:19:28 -0400 Message-Id: <20181013231933.28789-9-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181013231933.28789-1-cota@braap.org> References: <20181013231933.28789-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.111.4.27 Subject: [Qemu-devel] [PATCH v5 08/13] hardfloat: implement float32/64 addition and subtraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Performance results (single and double precision) for fp-bench: 1. Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz - before: add-single: 135.07 MFlops add-double: 131.60 MFlops sub-single: 130.04 MFlops sub-double: 133.01 MFlops - after: add-single: 443.04 MFlops add-double: 301.95 MFlops sub-single: 411.36 MFlops sub-double: 293.15 MFlops 2. ARM Aarch64 A57 @ 2.4GHz - before: add-single: 44.79 MFlops add-double: 49.20 MFlops sub-single: 44.55 MFlops sub-double: 49.06 MFlops - after: add-single: 93.28 MFlops add-double: 88.27 MFlops sub-single: 91.47 MFlops sub-double: 88.27 MFlops 3. IBM POWER8E @ 2.1 GHz - before: add-single: 72.59 MFlops add-double: 72.27 MFlops sub-single: 75.33 MFlops sub-double: 70.54 MFlops - after: add-single: 112.95 MFlops add-double: 201.11 MFlops sub-single: 116.80 MFlops sub-double: 188.72 MFlops Note that the IBM and ARM machines benefit from having HARDFLOAT_2F{32,64}_USE_FP set to 0. Otherwise their performance can suffer significantly: - IBM Power8: add-single: [1] 54.94 vs [0] 116.37 MFlops add-double: [1] 58.92 vs [0] 201.44 MFlops - Aarch64 A57: add-single: [1] 80.72 vs [0] 93.24 MFlops add-double: [1] 82.10 vs [0] 88.18 MFlops On the Intel machine, having 2F64 set to 1 pays off, but it doesn't for 2F32: - Intel i7-6700K: add-single: [1] 285.79 vs [0] 426.70 MFlops add-double: [1] 302.15 vs [0] 278.82 MFlops Signed-off-by: Emilio G. Cota --- fpu/softfloat.c | 106 ++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 98 insertions(+), 8 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 81d06548b5..d5d1c555dc 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1077,8 +1077,8 @@ float16 __attribute__((flatten)) float16_add(float16= a, float16 b, return float16_round_pack_canonical(pr, status); } =20 -float32 __attribute__((flatten)) float32_add(float32 a, float32 b, - float_status *status) +static float32 QEMU_SOFTFLOAT_ATTR +soft_float32_add(float32 a, float32 b, float_status *status) { FloatParts pa =3D float32_unpack_canonical(a, status); FloatParts pb =3D float32_unpack_canonical(b, status); @@ -1087,8 +1087,8 @@ float32 __attribute__((flatten)) float32_add(float32 = a, float32 b, return float32_round_pack_canonical(pr, status); } =20 -float64 __attribute__((flatten)) float64_add(float64 a, float64 b, - float_status *status) +static float64 QEMU_SOFTFLOAT_ATTR +soft_float64_add(float64 a, float64 b, float_status *status) { FloatParts pa =3D float64_unpack_canonical(a, status); FloatParts pb =3D float64_unpack_canonical(b, status); @@ -1107,8 +1107,8 @@ float16 __attribute__((flatten)) float16_sub(float16 = a, float16 b, return float16_round_pack_canonical(pr, status); } =20 -float32 __attribute__((flatten)) float32_sub(float32 a, float32 b, - float_status *status) +static float32 QEMU_SOFTFLOAT_ATTR +soft_float32_sub(float32 a, float32 b, float_status *status) { FloatParts pa =3D float32_unpack_canonical(a, status); FloatParts pb =3D float32_unpack_canonical(b, status); @@ -1117,8 +1117,8 @@ float32 __attribute__((flatten)) float32_sub(float32 = a, float32 b, return float32_round_pack_canonical(pr, status); } =20 -float64 __attribute__((flatten)) float64_sub(float64 a, float64 b, - float_status *status) +static float64 QEMU_SOFTFLOAT_ATTR +soft_float64_sub(float64 a, float64 b, float_status *status) { FloatParts pa =3D float64_unpack_canonical(a, status); FloatParts pb =3D float64_unpack_canonical(b, status); @@ -1127,6 +1127,96 @@ float64 __attribute__((flatten)) float64_sub(float64= a, float64 b, return float64_round_pack_canonical(pr, status); } =20 +static float float_add(float a, float b) +{ + return a + b; +} + +static float float_sub(float a, float b) +{ + return a - b; +} + +static double double_add(double a, double b) +{ + return a + b; +} + +static double double_sub(double a, double b) +{ + return a - b; +} + +static bool f32_addsub_post(float32 a, float32 b, const struct float_statu= s *s) +{ + return !(float32_is_zero(a) && float32_is_zero(b)); +} + +static bool +float_addsub_post(float a, float b, const struct float_status *s) +{ + return !(fpclassify(a) =3D=3D FP_ZERO && fpclassify(b) =3D=3D FP_ZERO); +} + +static bool f64_addsub_post(float64 a, float64 b, const struct float_statu= s *s) +{ + return !(float64_is_zero(a) && float64_is_zero(b)); +} + +static bool +double_addsub_post(double a, double b, const struct float_status *s) +{ + return !(fpclassify(a) =3D=3D FP_ZERO && fpclassify(b) =3D=3D FP_ZERO); +} + +static float32 float32_addsub(float32 a, float32 b, float_status *s, + float_op2_func_t hard, f32_op2_func_t soft) +{ + if (QEMU_HARDFLOAT_2F32_USE_FP) { + return float_gen2(a, b, s, hard, soft, float_is_zon2, float_addsub= _post, + NULL, NULL); + } else { + return f32_gen2(a, b, s, hard, soft, f32_is_zon2, f32_addsub_post, + NULL, NULL); + } +} + +static float64 float64_addsub(float64 a, float64 b, float_status *s, + double_op2_func_t hard, f64_op2_func_t soft) +{ + if (QEMU_HARDFLOAT_2F64_USE_FP) { + return double_gen2(a, b, s, hard, soft, double_is_zon2, + double_addsub_post, NULL, NULL); + } else { + return f64_gen2(a, b, s, hard, soft, f64_is_zon2, f64_addsub_post, + NULL, NULL); + } +} + +float32 __attribute__((flatten)) +float32_add(float32 a, float32 b, float_status *s) +{ + return float32_addsub(a, b, s, float_add, soft_float32_add); +} + +float32 __attribute__((flatten)) +float32_sub(float32 a, float32 b, float_status *s) +{ + return float32_addsub(a, b, s, float_sub, soft_float32_sub); +} + +float64 __attribute__((flatten)) +float64_add(float64 a, float64 b, float_status *s) +{ + return float64_addsub(a, b, s, double_add, soft_float64_add); +} + +float64 __attribute__((flatten)) +float64_sub(float64 a, float64 b, float_status *s) +{ + return float64_addsub(a, b, s, double_sub, soft_float64_sub); +} + /* * Returns the result of multiplying the floating-point values `a' and * `b'. The operation is performed according to the IEC/IEEE Standard --=20 2.17.1