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X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH 02/28] target/riscv: Convert RVXI branch insns to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 19 +++++++++ target/riscv/insn_trans/trans_rvi.inc.c | 52 +++++++++++++++++++++++++ target/riscv/translate.c | 19 +-------- 3 files changed, 72 insertions(+), 18 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 44d4e922b6..b49913416d 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -17,14 +17,33 @@ # this program. If not, see . =20 # Fields: +%rs2 20:5 +%rs1 15:5 %rd 7:5 =20 # immediates: +%imm_i 20:s12 +%imm_b 31:s1 7:1 25:6 8:4 !function=3Dex_shift_1 +%imm_j 31:s1 12:8 20:1 21:10 !function=3Dex_shift_1 %imm_u 12:s20 !function=3Dex_shift_12 =20 +# Argument sets: +&branch imm rs2 rs1 + # Formats 32: +@i ............ ..... ... ..... ....... imm=3D%imm_i = %rs1 %rd +@b ....... ..... ..... ... ..... ....... &branch imm=3D%imm_b %rs2= %rs1 @u .................... ..... ....... imm=3D%imm_u = %rd +@j .................... ..... ....... imm=3D%imm_j = %rd =20 # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u auipc .................... ..... 0010111 @u +jal .................... ..... 1101111 @j +jalr ............ ..... 000 ..... 1100111 @i +beq ....... ..... ..... 000 ..... 1100011 @b +bne ....... ..... ..... 001 ..... 1100011 @b +blt ....... ..... ..... 100 ..... 1100011 @b +bge ....... ..... ..... 101 ..... 1100011 @b +bltu ....... ..... ..... 110 ..... 1100011 @b +bgeu ....... ..... ..... 111 ..... 1100011 @b diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index aee0d1637d..83345d71d7 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -33,3 +33,55 @@ static bool trans_auipc(DisasContext *ctx, arg_auipc *a,= uint32_t insn) } return true; } + +static bool trans_jal(DisasContext *ctx, arg_jal *a, uint32_t insn) +{ + CPURISCVState *env =3D current_cpu->env_ptr; + gen_jal(env, ctx, a->rd, a->imm); + return true; +} + +static bool trans_jalr(DisasContext *ctx, arg_jalr *a, uint32_t insn) +{ + CPURISCVState *env =3D current_cpu->env_ptr; + gen_jalr(env, ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm); + return true; +} + +static bool trans_beq(DisasContext *ctx, arg_beq *a, uint32_t insn) +{ + CPURISCVState *env =3D current_cpu->env_ptr; + gen_branch(env, ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm); + return true; +} +static bool trans_bne(DisasContext *ctx, arg_bne *a, uint32_t insn) +{ + CPURISCVState *env =3D current_cpu->env_ptr; + gen_branch(env, ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm); + return true; +} +static bool trans_blt(DisasContext *ctx, arg_blt *a, uint32_t insn) +{ + CPURISCVState *env =3D current_cpu->env_ptr; + gen_branch(env, ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm); + return true; +} +static bool trans_bge(DisasContext *ctx, arg_bge *a, uint32_t insn) +{ + CPURISCVState *env =3D current_cpu->env_ptr; + gen_branch(env, ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm); + return true; +} +static bool trans_bltu(DisasContext *ctx, arg_bltu *a, uint32_t insn) +{ + CPURISCVState *env =3D current_cpu->env_ptr; + gen_branch(env, ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm); + return true; +} +static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a, uint32_t insn) +{ + + CPURISCVState *env =3D current_cpu->env_ptr; + gen_branch(env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm); + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 2ee886c6b7..8181ad7419 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1671,6 +1671,7 @@ static void decode_RV32_64C(CPURISCVState *env, Disas= Context *ctx) { \ return imm << amount; \ } +EX_SH(1) EX_SH(12) =20 bool decode_insn32(DisasContext *ctx, uint32_t insn); @@ -1699,24 +1700,6 @@ static void decode_RV32_64G(CPURISCVState *env, Disa= sContext *ctx) imm =3D GET_IMM(ctx->opcode); =20 switch (op) { - case OPC_RISC_AUIPC: - if (rd =3D=3D 0) { - break; /* NOP */ - } - tcg_gen_movi_tl(cpu_gpr[rd], (sextract64(ctx->opcode, 12, 20) << 1= 2) + - ctx->base.pc_next); - break; - case OPC_RISC_JAL: - imm =3D GET_JAL_IMM(ctx->opcode); - gen_jal(env, ctx, rd, imm); - break; - case OPC_RISC_JALR: - gen_jalr(env, ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm); - break; - case OPC_RISC_BRANCH: - gen_branch(env, ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2, - GET_B_IMM(ctx->opcode)); - break; case OPC_RISC_LOAD: gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm); break; --=20 2.19.1