From nobody Thu Nov 6 04:23:57 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=mail.uni-paderborn.de Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539367332499795.246604326526; Fri, 12 Oct 2018 11:02:12 -0700 (PDT) Received: from localhost ([::1]:42062 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB1lL-0007T8-DK for importer@patchew.org; Fri, 12 Oct 2018 14:02:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40111) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gB1Ht-00020a-Hy for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gB1Hs-0000UU-7r for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:45 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:33852) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gB1Hr-0000H3-Rd for qemu-devel@nongnu.org; Fri, 12 Oct 2018 13:31:44 -0400 Received: from wormulon.uni-paderborn.de ([131.234.189.22] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 hoth) id 1gB1Hf-00066L-QQ; Fri, 12 Oct 2018 19:31:31 +0200 Received: from mail.uni-paderborn.de by wormulon with queue id 2934322-5; Fri, 12 Oct 2018 17:31:30 GMT Received: from aftr-95-222-26-80.unity-media.net ([95.222.26.80] helo=schnipp.lan) by mail.uni-paderborn.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89 nylar) id 1gB1He-0006OT-PO; Fri, 12 Oct 2018 19:31:30 +0200 X-Envelope-From: From: Bastian Koppelmann To: mjc@sifive.com, palmer@sifive.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de Date: Fri, 12 Oct 2018 19:30:47 +0200 Message-Id: <20181012173047.25420-29-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de> References: <20181012173047.25420-1-kbastian@mail.uni-paderborn.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-PMX-Version: 6.4.5.2775670, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2018.10.12.172416, AntiVirus-Engine: 5.53.0, AntiVirus-Data: 2018.10.10.5530001 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH 28/28] target/riscv: Replace gen_exception_illegal with return false X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" return false in trans_* instructions is no longer used as a fallback to the old decoder. We can therefore now use 'return false' to indicate an ill= egal instruction. Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- .../riscv/insn_trans/trans_privileged.inc.c | 6 ++---- target/riscv/insn_trans/trans_rvc.inc.c | 21 +++++++------------ target/riscv/insn_trans/trans_rvd.inc.c | 14 ++++++------- target/riscv/insn_trans/trans_rvf.inc.c | 10 ++++----- target/riscv/insn_trans/trans_rvi.inc.c | 18 ++++++---------- target/riscv/translate.c | 1 + 6 files changed, 28 insertions(+), 42 deletions(-) diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/= insn_trans/trans_privileged.inc.c index 9534adb025..f378c3852e 100644 --- a/target/riscv/insn_trans/trans_privileged.inc.c +++ b/target/riscv/insn_trans/trans_privileged.inc.c @@ -37,8 +37,7 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a= , uint32_t insn) =20 static bool trans_uret(DisasContext *ctx, arg_uret *a, uint32_t insn) { - gen_exception_illegal(ctx); - return true; + return false; } =20 static bool trans_sret(DisasContext *ctx, arg_sret *a, uint32_t insn) @@ -61,8 +60,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a, ui= nt32_t insn) =20 static bool trans_hret(DisasContext *ctx, arg_hret *a, uint32_t insn) { - gen_exception_illegal(ctx); - return true; + return false; } =20 static bool trans_mret(DisasContext *ctx, arg_mret *a, uint32_t insn) diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_tr= ans/trans_rvc.inc.c index b98c18d99e..43e9e6e1ac 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -23,8 +23,7 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_add= i4spn *a, { if (a->nzuimm =3D=3D 0) { /* Reserved in ISA */ - gen_exception_illegal(ctx); - return true; + return false; } arg_addi arg =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->nzuimm }; return trans_addi(ctx, &arg, insn); @@ -144,14 +143,12 @@ static bool trans_c_srli(DisasContext *ctx, arg_c_srl= i *a, uint16_t insn) { if (a->shamt =3D=3D 0) { /* Reserved in ISA */ - gen_exception_illegal(ctx); - return true; + return false; } #ifdef TARGET_RISCV32 /* Ensure, that shamt[5] is zero for RV32 */ if (a->shamt >=3D 32) { - gen_exception_illegal(ctx); - return true; + return false; } #endif =20 @@ -163,14 +160,12 @@ static bool trans_c_srai(DisasContext *ctx, arg_c_sra= i *a, uint16_t insn) { if (a->shamt =3D=3D 0) { /* Reserved in ISA */ - gen_exception_illegal(ctx); - return true; + return false; } #ifdef TARGET_RISCV32 /* Ensure, that shamt[5] is zero for RV32 */ if (a->shamt >=3D 32) { - gen_exception_illegal(ctx); - return true; + return false; } #endif =20 @@ -242,15 +237,13 @@ static bool trans_c_slli(DisasContext *ctx, arg_c_sll= i *a, uint16_t insn) { if (a->shamt =3D=3D 0) { /* Reserved in ISA */ - gen_exception_illegal(ctx); - return true; + return false; } =20 #ifdef TARGET_RISCV32 /* Ensure, that shamt[5] is zero for RV32 */ if (a->shamt >=3D 32) { - gen_exception_illegal(ctx); - return true; + return false; } #endif =20 diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_tr= ans/trans_rvd.inc.c index 076d2147c3..8593b20233 100644 --- a/target/riscv/insn_trans/trans_rvd.inc.c +++ b/target/riscv/insn_trans/trans_rvd.inc.c @@ -253,7 +253,7 @@ static bool trans_fclass_d(DisasContext *ctx, arg_fclas= s_d *a, uint32_t insn) gen_set_gpr(a->rd, t0); tcg_temp_free(t0); #else - gen_exception_illegal(ctx); + return false; #endif return true; } @@ -323,7 +323,7 @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_= l_d *a, uint32_t insn) gen_set_gpr(a->rd, t0); tcg_temp_free(t0); #else - gen_exception_illegal(ctx); + return false; #endif return true; } @@ -339,7 +339,7 @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt= _lu_d *a, uint32_t insn) gen_set_gpr(a->rd, t0); tcg_temp_free(t0); #else - gen_exception_illegal(ctx); + return false; #endif return true; } @@ -351,7 +351,7 @@ static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_= d *a, uint32_t insn) =20 gen_set_gpr(a->rd, cpu_fpr[a->rs1]); #else - gen_exception_illegal(ctx); + return false; #endif return true; } @@ -368,7 +368,7 @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_= d_l *a, uint32_t insn) gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0); tcg_temp_free(t0); #else - gen_exception_illegal(ctx); + return false; #endif return true; } @@ -385,7 +385,7 @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt= _d_lu *a, uint32_t insn) gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0); tcg_temp_free(t0); #else - gen_exception_illegal(ctx); + return false; #endif return true; } @@ -401,7 +401,7 @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_= x *a, uint32_t insn) tcg_gen_mov_tl(cpu_fpr[a->rd], t0); tcg_temp_free(t0); #else - gen_exception_illegal(ctx); + return false; #endif return true; } diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_tr= ans/trans_rvf.inc.c index d33a0113c2..6b9a6eea95 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.inc.c @@ -20,7 +20,7 @@ =20 #define REQUIRE_FPU \ if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) \ - gen_exception_illegal(ctx) + return false; =20 static bool trans_flw(DisasContext *ctx, arg_flw *a, uint32_t insn) { @@ -336,7 +336,7 @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_= l_s *a, uint32_t insn) gen_set_gpr(a->rd, t0); tcg_temp_free(t0); #else - gen_exception_illegal(ctx); + return false; #endif =20 return true; @@ -353,7 +353,7 @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt= _lu_s *a, uint32_t insn) gen_set_gpr(a->rd, t0); tcg_temp_free(t0); #else - gen_exception_illegal(ctx); + return false; #endif =20 return true; @@ -372,7 +372,7 @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_= s_l *a, uint32_t insn) =20 tcg_temp_free(t0); #else - gen_exception_illegal(ctx); + return false; #endif return true; } @@ -390,7 +390,7 @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt= _s_lu *a, uint32_t insn) =20 tcg_temp_free(t0); #else - gen_exception_illegal(ctx); + return false; #endif return true; } diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index b84a2e018b..a0c15a256b 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -286,8 +286,7 @@ static bool trans_slli(DisasContext *ctx, arg_slli *a, = uint32_t insn) gen_get_gpr(t, a->rs1); =20 if (a->shamt >=3D TARGET_LONG_BITS) { - gen_exception_illegal(ctx); - return true; + return false; } tcg_gen_shli_tl(t, t, a->shamt); =20 @@ -447,8 +446,7 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a= , uint32_t insn) static bool trans_addw(DisasContext *ctx, arg_addw *a, uint32_t insn) { #if !defined(TARGET_RISCV64) - gen_exception_illegal(ctx); - return true; + return false; #endif return trans_arith(ctx, a, &tcg_gen_add_tl); } @@ -456,8 +454,7 @@ static bool trans_addw(DisasContext *ctx, arg_addw *a, = uint32_t insn) static bool trans_subw(DisasContext *ctx, arg_subw *a, uint32_t insn) { #if !defined(TARGET_RISCV64) - gen_exception_illegal(ctx); - return true; + return false; #endif return trans_arith(ctx, a, &tcg_gen_sub_tl); } @@ -465,8 +462,7 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a, = uint32_t insn) static bool trans_sllw(DisasContext *ctx, arg_sllw *a, uint32_t insn) { #if !defined(TARGET_RISCV64) - gen_exception_illegal(ctx); - return true; + return false; #endif TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); @@ -486,8 +482,7 @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a, = uint32_t insn) static bool trans_srlw(DisasContext *ctx, arg_srlw *a, uint32_t insn) { #if !defined(TARGET_RISCV64) - gen_exception_illegal(ctx); - return true; + return false; #endif TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); @@ -509,8 +504,7 @@ static bool trans_srlw(DisasContext *ctx, arg_srlw *a, = uint32_t insn) static bool trans_sraw(DisasContext *ctx, arg_sraw *a, uint32_t insn) { #if !defined(TARGET_RISCV64) - gen_exception_illegal(ctx); - return true; + return false; #endif TCGv source1 =3D tcg_temp_new(); TCGv source2 =3D tcg_temp_new(); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 8ef943f6c8..298f2e4aa5 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -427,6 +427,7 @@ static void decode_opc(CPURISCVState *env, DisasContext= *ctx) } else { ctx->pc_succ_insn =3D ctx->base.pc_next + 4; if (!decode_insn32(ctx, ctx->opcode)) { + gen_exception_illegal(ctx); } } } --=20 2.19.1