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X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH 01/28] targer/riscv: Activate decodetree and implemnt LUI & AUIPC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" for now only LUI & AUIPC are decoded and translated. If decodetree fails, we falls back to the old decoder. Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt Reviewed-by: Richard Henderson --- target/riscv/Makefile.objs | 10 +++++++ target/riscv/insn32.decode | 30 +++++++++++++++++++++ target/riscv/insn_trans/trans_rvi.inc.c | 35 +++++++++++++++++++++++++ target/riscv/translate.c | 24 ++++++++++++----- 4 files changed, 92 insertions(+), 7 deletions(-) create mode 100644 target/riscv/insn32.decode create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index abd0a7cde3..ea02f9b9ef 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -1 +1,11 @@ obj-y +=3D translate.o op_helper.o helper.o cpu.o fpu_helper.o gdbstub.o p= mp.o + +DECODETREE =3D $(SRC_PATH)/scripts/decodetree.py + +target/riscv/decode_insn32.inc.c: \ + $(SRC_PATH)/target/riscv/insn32.decode $(DECODETREE) + $(call quiet-command, \ + $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $<, \ + "GEN", $(TARGET_DIR)$@) + +target/riscv/translate.o: target/riscv/decode_insn32.inc.c diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode new file mode 100644 index 0000000000..44d4e922b6 --- /dev/null +++ b/target/riscv/insn32.decode @@ -0,0 +1,30 @@ +# +# RISC-V translation routines for the RVXI Base Integer Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along = with +# this program. If not, see . + +# Fields: +%rd 7:5 + +# immediates: +%imm_u 12:s20 !function=3Dex_shift_12 + +# Formats 32: +@u .................... ..... ....... imm=3D%imm_u = %rd + +# *** RV32I Base Instruction Set *** +lui .................... ..... 0110111 @u +auipc .................... ..... 0010111 @u diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c new file mode 100644 index 0000000000..aee0d1637d --- /dev/null +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -0,0 +1,35 @@ +/* + * RISC-V translation routines for the RVXI Base Integer Instruction Set. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de + * Bastian Koppelmann, kbastian@mail.uni-paderborn.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +static bool trans_lui(DisasContext *ctx, arg_lui *a, uint32_t insn) +{ + if (a->rd !=3D 0) { + tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm); + } + return true; +} + +static bool trans_auipc(DisasContext *ctx, arg_auipc *a, uint32_t insn) +{ + if (a->rd !=3D 0) { + tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next); + } + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 18d7b6d147..2ee886c6b7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1666,6 +1666,19 @@ static void decode_RV32_64C(CPURISCVState *env, Disa= sContext *ctx) } } =20 +#define EX_SH(amount) \ + static int64_t ex_shift_##amount(int imm) \ + { \ + return imm << amount; \ + } +EX_SH(12) + +bool decode_insn32(DisasContext *ctx, uint32_t insn); +/* Include the auto-generated decoder for 32 bit insn */ +#include "decode_insn32.inc.c" +/* Include insn module translation function */ +#include "insn_trans/trans_rvi.inc.c" + static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) { int rs1; @@ -1686,12 +1699,6 @@ static void decode_RV32_64G(CPURISCVState *env, Disa= sContext *ctx) imm =3D GET_IMM(ctx->opcode); =20 switch (op) { - case OPC_RISC_LUI: - if (rd =3D=3D 0) { - break; /* NOP */ - } - tcg_gen_movi_tl(cpu_gpr[rd], sextract64(ctx->opcode, 12, 20) << 12= ); - break; case OPC_RISC_AUIPC: if (rd =3D=3D 0) { break; /* NOP */ @@ -1801,7 +1808,10 @@ static void decode_opc(CPURISCVState *env, DisasCont= ext *ctx) } } else { ctx->pc_succ_insn =3D ctx->base.pc_next + 4; - decode_RV32_64G(env, ctx); + if (!decode_insn32(ctx, ctx->opcode)) { + /* fallback to old decoder */ + decode_RV32_64G(env, ctx); + } } } =20 --=20 2.19.1