From nobody Thu Nov 6 06:16:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539355928714488.4187756484804; Fri, 12 Oct 2018 07:52:08 -0700 (PDT) Received: from localhost ([::1]:41137 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAynP-0006ax-EK for importer@patchew.org; Fri, 12 Oct 2018 10:52:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55448) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAyeV-000885-9Z for qemu-devel@nongnu.org; Fri, 12 Oct 2018 10:42:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAyeU-00037N-BZ for qemu-devel@nongnu.org; Fri, 12 Oct 2018 10:42:55 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51808) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gAyeR-0002yA-Tp; Fri, 12 Oct 2018 10:42:52 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gAyeM-0000PB-HJ; Fri, 12 Oct 2018 15:42:46 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 15:42:31 +0100 Message-Id: <20181012144235.19646-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181012144235.19646-1-peter.maydell@linaro.org> References: <20181012144235.19646-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 06/10] target/arm: Implement HCR.VI and VF X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The HCR_EL2 VI and VF bits are supposed to track whether there is a pending virtual IRQ or virtual FIQ. For QEMU we store the pending VIRQ/VFIQ status in cs->interrupt_request, so this means: * if the register is read we must get these bit values from cs->interrupt_request * if the register is written then we must write the bit values back into cs->interrupt_request Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 47 +++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 43 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 65e431e03b3..78d05fe1e57 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3928,6 +3928,7 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = =3D { static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) { ARMCPU *cpu =3D arm_env_get_cpu(env); + CPUState *cs =3D ENV_GET_CPU(env); uint64_t valid_mask =3D HCR_MASK; =20 if (arm_feature(env, ARM_FEATURE_EL3)) { @@ -3946,6 +3947,28 @@ static void hcr_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) /* Clear RES0 bits. */ value &=3D valid_mask; =20 + /* + * VI and VF are kept in cs->interrupt_request. Modifying that + * requires that we have the iothread lock, which is done by + * marking the reginfo structs as ARM_CP_IO. + * Note that if a write to HCR pends a VIRQ or VFIQ it is never + * possible for it to be taken immediately, because VIRQ and + * VFIQ are masked unless running at EL0 or EL1, and HCR + * can only be written at EL2. + */ + g_assert(qemu_mutex_iothread_locked()); + if (value & HCR_VI) { + cs->interrupt_request |=3D CPU_INTERRUPT_VIRQ; + } else { + cs->interrupt_request &=3D ~CPU_INTERRUPT_VIRQ; + } + if (value & HCR_VF) { + cs->interrupt_request |=3D CPU_INTERRUPT_VFIQ; + } else { + cs->interrupt_request &=3D ~CPU_INTERRUPT_VFIQ; + } + value &=3D ~(HCR_VI | HCR_VF); + /* These bits change the MMU setup: * HCR_VM enables stage 2 translation * HCR_PTW forbids certain page-table setups @@ -3973,16 +3996,32 @@ static void hcr_writelow(CPUARMState *env, const AR= MCPRegInfo *ri, hcr_write(env, NULL, value); } =20 +static uint64_t hcr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* The VI and VF bits live in cs->interrupt_request */ + uint64_t ret =3D env->cp15.hcr_el2 & ~(HCR_VI | HCR_VF); + CPUState *cs =3D ENV_GET_CPU(env); + + if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { + ret |=3D HCR_VI; + } + if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { + ret |=3D HCR_VF; + } + return ret; +} + static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), - .writefn =3D hcr_write }, + .writefn =3D hcr_write, .readfn =3D hcr_read }, { .name =3D "HCR", .state =3D ARM_CP_STATE_AA32, - .type =3D ARM_CP_ALIAS, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), - .writefn =3D hcr_writelow }, + .writefn =3D hcr_writelow, .readfn =3D hcr_read }, { .name =3D "ELR_EL2", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, @@ -4219,7 +4258,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { =20 static const ARMCPRegInfo el2_v8_cp_reginfo[] =3D { { .name =3D "HCR2", .state =3D ARM_CP_STATE_AA32, - .type =3D ARM_CP_ALIAS, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, .access =3D PL2_RW, .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.hcr_el2), --=20 2.19.0