From nobody Thu Nov 6 06:16:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539355509265556.9869932548523; Fri, 12 Oct 2018 07:45:09 -0700 (PDT) Received: from localhost ([::1]:41081 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAyge-000176-48 for importer@patchew.org; Fri, 12 Oct 2018 10:45:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55315) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAyeN-0007zD-Fl for qemu-devel@nongnu.org; Fri, 12 Oct 2018 10:42:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAyeM-0002w0-Mm for qemu-devel@nongnu.org; Fri, 12 Oct 2018 10:42:47 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51790) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gAyeK-0002ix-9S; Fri, 12 Oct 2018 10:42:44 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gAyeI-0000Oa-Di; Fri, 12 Oct 2018 15:42:42 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 15:42:29 +0100 Message-Id: <20181012144235.19646-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181012144235.19646-1-peter.maydell@linaro.org> References: <20181012144235.19646-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 04/10] target/arm: Implement HCR.DC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The HCR.DC virtualization configuration register bit has the following effects: * SCTLR.M behaves as if it is 0 for all purposes except direct reads of the bit * HCR.VM behaves as if it is 1 for all purposes except direct reads of the bit * the memory type produced by the first stage of the EL1&EL0 translation regime is Normal Non-Shareable, Inner Write-Back Read-Allocate Write-Allocate, Outer Write-Back Read-Allocate Write-Allocate. Implement this behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index cbec6844a44..84b40031b6f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2300,13 +2300,15 @@ static uint64_t do_ats_write(CPUARMState *env, uint= 64_t value, * * The Non-secure TTBCR.EAE bit is set to 1 * * The implementation includes EL2, and the value of HCR.VM is 1 * + * (Note that HCR.DC makes HCR.VM behave as if it is 1.) + * * ATS1Hx always uses the 64bit format (not supported yet). */ format64 =3D arm_s1_regime_using_lpae_format(env, mmu_idx); =20 if (arm_feature(env, ARM_FEATURE_EL2)) { if (mmu_idx =3D=3D ARMMMUIdx_S12NSE0 || mmu_idx =3D=3D ARMMMUI= dx_S12NSE1) { - format64 |=3D env->cp15.hcr_el2 & HCR_VM; + format64 |=3D env->cp15.hcr_el2 & (HCR_VM | HCR_DC); } else { format64 |=3D arm_current_el(env) =3D=3D 2; } @@ -8711,7 +8713,8 @@ static inline bool regime_translation_disabled(CPUARM= State *env, } =20 if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { - return (env->cp15.hcr_el2 & HCR_VM) =3D=3D 0; + /* HCR.DC means HCR.VM behaves as 1 */ + return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) =3D=3D 0; } =20 if (env->cp15.hcr_el2 & HCR_TGE) { @@ -8721,6 +8724,12 @@ static inline bool regime_translation_disabled(CPUAR= MState *env, } } =20 + if ((env->cp15.hcr_el2 & HCR_DC) && + (mmu_idx =3D=3D ARMMMUIdx_S1NSE0 || mmu_idx =3D=3D ARMMMUIdx_S1NSE= 1)) { + /* HCR.DC means SCTLR_EL1.M behaves as 0 */ + return true; + } + return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; } =20 @@ -10701,6 +10710,16 @@ static bool get_phys_addr(CPUARMState *env, target= _ulong address, =20 /* Combine the S1 and S2 cache attributes, if needed */ if (!ret && cacheattrs !=3D NULL) { + if (env->cp15.hcr_el2 & HCR_DC) { + /* + * HCR.DC forces the first stage attributes to + * Normal Non-Shareable, + * Inner Write-Back Read-Allocate Write-Allocate, + * Outer Write-Back Read-Allocate Write-Allocate. + */ + cacheattrs->attrs =3D 0xff; + cacheattrs->shareability =3D 0; + } *cacheattrs =3D combine_cacheattrs(*cacheattrs, cacheattrs= 2); } =20 --=20 2.19.0