From nobody Thu Nov 6 06:17:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539356063184505.0555588164757; Fri, 12 Oct 2018 07:54:23 -0700 (PDT) Received: from localhost ([::1]:41148 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAypV-0008Hd-Hq for importer@patchew.org; Fri, 12 Oct 2018 10:54:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55452) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAyeV-00088X-NO for qemu-devel@nongnu.org; Fri, 12 Oct 2018 10:42:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAyeU-00037o-N5 for qemu-devel@nongnu.org; Fri, 12 Oct 2018 10:42:55 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51816) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gAyeS-00031c-8C; Fri, 12 Oct 2018 10:42:52 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1gAyeQ-0000QD-BJ; Fri, 12 Oct 2018 15:42:50 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 12 Oct 2018 15:42:35 +0100 Message-Id: <20181012144235.19646-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181012144235.19646-1-peter.maydell@linaro.org> References: <20181012144235.19646-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 10/10] target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" For traps of FP/SIMD instructions to AArch32 Hyp mode, the syndrome provided in HSR has more information than is reported to AArch64. Specifically, there are extra fields TA and coproc which indicate whether the trapped instruction was FP or SIMD. Add this extra information to the syndromes we construct, and mask it out when taking the exception to AArch64. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/internals.h | 14 +++++++++++++- target/arm/helper.c | 9 +++++++++ target/arm/translate.c | 8 ++++---- 3 files changed, 26 insertions(+), 5 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index cd8bc1ec3d4..960dfb3c06a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -288,6 +288,9 @@ static inline uint32_t syn_get_ec(uint32_t syn) * few cases the value in HSR for exceptions taken to AArch32 Hyp * mode differs slightly, and we fix this up when populating HSR in * arm_cpu_do_interrupt_aarch32_hyp(). + * The exception is FP/SIMD access traps -- these report extra information + * when taking an exception to AArch32. For those we include the extra cop= roc + * and TA fields, and mask them out when taking the exception to AArch64. */ static inline uint32_t syn_uncategorized(void) { @@ -387,9 +390,18 @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int c= ond, int opc1, int crm, =20 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) { + /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA =3D=3D 0 coproc =3D= =3D 0xa */ return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) | (is_16bit ? 0 : ARM_EL_IL) - | (cv << 24) | (cond << 20); + | (cv << 24) | (cond << 20) | 0xa; +} + +static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bi= t) +{ + /* AArch32 SIMD trap: TA =3D=3D 1 coproc =3D=3D 0 */ + return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) + | (is_16bit ? 0 : ARM_EL_IL) + | (cv << 24) | (cond << 20) | (1 << 5); } =20 static inline uint32_t syn_sve_access_trap(void) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0b659171b07..43afdd082e1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8540,6 +8540,15 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *c= s) case EXCP_HVC: case EXCP_HYP_TRAP: case EXCP_SMC: + if (syn_get_ec(env->exception.syndrome) =3D=3D EC_ADVSIMDFPACCESST= RAP) { + /* + * QEMU internal FP/SIMD syndromes from AArch32 include the + * TA and coproc fields which are only exposed if the exception + * is taken to AArch32 Hyp mode. Mask them out to get a valid + * AArch64 format syndrome. + */ + env->exception.syndrome &=3D ~MAKE_64BIT_MASK(0, 20); + } env->cp15.esr_el[new_el] =3D env->exception.syndrome; break; case EXCP_IRQ: diff --git a/target/arm/translate.c b/target/arm/translate.c index 7c7d920e331..d71597796f5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4948,7 +4948,7 @@ static int disas_neon_ls_insn(DisasContext *s, uint32= _t insn) */ if (s->fp_excp_el) { gen_exception_insn(s, 4, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), s->fp_excp_e= l); + syn_simd_access_trap(1, 0xe, false), s->fp_excp= _el); return 0; } =20 @@ -5727,7 +5727,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) */ if (s->fp_excp_el) { gen_exception_insn(s, 4, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), s->fp_excp_e= l); + syn_simd_access_trap(1, 0xe, false), s->fp_excp= _el); return 0; } =20 @@ -7840,7 +7840,7 @@ static int disas_neon_insn_3same_ext(DisasContext *s,= uint32_t insn) =20 if (s->fp_excp_el) { gen_exception_insn(s, 4, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), s->fp_excp_e= l); + syn_simd_access_trap(1, 0xe, false), s->fp_excp= _el); return 0; } if (!s->vfp_enabled) { @@ -7926,7 +7926,7 @@ static int disas_neon_insn_2reg_scalar_ext(DisasConte= xt *s, uint32_t insn) =20 if (s->fp_excp_el) { gen_exception_insn(s, 4, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), s->fp_excp_e= l); + syn_simd_access_trap(1, 0xe, false), s->fp_excp= _el); return 0; } if (!s->vfp_enabled) { --=20 2.19.0