From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153930181382827.332464885809713; Thu, 11 Oct 2018 16:50:13 -0700 (PDT) Received: from localhost ([::1]:37594 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAkia-0007C0-As for importer@patchew.org; Thu, 11 Oct 2018 19:50:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54261) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAkar-0001oG-C1 for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAkao-0002HV-Cg for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:13 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:40020) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAkam-0001zP-7w for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:10 -0400 Received: by mail-pl1-x634.google.com with SMTP id 1-v6so4970059plv.7 for ; Thu, 11 Oct 2018 16:42:05 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id o12-v6sm12258302pgv.7.2018.10.11.16.42.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 16:42:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8hlA60Zgri2M+snlT0Rvz4vYsbywQnqNbPP7KQ9tpCk=; b=UvgKlzMTJHV1qQ5MfsVYgCJtJQYp7N+OTZJs1OP9TMNfVXfwkhujTUzOd+5yZf1JCG qOOyMXU6WRgt7L7JT7O5SlLsttJ/tgSfoEMSfMios4/qQvklmpUPecGdMFHoBgjOY7TS izf93Ia8yJEUOtTZy6f5L8M9dke3ELFWNZu1k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8hlA60Zgri2M+snlT0Rvz4vYsbywQnqNbPP7KQ9tpCk=; b=KVMs59hMV7Jn11gk5anLals4yLg4QQf1cbDCi2xkAPQbAQ1SHvneV26RlxbRgLWPQ+ EaPIFM6GsmXk8GkYChVWdGrD1JQKqgH+Ra0MYaL5AYo4WtcVXuOUHu1jP5R0b2j9zGFP UozujxBF8z+FoCc91QRzO1L6LgQ55KNo/HYVo3w1yNDWCkI9ved6DKi/RjOlDX69ZE9X XIwafIAdwIgorVXYcfEl/F7VvjXdtsyRMHK4x5KniRMaqTfIRTIefU6pxdMD57lVjlkI xl7JWVV/o3NDAH3vamjH/XICUwzP/vEF7vssvVef9sTO2nvwUjW9a6vdB6RATwY3OzUT szuA== X-Gm-Message-State: ABuFfohamraHpBZbkA0HKThUME7xianoFVPbLBzft03rd017CsPb1lax ylMW2V3zbEM91mVA+AeGb+DpoKxiOBU= X-Google-Smtp-Source: ACcGV61wV8G1A2s3pWXBgEe2Uhu7AE2HfbJ6xOTsLqd5j3VHoZXwhYjOTTkZSeqB9Lap5xI5zto4Aw== X-Received: by 2002:a17:902:101:: with SMTP id 1-v6mr3509394plb.15.1539301323433; Thu, 11 Oct 2018 16:42:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 16:41:53 -0700 Message-Id: <20181011234159.11496-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011234159.11496-1-richard.henderson@linaro.org> References: <20181011234159.11496-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::634 Subject: [Qemu-devel] [PATCH 1/7] target/ppc: Split up float_invalid_op_excp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The always_inline trick only works if the function is always called from the outer-most helper. But it isn't, so pass in the outer-most return address. There's no need for a switch statement whose argument is always a constant. Unravel the switch and goto via more helpers. Signed-off-by: Richard Henderson --- target/ppc/fpu_helper.c | 344 +++++++++++++++++++++------------------- 1 file changed, 181 insertions(+), 163 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index b9bb1b856e..6ec5227dd5 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -170,96 +170,120 @@ COMPUTE_FPRF(float64) COMPUTE_FPRF(float128) =20 /* Floating-point invalid operations exception */ -static inline __attribute__((__always_inline__)) -uint64_t float_invalid_op_excp(CPUPPCState *env, int op, int set_fpcc) +static void finish_invalid_op_excp(CPUPPCState *env, int op, uintptr_t ret= addr) { - CPUState *cs =3D CPU(ppc_env_get_cpu(env)); - uint64_t ret =3D 0; - int ve; + /* Update the floating-point invalid operation summary */ + env->fpscr |=3D 1 << FPSCR_VX; + /* Update the floating-point exception summary */ + env->fpscr |=3D FP_FX; + if (fpscr_ve !=3D 0) { + /* Update the floating-point enabled exception summary */ + env->fpscr |=3D 1 << FPSCR_FEX; + if (fp_exceptions_enabled(env)) { + raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_FP | op, retaddr); + } + } +} =20 - ve =3D fpscr_ve; - switch (op) { - case POWERPC_EXCP_FP_VXSNAN: - env->fpscr |=3D 1 << FPSCR_VXSNAN; - break; - case POWERPC_EXCP_FP_VXSOFT: - env->fpscr |=3D 1 << FPSCR_VXSOFT; - break; - case POWERPC_EXCP_FP_VXISI: - /* Magnitude subtraction of infinities */ - env->fpscr |=3D 1 << FPSCR_VXISI; - goto update_arith; - case POWERPC_EXCP_FP_VXIDI: - /* Division of infinity by infinity */ - env->fpscr |=3D 1 << FPSCR_VXIDI; - goto update_arith; - case POWERPC_EXCP_FP_VXZDZ: - /* Division of zero by zero */ - env->fpscr |=3D 1 << FPSCR_VXZDZ; - goto update_arith; - case POWERPC_EXCP_FP_VXIMZ: - /* Multiplication of zero by infinity */ - env->fpscr |=3D 1 << FPSCR_VXIMZ; - goto update_arith; - case POWERPC_EXCP_FP_VXVC: - /* Ordered comparison of NaN */ - env->fpscr |=3D 1 << FPSCR_VXVC; +static void finish_invalid_op_arith(CPUPPCState *env, int op, + bool set_fpcc, uintptr_t retaddr) +{ + env->fpscr &=3D ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); + if (fpscr_ve =3D=3D 0) { if (set_fpcc) { env->fpscr &=3D ~(0xF << FPSCR_FPCC); env->fpscr |=3D 0x11 << FPSCR_FPCC; } - /* We must update the target FPR before raising the exception */ - if (ve !=3D 0) { - cs->exception_index =3D POWERPC_EXCP_PROGRAM; - env->error_code =3D POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC; - /* Update the floating-point enabled exception summary */ - env->fpscr |=3D 1 << FPSCR_FEX; - /* Exception is differed */ - ve =3D 0; - } - break; - case POWERPC_EXCP_FP_VXSQRT: - /* Square root of a negative number */ - env->fpscr |=3D 1 << FPSCR_VXSQRT; - update_arith: - env->fpscr &=3D ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); - if (ve =3D=3D 0) { - /* Set the result to quiet NaN */ - ret =3D 0x7FF8000000000000ULL; - if (set_fpcc) { - env->fpscr &=3D ~(0xF << FPSCR_FPCC); - env->fpscr |=3D 0x11 << FPSCR_FPCC; - } - } - break; - case POWERPC_EXCP_FP_VXCVI: - /* Invalid conversion */ - env->fpscr |=3D 1 << FPSCR_VXCVI; - env->fpscr &=3D ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); - if (ve =3D=3D 0) { - /* Set the result to quiet NaN */ - ret =3D 0x7FF8000000000000ULL; - if (set_fpcc) { - env->fpscr &=3D ~(0xF << FPSCR_FPCC); - env->fpscr |=3D 0x11 << FPSCR_FPCC; - } - } - break; + } + finish_invalid_op_excp(env, op, retaddr); +} + +/* Signalling NaN */ +static void float_invalid_op_vxsnan(CPUPPCState *env, uintptr_t retaddr) +{ + env->fpscr |=3D 1 << FPSCR_VXSNAN; + finish_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, retaddr); +} + +/* Magnitude subtraction of infinities */ +static void float_invalid_op_vxisi(CPUPPCState *env, bool set_fpcc, + uintptr_t retaddr) +{ + env->fpscr |=3D 1 << FPSCR_VXISI; + finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXISI, set_fpcc, retaddr); +} + +/* Division of infinity by infinity */ +static void float_invalid_op_vxidi(CPUPPCState *env, bool set_fpcc, + uintptr_t retaddr) +{ + env->fpscr |=3D 1 << FPSCR_VXIDI; + finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXIDI, set_fpcc, retaddr); +} + +/* Division of zero by zero */ +static void float_invalid_op_vxzdz(CPUPPCState *env, bool set_fpcc, + uintptr_t retaddr) +{ + env->fpscr |=3D 1 << FPSCR_VXZDZ; + finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXZDZ, set_fpcc, retaddr); +} + +/* Multiplication of zero by infinity */ +static void float_invalid_op_vximz(CPUPPCState *env, bool set_fpcc, + uintptr_t retaddr) +{ + env->fpscr |=3D 1 << FPSCR_VXIMZ; + finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXIMZ, set_fpcc, retaddr); +} + +/* Square root of a negative number */ +static void float_invalid_op_vxsqrt(CPUPPCState *env, bool set_fpcc, + uintptr_t retaddr) +{ + env->fpscr |=3D 1 << FPSCR_VXSQRT; + finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXSQRT, set_fpcc, retaddr= ); +} + +/* Ordered comparison of NaN */ +static void float_invalid_op_vxvc(CPUPPCState *env, bool set_fpcc, + uintptr_t retaddr) +{ + env->fpscr |=3D 1 << FPSCR_VXVC; + if (set_fpcc) { + env->fpscr &=3D ~(0xF << FPSCR_FPCC); + env->fpscr |=3D 0x11 << FPSCR_FPCC; } /* Update the floating-point invalid operation summary */ env->fpscr |=3D 1 << FPSCR_VX; /* Update the floating-point exception summary */ env->fpscr |=3D FP_FX; - if (ve !=3D 0) { + /* We must update the target FPR before raising the exception */ + if (fpscr_ve !=3D 0) { + CPUState *cs =3D CPU(ppc_env_get_cpu(env)); + + cs->exception_index =3D POWERPC_EXCP_PROGRAM; + env->error_code =3D POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC; /* Update the floating-point enabled exception summary */ env->fpscr |=3D 1 << FPSCR_FEX; - if (fp_exceptions_enabled(env)) { - /* GETPC() works here because this is inline */ - raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, - POWERPC_EXCP_FP | op, GETPC()); + /* Exception is differed */ + } +} + +/* Invalid conversion */ +static void float_invalid_op_vxcvi(CPUPPCState *env, bool set_fpcc, + uintptr_t retaddr) +{ + env->fpscr |=3D 1 << FPSCR_VXCVI; + env->fpscr &=3D ~((1 << FPSCR_FR) | (1 << FPSCR_FI)); + if (fpscr_ve =3D=3D 0) { + if (set_fpcc) { + env->fpscr &=3D ~(0xF << FPSCR_FPCC); + env->fpscr |=3D 0x11 << FPSCR_FPCC; } } - return ret; + finish_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, retaddr); } =20 static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t radd= r) @@ -632,11 +656,11 @@ float64 helper_fadd(CPUPPCState *env, float64 arg1, f= loat64 arg2) if (unlikely(status & float_flag_invalid)) { if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) { /* Magnitude subtraction of infinities */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); + float_invalid_op_vxisi(env, 1, GETPC()); } else if (float64_is_signaling_nan(arg1, &env->fp_status) || float64_is_signaling_nan(arg2, &env->fp_status)) { /* sNaN addition */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } =20 @@ -652,11 +676,11 @@ float64 helper_fsub(CPUPPCState *env, float64 arg1, f= loat64 arg2) if (unlikely(status & float_flag_invalid)) { if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) { /* Magnitude subtraction of infinities */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); + float_invalid_op_vxisi(env, 1, GETPC()); } else if (float64_is_signaling_nan(arg1, &env->fp_status) || float64_is_signaling_nan(arg2, &env->fp_status)) { /* sNaN addition */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } =20 @@ -673,11 +697,11 @@ float64 helper_fmul(CPUPPCState *env, float64 arg1, f= loat64 arg2) if ((float64_is_infinity(arg1) && float64_is_zero(arg2)) || (float64_is_zero(arg1) && float64_is_infinity(arg2))) { /* Multiplication of zero by infinity */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1); + float_invalid_op_vximz(env, 1, GETPC()); } else if (float64_is_signaling_nan(arg1, &env->fp_status) || float64_is_signaling_nan(arg2, &env->fp_status)) { /* sNaN multiplication */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } =20 @@ -695,14 +719,14 @@ float64 helper_fdiv(CPUPPCState *env, float64 arg1, f= loat64 arg2) /* Determine what kind of invalid operation was seen. */ if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) { /* Division of infinity by infinity */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, 1); + float_invalid_op_vxidi(env, 1, GETPC()); } else if (float64_is_zero(arg1) && float64_is_zero(arg2)) { /* Division of zero by zero */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, 1); + float_invalid_op_vxzdz(env, 1, GETPC()); } else if (float64_is_signaling_nan(arg1, &env->fp_status) || float64_is_signaling_nan(arg2, &env->fp_status)) { /* sNaN division */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } if (status & float_flag_divbyzero) { @@ -724,14 +748,14 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg) = \ \ if (unlikely(env->fp_status.float_exception_flags)) { \ if (float64_is_any_nan(arg)) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \ + float_invalid_op_vxcvi(env, 1, GETPC()); \ if (float64_is_signaling_nan(arg, &env->fp_status)) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ farg.ll =3D nanval; \ } else if (env->fp_status.float_exception_flags & \ float_flag_invalid) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1); \ + float_invalid_op_vxcvi(env, 1, GETPC()); \ } \ float_check_status(env); \ } \ @@ -776,7 +800,7 @@ static inline uint64_t do_fri(CPUPPCState *env, uint64_= t arg, =20 if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) { /* sNaN round */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); farg.ll =3D arg | 0x0008000000000000ULL; } else { int inexact =3D get_float_exception_flags(&env->fp_status) & @@ -817,18 +841,18 @@ uint64_t helper_frim(CPUPPCState *env, uint64_t arg) =20 #define FPU_MADDSUB_UPDATE(NAME, TP) \ static void NAME(CPUPPCState *env, TP arg1, TP arg2, TP arg3, \ - unsigned int madd_flags) \ + unsigned int madd_flags, uintptr_t retaddr) \ { \ if (TP##_is_signaling_nan(arg1, &env->fp_status) || \ TP##_is_signaling_nan(arg2, &env->fp_status) || \ TP##_is_signaling_nan(arg3, &env->fp_status)) { \ /* sNaN operation */ \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); \ + float_invalid_op_vxsnan(env, retaddr); \ } \ if ((TP##_is_infinity(arg1) && TP##_is_zero(arg2)) || \ (TP##_is_zero(arg1) && TP##_is_infinity(arg2))) { \ /* Multiplication of zero by infinity */ \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1); \ + float_invalid_op_vximz(env, 1, retaddr); \ } \ if ((TP##_is_infinity(arg1) || TP##_is_infinity(arg2)) && \ TP##_is_infinity(arg3)) { \ @@ -841,7 +865,7 @@ static void NAME(CPUPPCState *env, TP arg1, TP arg2, TP= arg3, \ cSign ^=3D 1; \ } \ if (aSign ^ bSign ^ cSign) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); \ + float_invalid_op_vxisi(env, 1, retaddr); \ } \ } \ } @@ -859,7 +883,7 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, = \ if (flags) { \ if (flags & float_flag_invalid) { \ float64_maddsub_update_excp(env, arg1, arg2, arg3, \ - madd_flags); \ + madd_flags, GETPC()); \ } \ float_check_status(env); \ } \ @@ -885,8 +909,7 @@ uint64_t helper_frsp(CPUPPCState *env, uint64_t arg) farg.ll =3D arg; =20 if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) { - /* sNaN square root */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } f32 =3D float64_to_float32(farg.d, &env->fp_status); farg.d =3D float32_to_float64(f32, &env->fp_status); @@ -904,11 +927,11 @@ float64 helper_fsqrt(CPUPPCState *env, float64 arg) if (unlikely(float64_is_any_nan(arg))) { if (unlikely(float64_is_signaling_nan(arg, &env->fp_status))) { /* sNaN square root */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } else { /* Square root of a negative nonzero number */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); + float_invalid_op_vxsqrt(env, 1, GETPC()); } } =20 @@ -926,7 +949,7 @@ float64 helper_fre(CPUPPCState *env, float64 arg) if (status & float_flag_invalid) { if (float64_is_signaling_nan(arg, &env->fp_status)) { /* sNaN reciprocal */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } if (status & float_flag_divbyzero) { @@ -949,7 +972,7 @@ uint64_t helper_fres(CPUPPCState *env, uint64_t arg) =20 if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) { /* sNaN reciprocal */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } farg.d =3D float64_div(float64_one, farg.d, &env->fp_status); f32 =3D float64_to_float32(farg.d, &env->fp_status); @@ -970,10 +993,10 @@ float64 helper_frsqrte(CPUPPCState *env, float64 arg) if (status & float_flag_invalid) { if (float64_is_signaling_nan(arg, &env->fp_status)) { /* sNaN reciprocal */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } else { /* Square root of a negative nonzero number */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); + float_invalid_op_vxsqrt(env, 1, GETPC()); } } if (status & float_flag_divbyzero) { @@ -1095,7 +1118,7 @@ void helper_fcmpu(CPUPPCState *env, uint64_t arg1, ui= nt64_t arg2, && (float64_is_signaling_nan(farg1.d, &env->fp_status) || float64_is_signaling_nan(farg2.d, &env->fp_status))))= { /* sNaN comparison */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } =20 @@ -1123,14 +1146,11 @@ void helper_fcmpo(CPUPPCState *env, uint64_t arg1, = uint64_t arg2, env->fpscr |=3D ret << FPSCR_FPRF; env->crf[crfD] =3D ret; if (unlikely(ret =3D=3D 0x01UL)) { + float_invalid_op_vxvc(env, 1, GETPC()); if (float64_is_signaling_nan(farg1.d, &env->fp_status) || float64_is_signaling_nan(farg2.d, &env->fp_status)) { /* sNaN comparison */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN | - POWERPC_EXCP_FP_VXVC, 1); - } else { - /* qNaN comparison */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 1); + float_invalid_op_vxsnan(env, GETPC()); } } } @@ -1783,10 +1803,10 @@ void helper_##name(CPUPPCState *env, uint32_t opcod= e) \ = \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { = \ if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf); = \ + float_invalid_op_vxisi(env, sfprf, GETPC()); = \ } else if (tp##_is_signaling_nan(xa.fld, &tstat) || = \ tp##_is_signaling_nan(xb.fld, &tstat)) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);= \ + float_invalid_op_vxsnan(env, GETPC()); = \ } = \ } = \ = \ @@ -1832,10 +1852,10 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t opco= de) =20 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)= ) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); + float_invalid_op_vxisi(env, 1, GETPC()); } else if (float128_is_signaling_nan(xa.f128, &tstat) || float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } =20 @@ -1872,10 +1892,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)= \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { = \ if ((tp##_is_infinity(xa.fld) && tp##_is_zero(xb.fld)) || = \ (tp##_is_infinity(xb.fld) && tp##_is_zero(xa.fld))) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, sfprf); = \ + float_invalid_op_vximz(env, sfprf, GETPC()); = \ } else if (tp##_is_signaling_nan(xa.fld, &tstat) || = \ tp##_is_signaling_nan(xb.fld, &tstat)) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);= \ + float_invalid_op_vxsnan(env, GETPC()); = \ } = \ } = \ = \ @@ -1919,10 +1939,10 @@ void helper_xsmulqp(CPUPPCState *env, uint32_t opco= de) if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { if ((float128_is_infinity(xa.f128) && float128_is_zero(xb.f128)) || (float128_is_infinity(xb.f128) && float128_is_zero(xa.f128))) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1); + float_invalid_op_vximz(env, 1, GETPC()); } else if (float128_is_signaling_nan(xa.f128, &tstat) || float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } helper_compute_fprf_float128(env, xt.f128); @@ -1957,13 +1977,12 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)= \ = \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { = \ if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, sfprf); = \ - } else if (tp##_is_zero(xa.fld) && = \ - tp##_is_zero(xb.fld)) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, sfprf); = \ + float_invalid_op_vxidi(env, sfprf, GETPC()); = \ + } else if (tp##_is_zero(xa.fld) && tp##_is_zero(xb.fld)) { = \ + float_invalid_op_vxzdz(env, sfprf, GETPC()); = \ } else if (tp##_is_signaling_nan(xa.fld, &tstat) || = \ - tp##_is_signaling_nan(xb.fld, &tstat)) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);= \ + tp##_is_signaling_nan(xb.fld, &tstat)) { = \ + float_invalid_op_vxsnan(env, GETPC()); = \ } = \ } = \ if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) = { \ @@ -2009,13 +2028,12 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t opco= de) =20 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)= ) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, 1); - } else if (float128_is_zero(xa.f128) && - float128_is_zero(xb.f128)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, 1); + float_invalid_op_vxidi(env, 1, GETPC()); + } else if (float128_is_zero(xa.f128) && float128_is_zero(xb.f128))= { + float_invalid_op_vxzdz(env, 1, GETPC()); } else if (float128_is_signaling_nan(xa.f128, &tstat) || - float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float128_is_signaling_nan(xb.f128, &tstat)) { + float_invalid_op_vxsnan(env, GETPC()); } } if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { @@ -2046,7 +2064,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ = \ for (i =3D 0; i < nels; i++) { = \ if (unlikely(tp##_is_signaling_nan(xb.fld, &env->fp_status))) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);= \ + float_invalid_op_vxsnan(env, GETPC()); = \ } = \ xt.fld =3D tp##_div(tp##_one, xb.fld, &env->fp_status); = \ = \ @@ -2093,9 +2111,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ = \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { = \ if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf);= \ + float_invalid_op_vxsqrt(env, sfprf, GETPC()); = \ } else if (tp##_is_signaling_nan(xb.fld, &tstat)) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);= \ + float_invalid_op_vxsnan(env, GETPC()); = \ } = \ } = \ = \ @@ -2143,9 +2161,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ = \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { = \ if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf);= \ + float_invalid_op_vxsqrt(env, sfprf, GETPC()); = \ } else if (tp##_is_signaling_nan(xb.fld, &tstat)) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);= \ + float_invalid_op_vxsnan(env, GETPC()); = \ } = \ } = \ = \ @@ -2329,7 +2347,8 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ env->fp_status.float_exception_flags |=3D tstat.float_exception_fl= ags; \ = \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { = \ - tp##_maddsub_update_excp(env, xa.fld, b->fld, c->fld, maddflgs= ); \ + tp##_maddsub_update_excp(env, xa.fld, b->fld, = \ + c->fld, maddflgs, GETPC()); = \ } = \ = \ if (r2sp) { = \ @@ -2407,10 +2426,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)= \ float64_is_quiet_nan(xb.VsrD(0), &env->fp_status); = \ } = \ if (vxsnan_flag) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); = \ + float_invalid_op_vxsnan(env, GETPC()); = \ } = \ if (vxvc_flag) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); = \ + float_invalid_op_vxvc(env, 0, GETPC()); = \ } = \ vex_flag =3D fpscr_ve && (vxvc_flag || vxsnan_flag); = \ = \ @@ -2522,10 +2541,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)= \ } \ } \ if (vxsnan_flag) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ if (vxvc_flag) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \ + float_invalid_op_vxvc(env, 0, GETPC()); \ } \ \ if (float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) { \ @@ -2572,10 +2591,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)= \ } \ } \ if (vxsnan_flag) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ if (vxvc_flag) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \ + float_invalid_op_vxvc(env, 0, GETPC()); \ } \ \ if (float128_lt(xa.f128, xb.f128, &env->fp_status)) { \ @@ -2617,7 +2636,7 @@ void helper_##name(CPUPPCState *env, uint32_t opcode)= \ xt.fld =3D tp##_##op(xa.fld, xb.fld, &env->fp_status); = \ if (unlikely(tp##_is_signaling_nan(xa.fld, &env->fp_status) || = \ tp##_is_signaling_nan(xb.fld, &env->fp_status))) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); = \ + float_invalid_op_vxsnan(env, GETPC()); = \ } = \ } = \ = \ @@ -2660,7 +2679,7 @@ void helper_##name(CPUPPCState *env, uint32_t opcode)= \ = \ vex_flag =3D fpscr_ve & vxsnan_flag; = \ if (vxsnan_flag) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); = \ + float_invalid_op_vxsnan(env, GETPC()); = \ } = \ if (!vex_flag) { = \ putVSR(rD(opcode) + 32, &xt, env); = \ @@ -2715,7 +2734,7 @@ void helper_##name(CPUPPCState *env, uint32_t opcode)= \ = \ vex_flag =3D fpscr_ve & vxsnan_flag; = \ if (vxsnan_flag) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); = \ + float_invalid_op_vxsnan(env, GETPC()); = \ } = \ if (!vex_flag) { = \ putVSR(rD(opcode) + 32, &xt, env); = \ @@ -2751,10 +2770,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)= \ tp##_is_any_nan(xb.fld))) { \ if (tp##_is_signaling_nan(xa.fld, &env->fp_status) || \ tp##_is_signaling_nan(xb.fld, &env->fp_status)) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ } \ if (svxvc) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \ + float_invalid_op_vxvc(env, 0, GETPC()); \ } \ xt.fld =3D 0; = \ all_true =3D 0; = \ @@ -2807,7 +2826,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ xt.tfld =3D stp##_to_##ttp(xb.sfld, &env->fp_status); \ if (unlikely(stp##_is_signaling_nan(xb.sfld, \ &env->fp_status))) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ xt.tfld =3D ttp##_snan_to_qnan(xt.tfld); \ } \ if (sfprf) { \ @@ -2846,7 +2865,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ xt.tfld =3D stp##_to_##ttp(xb.sfld, &env->fp_status); \ if (unlikely(stp##_is_signaling_nan(xb.sfld, \ &env->fp_status))) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ xt.tfld =3D ttp##_snan_to_qnan(xt.tfld); \ } \ if (sfprf) { \ @@ -2883,7 +2902,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ xt.tfld =3D stp##_to_##ttp(xb.sfld, 1, &env->fp_status); \ if (unlikely(stp##_is_signaling_nan(xb.sfld, \ &env->fp_status))) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ xt.tfld =3D ttp##_snan_to_qnan(xt.tfld); \ } \ if (sfprf) { \ @@ -2919,9 +2938,8 @@ void helper_xscvqpdp(CPUPPCState *env, uint32_t opcod= e) =20 xt.VsrD(0) =3D float128_to_float64(xb.f128, &tstat); env->fp_status.float_exception_flags |=3D tstat.float_exception_flags; - if (unlikely(float128_is_signaling_nan(xb.f128, - &tstat))) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); + if (unlikely(float128_is_signaling_nan(xb.f128, &tstat))) { + float_invalid_op_vxsnan(env, GETPC()); xt.VsrD(0) =3D float64_snan_to_qnan(xt.VsrD(0)); } helper_compute_fprf_float64(env, xt.VsrD(0)); @@ -2967,15 +2985,15 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)= \ for (i =3D 0; i < nels; i++) { = \ if (unlikely(stp##_is_any_nan(xb.sfld))) { = \ if (stp##_is_signaling_nan(xb.sfld, &env->fp_status)) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); = \ + float_invalid_op_vxsnan(env, GETPC()); = \ } = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); = \ + float_invalid_op_vxcvi(env, 0, GETPC()); = \ xt.tfld =3D rnan; = \ } else { = \ xt.tfld =3D stp##_to_##ttp##_round_to_zero(xb.sfld, = \ &env->fp_status); = \ if (env->fp_status.float_exception_flags & float_flag_invalid)= { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); = \ + float_invalid_op_vxcvi(env, 0, GETPC()); = \ } = \ } = \ } = \ @@ -3020,15 +3038,15 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)= \ = \ if (unlikely(stp##_is_any_nan(xb.sfld))) { = \ if (stp##_is_signaling_nan(xb.sfld, &env->fp_status)) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); = \ + float_invalid_op_vxsnan(env, GETPC()); = \ } = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); = \ + float_invalid_op_vxcvi(env, 0, GETPC()); = \ xt.tfld =3D rnan; = \ } else { = \ xt.tfld =3D stp##_to_##ttp##_round_to_zero(xb.sfld, = \ &env->fp_status); = \ if (env->fp_status.float_exception_flags & float_flag_invalid) { = \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0); = \ + float_invalid_op_vxcvi(env, 0, GETPC()); = \ } = \ } = \ = \ @@ -3144,7 +3162,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ for (i =3D 0; i < nels; i++) { \ if (unlikely(tp##_is_signaling_nan(xb.fld, \ &env->fp_status))) { \ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ + float_invalid_op_vxsnan(env, GETPC()); \ xt.fld =3D tp##_snan_to_qnan(xb.fld); \ } else { \ xt.fld =3D tp##_round_to_int(xb.fld, &env->fp_status); \ @@ -3373,7 +3391,7 @@ void helper_xsrqpi(CPUPPCState *env, uint32_t opcode) =20 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { if (float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); + float_invalid_op_vxsnan(env, GETPC()); xt.f128 =3D float128_snan_to_qnan(xt.f128); } } @@ -3433,7 +3451,7 @@ void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode) =20 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { if (float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); + float_invalid_op_vxsnan(env, GETPC()); xt.f128 =3D float128_snan_to_qnan(xt.f128); } } @@ -3464,12 +3482,12 @@ void helper_xssqrtqp(CPUPPCState *env, uint32_t opc= ode) =20 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { if (float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); xt.f128 =3D float128_snan_to_qnan(xb.f128); } else if (float128_is_quiet_nan(xb.f128, &tstat)) { xt.f128 =3D xb.f128; } else if (float128_is_neg(xb.f128) && !float128_is_zero(xb.f128))= { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); + float_invalid_op_vxsqrt(env, 1, GETPC()); xt.f128 =3D float128_default_nan(&env->fp_status); } } @@ -3500,10 +3518,10 @@ void helper_xssubqp(CPUPPCState *env, uint32_t opco= de) =20 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)= ) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); + float_invalid_op_vxisi(env, 1, GETPC()); } else if (float128_is_signaling_nan(xa.f128, &tstat) || float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + float_invalid_op_vxsnan(env, GETPC()); } } =20 --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539301476035305.74512031791824; Thu, 11 Oct 2018 16:44:36 -0700 (PDT) Received: from localhost ([::1]:37567 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAkd5-0003GU-T9 for importer@patchew.org; Thu, 11 Oct 2018 19:44:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54216) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAkaq-0001o9-Fj for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAkao-0002HG-Az for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:12 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:40710) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAkam-000253-9n for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:10 -0400 Received: by mail-pg1-x533.google.com with SMTP id n31-v6so4907749pgm.7 for ; Thu, 11 Oct 2018 16:42:05 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id o12-v6sm12258302pgv.7.2018.10.11.16.42.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 16:42:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yrgo0W40GzchkKDcwDXdsjMqIoSnDXdiHCdiAzubplg=; b=gByk2p084+xjzfpnHwcc7TC1AhVbzIiZULAw1ov8eciEIFFEs+Dg6sHPDqF3RMzQ+f JFQnpQvdbK9UbEKlntGU3uxOK5GkLQX5c98R20fFdM1k3LytySWiHCsgCMTwQZXvjc57 o65gOaeyBjQf6nn03jH+5ny9pt7QyVKdhVAjI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yrgo0W40GzchkKDcwDXdsjMqIoSnDXdiHCdiAzubplg=; b=tRU2dQm/wpyyDCoXNZDU0MN3/UomGVduhWAxnUvKdlwx3o1B4pgOJU7ICXZh3ZadWW 5DobmBC4Dn9Fq5VmXt22SA9magvFXFH6WXI+Px+EhgPQn6X0WC1Rp9ooMS1Cx0YfTqfr b2NC0+Yn1i3dr2c5FKq+Eq8TvJODrKPjyNxggIc7iSUkn0ah6qNuuMWzl0afbdqbFMrs Bm2HfnqYpCJw94HE0Grf+WH2c+6ud3njTlWlUSan0eISyXfkYyP6ocVuXvAgW2KqVlq4 a7tR2813/9a3Jv9ecis/hGcUvj/k0ISFhwtxZdbXZjt17pahWTC0KXErughrB6lxSX6m P7+A== X-Gm-Message-State: ABuFfogU7UNILeDz2mpeRilvMNlgzEmDgQa6yj/507YjonlaFXiAKgPO 0eheNiQFARlqLD8X1N1zzu61vhC5r70= X-Google-Smtp-Source: ACcGV63VcChFGFwTO6d9sV09MLvRVQF4r2ijefiWQx1A58WN+PKHqYbrR/EHbZJWhjCCJAwkkxQ9fQ== X-Received: by 2002:a62:76d8:: with SMTP id r207-v6mr3644191pfc.216.1539301324556; Thu, 11 Oct 2018 16:42:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 16:41:54 -0700 Message-Id: <20181011234159.11496-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011234159.11496-1-richard.henderson@linaro.org> References: <20181011234159.11496-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::533 Subject: [Qemu-devel] [PATCH 2/7] target/ppc: Remove float_check_status X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Use do_float_check_status directly, so that we don't get confused about which return address we're using. And definitely don't use helper_float_check_status. Signed-off-by: Richard Henderson --- target/ppc/fpu_helper.c | 77 +++++++++++++++++++---------------------- 1 file changed, 35 insertions(+), 42 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 6ec5227dd5..c9198f826d 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -630,13 +630,6 @@ static void do_float_check_status(CPUPPCState *env, ui= ntptr_t raddr) } } =20 -static inline __attribute__((__always_inline__)) -void float_check_status(CPUPPCState *env) -{ - /* GETPC() works here because this is inline */ - do_float_check_status(env, GETPC()); -} - void helper_float_check_status(CPUPPCState *env) { do_float_check_status(env, GETPC()); @@ -757,7 +750,7 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg) = \ float_flag_invalid) { \ float_invalid_op_vxcvi(env, 1, GETPC()); \ } \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } \ return farg.ll; \ } @@ -782,7 +775,7 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg) = \ } else { \ farg.d =3D cvtr(arg, &env->fp_status); \ } \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ return farg.ll; \ } =20 @@ -815,7 +808,7 @@ static inline uint64_t do_fri(CPUPPCState *env, uint64_= t arg, env->fp_status.float_exception_flags &=3D ~float_flag_inexact; } } - float_check_status(env); + do_float_check_status(env, GETPC()); return farg.ll; } =20 @@ -885,7 +878,7 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, = \ float64_maddsub_update_excp(env, arg1, arg2, arg3, \ madd_flags, GETPC()); \ } \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } \ return ret; \ } @@ -1819,7 +1812,7 @@ void helper_##name(CPUPPCState *env, uint32_t opcode)= \ } = \ } = \ putVSR(xT(opcode), &xt, env); = \ - float_check_status(env); = \ + do_float_check_status(env, GETPC()); = \ } =20 VSX_ADD_SUB(xsadddp, add, 1, float64, VsrD(0), 1, 0) @@ -1862,7 +1855,7 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t opcode) helper_compute_fprf_float128(env, xt.f128); =20 putVSR(rD(opcode) + 32, &xt, env); - float_check_status(env); + do_float_check_status(env, GETPC()); } =20 /* VSX_MUL - VSX floating point multiply @@ -1909,7 +1902,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ } = \ = \ putVSR(xT(opcode), &xt, env); = \ - float_check_status(env); = \ + do_float_check_status(env, GETPC()); = \ } =20 VSX_MUL(xsmuldp, 1, float64, VsrD(0), 1, 0) @@ -1948,7 +1941,7 @@ void helper_xsmulqp(CPUPPCState *env, uint32_t opcode) helper_compute_fprf_float128(env, xt.f128); =20 putVSR(rD(opcode) + 32, &xt, env); - float_check_status(env); + do_float_check_status(env, GETPC()); } =20 /* VSX_DIV - VSX floating point divide @@ -1999,7 +1992,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ } = \ = \ putVSR(xT(opcode), &xt, env); = \ - float_check_status(env); = \ + do_float_check_status(env, GETPC()); = \ } =20 VSX_DIV(xsdivdp, 1, float64, VsrD(0), 1, 0) @@ -2042,7 +2035,7 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t opcode) =20 helper_compute_fprf_float128(env, xt.f128); putVSR(rD(opcode) + 32, &xt, env); - float_check_status(env); + do_float_check_status(env, GETPC()); } =20 /* VSX_RE - VSX floating point reciprocal estimate @@ -2078,7 +2071,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ } = \ = \ putVSR(xT(opcode), &xt, env); = \ - float_check_status(env); = \ + do_float_check_status(env, GETPC()); = \ } =20 VSX_RE(xsredp, 1, float64, VsrD(0), 1, 0) @@ -2127,7 +2120,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ } = \ = \ putVSR(xT(opcode), &xt, env); = \ - float_check_status(env); = \ + do_float_check_status(env, GETPC()); = \ } =20 VSX_SQRT(xssqrtdp, 1, float64, VsrD(0), 1, 0) @@ -2177,7 +2170,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ } = \ = \ putVSR(xT(opcode), &xt, env); = \ - float_check_status(env); = \ + do_float_check_status(env, GETPC()); = \ } =20 VSX_RSQRTE(xsrsqrtedp, 1, float64, VsrD(0), 1, 0) @@ -2360,7 +2353,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ } = \ } = \ putVSR(xT(opcode), &xt_out, env); = \ - float_check_status(env); = \ + do_float_check_status(env, GETPC()); = \ } =20 VSX_MADD(xsmaddadp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 0) @@ -2443,7 +2436,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ } = \ } = \ putVSR(xT(opcode), &xt, env); = \ - helper_float_check_status(env); = \ + do_float_check_status(env, GETPC()); = \ } =20 VSX_SCALAR_CMP_DP(xscmpeqdp, eq, 1, 0) @@ -2480,7 +2473,7 @@ void helper_xscmpexpdp(CPUPPCState *env, uint32_t opc= ode) env->fpscr |=3D cc << FPSCR_FPRF; env->crf[BF(opcode)] =3D cc; =20 - helper_float_check_status(env); + do_float_check_status(env, GETPC()); } =20 void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode) @@ -2512,7 +2505,7 @@ void helper_xscmpexpqp(CPUPPCState *env, uint32_t opc= ode) env->fpscr |=3D cc << FPSCR_FPRF; env->crf[BF(opcode)] =3D cc; =20 - helper_float_check_status(env); + do_float_check_status(env, GETPC()); } =20 #define VSX_SCALAR_CMP(op, ordered) \ @@ -2559,7 +2552,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ env->fpscr |=3D cc << FPSCR_FPRF; = \ env->crf[BF(opcode)] =3D cc; = \ \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } =20 VSX_SCALAR_CMP(xscmpodp, 1) @@ -2609,7 +2602,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ env->fpscr |=3D cc << FPSCR_FPRF; \ env->crf[BF(opcode)] =3D cc; \ \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } =20 VSX_SCALAR_CMPQ(xscmpoqp, 1) @@ -2641,7 +2634,7 @@ void helper_##name(CPUPPCState *env, uint32_t opcode)= \ } = \ = \ putVSR(xT(opcode), &xt, env); = \ - float_check_status(env); = \ + do_float_check_status(env, GETPC()); = \ } =20 VSX_MAX_MIN(xsmaxdp, maxnum, 1, float64, VsrD(0)) @@ -2792,7 +2785,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ if ((opcode >> (31-21)) & 1) { \ env->crf[6] =3D (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); = \ } \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } =20 VSX_CMP(xvcmpeqdp, 2, float64, VsrD(i), eq, 0, 1) @@ -2835,7 +2828,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ } \ \ putVSR(xT(opcode), &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } =20 VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, VsrD(0), VsrW(0), 1) @@ -2874,7 +2867,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ } \ \ putVSR(rD(opcode) + 32, &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } =20 VSX_CVT_FP_TO_FP_VECTOR(xscvdpqp, 1, float64, float128, VsrD(0), f128, 1) @@ -2911,7 +2904,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ } \ \ putVSR(xT(opcode), &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } =20 VSX_CVT_FP_TO_FP_HP(xscvdphp, 1, float64, float16, VsrD(0), VsrH(3), 1) @@ -2945,7 +2938,7 @@ void helper_xscvqpdp(CPUPPCState *env, uint32_t opcod= e) helper_compute_fprf_float64(env, xt.VsrD(0)); =20 putVSR(rD(opcode) + 32, &xt, env); - float_check_status(env); + do_float_check_status(env, GETPC()); } =20 uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb) @@ -2999,7 +2992,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ } = \ = \ putVSR(xT(opcode), &xt, env); = \ - float_check_status(env); = \ + do_float_check_status(env, GETPC()); = \ } =20 VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, VsrD(0), VsrD(0), \ @@ -3051,7 +3044,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ } = \ = \ putVSR(rD(opcode) + 32, &xt, env); = \ - float_check_status(env); = \ + do_float_check_status(env, GETPC()); = \ } =20 VSX_CVT_FP_TO_INT_VECTOR(xscvqpsdz, float128, int64, f128, VsrD(0), = \ @@ -3092,7 +3085,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ } \ \ putVSR(xT(opcode), &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } =20 VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, VsrD(0), VsrD(0), 1, 0) @@ -3127,7 +3120,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ helper_compute_fprf_##ttp(env, xt.tfld); \ \ putVSR(xT(opcode) + 32, &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } =20 VSX_CVT_INT_TO_FP_VECTOR(xscvsdqp, int64, float128, VsrD(0), f128) @@ -3181,7 +3174,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ } \ \ putVSR(xT(opcode), &xt, env); \ - float_check_status(env); \ + do_float_check_status(env, GETPC()); \ } =20 VSX_ROUND(xsrdpi, 1, float64, VsrD(0), float_round_ties_away, 1) @@ -3209,7 +3202,7 @@ uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb) uint64_t xt =3D helper_frsp(env, xb); =20 helper_compute_fprf_float64(env, xt); - float_check_status(env); + do_float_check_status(env, GETPC()); return xt; } =20 @@ -3401,7 +3394,7 @@ void helper_xsrqpi(CPUPPCState *env, uint32_t opcode) } =20 helper_compute_fprf_float128(env, xt.f128); - float_check_status(env); + do_float_check_status(env, GETPC()); putVSR(rD(opcode) + 32, &xt, env); } =20 @@ -3458,7 +3451,7 @@ void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode) =20 helper_compute_fprf_float128(env, xt.f128); putVSR(rD(opcode) + 32, &xt, env); - float_check_status(env); + do_float_check_status(env, GETPC()); } =20 void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode) @@ -3494,7 +3487,7 @@ void helper_xssqrtqp(CPUPPCState *env, uint32_t opcod= e) =20 helper_compute_fprf_float128(env, xt.f128); putVSR(rD(opcode) + 32, &xt, env); - float_check_status(env); + do_float_check_status(env, GETPC()); } =20 void helper_xssubqp(CPUPPCState *env, uint32_t opcode) @@ -3527,5 +3520,5 @@ void helper_xssubqp(CPUPPCState *env, uint32_t opcode) =20 helper_compute_fprf_float128(env, xt.f128); putVSR(rD(opcode) + 32, &xt, env); - float_check_status(env); + do_float_check_status(env, GETPC()); } --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539301470917238.97751187784093; Thu, 11 Oct 2018 16:44:30 -0700 (PDT) Received: from localhost ([::1]:37566 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAkd3-0003EQ-Kc for importer@patchew.org; Thu, 11 Oct 2018 19:44:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54219) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAkaq-0001oA-G4 for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAkao-0002HA-A9 for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:12 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:32931) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAkam-0002Co-9o for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:10 -0400 Received: by mail-pg1-x530.google.com with SMTP id y18-v6so4925290pge.0 for ; Thu, 11 Oct 2018 16:42:07 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id o12-v6sm12258302pgv.7.2018.10.11.16.42.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 16:42:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aDUi/2KPKPuqwM/Oo0DDLTqdzuEHH3/tgSCRjp139f0=; b=ebejT+VNgr9ZAHVy04k3KyJkK5gn14S5d9aB/1G04lpORsvIRDvOy1YHJQlnnEhYFi xF1GNK3hhpU0E3g2HTuDXG73+werE0WklQqPv2v6yrQlX2iFaMEGSD7oduto5jbgP8Z7 VGd1MGW7pI27W13VoVm6AN6mfL4b6oM+WXimk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aDUi/2KPKPuqwM/Oo0DDLTqdzuEHH3/tgSCRjp139f0=; b=ijBFwJ28mFkLg9BZvXt5kurPkxFeq5vKJdRyHsc7Ec1ODp4aMz3jtdTIt4x/zajZX+ s9k0lkvJrdTUtV8K1HZnwP7xcfCzr1sskhQi/+QnP2YU9BxfI+J+BxF8XQRFOHR3F50h JbqjWETwHkWCPvaGxzXW8tDn1fn44xiA6LZYGT7jfqgeOqolUO5UDcjkk7VJNXpBVG6F BXeavH3CjMYqO5WD5su7DJXBTLt2SZvsZjOJVC+LmBERqrUS5SmF7QajP4Rlz0yM+/bk gKEbiVkDYEd9ijNRejwex3hhU29LZ1lPhfX87QUvLaYDboSenAV49b7L9Khqa1FmIubS yPeg== X-Gm-Message-State: ABuFfojutUCPVlbxCRe/9Ey5VOdfobH2sAXdWR/1WqkNRDHVyyg92xCO GJSGdrZVU2A1X/CsLEry0joU6LhGCLo= X-Google-Smtp-Source: ACcGV60Ku8B5rbYpHiAdP9CZrOqoC+VLhxkhc9Ae0PvIbpYPCezH62zT1pVl03Ew5Dn/bc41DI3sJQ== X-Received: by 2002:a62:f20f:: with SMTP id m15-v6mr3567359pfh.244.1539301325688; Thu, 11 Oct 2018 16:42:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 16:41:55 -0700 Message-Id: <20181011234159.11496-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011234159.11496-1-richard.henderson@linaro.org> References: <20181011234159.11496-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::530 Subject: [Qemu-devel] [PATCH 3/7] target/ppc: Introduce fp number classification X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Having a separate, logical classifiation of numbers will unify more error paths for different formats. Signed-off-by: Richard Henderson --- target/ppc/fpu_helper.c | 94 ++++++++++++++++++++++------------------- 1 file changed, 51 insertions(+), 43 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index c9198f826d..9ae55b1e93 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -114,54 +114,62 @@ static inline int ppc_float64_get_unbiased_exp(float6= 4 f) return ((f >> 52) & 0x7FF) - 1023; } =20 -#define COMPUTE_FPRF(tp) \ -void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \ +/* Classify a floating-point number. */ +enum { + is_normal =3D 1, + is_zero =3D 2, + is_denormal =3D 4, + is_inf =3D 8, + is_qnan =3D 16, + is_snan =3D 32, + is_neg =3D 64, +}; + +#define COMPUTE_CLASS(tp) \ +static int tp##_classify(tp arg) \ { \ - int isneg; \ - int fprf; \ - \ - isneg =3D tp##_is_neg(arg); \ + int ret =3D tp##_is_neg(arg) * is_neg; \ if (unlikely(tp##_is_any_nan(arg))) { \ - if (tp##_is_signaling_nan(arg, &env->fp_status)) { \ - /* Signaling NaN: flags are undefined */ \ - fprf =3D 0x00; \ - } else { \ - /* Quiet NaN */ \ - fprf =3D 0x11; \ - } \ + float_status dummy =3D { }; /* snan_bit_is_one =3D 0 */ \ + ret |=3D (tp##_is_signaling_nan(arg, &dummy) \ + ? is_snan : is_qnan); \ } else if (unlikely(tp##_is_infinity(arg))) { \ - /* +/- infinity */ \ - if (isneg) { \ - fprf =3D 0x09; \ - } else { \ - fprf =3D 0x05; \ - } \ + ret |=3D is_inf; \ + } else if (tp##_is_zero(arg)) { \ + ret |=3D is_zero; \ + } else if (tp##_is_zero_or_denormal(arg)) { \ + ret |=3D is_denormal; \ } else { \ - if (tp##_is_zero(arg)) { \ - /* +/- zero */ \ - if (isneg) { \ - fprf =3D 0x12; \ - } else { \ - fprf =3D 0x02; \ - } \ - } else { \ - if (tp##_is_zero_or_denormal(arg)) { \ - /* Denormalized numbers */ \ - fprf =3D 0x10; \ - } else { \ - /* Normalized numbers */ \ - fprf =3D 0x00; \ - } \ - if (isneg) { \ - fprf |=3D 0x08; \ - } else { \ - fprf |=3D 0x04; \ - } \ - } \ + ret |=3D is_normal; \ } \ - /* We update FPSCR_FPRF */ \ - env->fpscr &=3D ~(0x1F << FPSCR_FPRF); \ - env->fpscr |=3D fprf << FPSCR_FPRF; \ + return ret; \ +} + +COMPUTE_CLASS(float16) +COMPUTE_CLASS(float32) +COMPUTE_CLASS(float64) +COMPUTE_CLASS(float128) + +static void set_fprf_from_class(CPUPPCState *env, int class) +{ + static const uint8_t fprf[6][2] =3D { + { 0x04, 0x08 }, /* normalized */ + { 0x02, 0x12 }, /* zero */ + { 0x14, 0x18 }, /* denormalized */ + { 0x05, 0x09 }, /* infinity */ + { 0x11, 0x11 }, /* qnan */ + { 0x00, 0x00 }, /* snan -- flags are undefined */ + }; + bool isneg =3D class & is_neg; + + env->fpscr &=3D ~(0x1F << FPSCR_FPRF); + env->fpscr |=3D fprf[ctz32(class)][isneg] << FPSCR_FPRF; +} + +#define COMPUTE_FPRF(tp) \ +void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \ +{ \ + set_fprf_from_class(env, tp##_classify(arg)); \ } =20 COMPUTE_FPRF(float16) --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153930161482622.624470249503247; Thu, 11 Oct 2018 16:46:54 -0700 (PDT) Received: from localhost ([::1]:37581 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAkfN-0004tJ-GI for importer@patchew.org; Thu, 11 Oct 2018 19:46:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54268) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAkar-0001oP-OB for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAkaq-0002In-B9 for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:13 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:34585) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAkao-0002FV-76 for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:10 -0400 Received: by mail-pl1-x62f.google.com with SMTP id f18-v6so4985258plr.1 for ; Thu, 11 Oct 2018 16:42:08 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id o12-v6sm12258302pgv.7.2018.10.11.16.42.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 16:42:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FKGYBm3b74Ebw4RKCZXEr3hKePvFludk+sTyBCj+v30=; b=kTrBVSwCyMCJ1jDWNuGKMaQsUHqoclR8xXA6GZeFv4J+BO5CX8R8jKJ6TUBF9tmg3x 1ja9MAW3oPdD5sacoaQ0+n47xpw2Fr52CPUfw+RSo6Di1UFXUcYEEU09TLy+WY/7S9w1 CFCOEvk56RyV5Cc+rbTnDzFPaxX+K7PNBKLdU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FKGYBm3b74Ebw4RKCZXEr3hKePvFludk+sTyBCj+v30=; b=mUeeZnRGda77jWpPgQO6C2E15dVdOHs0YtPQnoWd+5g7kWWqlzI2kPeRg+kfQ7I63Q btxwP93Z/f+NQUmxOqldpXRHixJcEhwMr3+1bgbB4ePNoYxQ7xOvdrTTc3vU1Lsb3tqm /XOdiCq1LkN7K8MtEw7cAWYNDMqdMRaow7CWOReUCgI/ehorY/elxLqqbT3ExcddKk4h b9zaHmEgRa18om83jeY1/EuQjWjaG0qje8PSp/xYXRo5QD4U6fV3/aeDeqs91l4jknoX jDzTTKM9+QyyUKjN0TSzwNam9yyDTnDFuGNT0ShGliVaEdSwRE5lPaE78zDBi1E1BahH 6F9A== X-Gm-Message-State: ABuFfojD3BRLmz7ZQ2j/TOftNX/a69QdX4o3EPE1OULJpqEYy5oDXhlm kbrkZaTwCik5wAQS3HIsCa3gsJXUVRI= X-Google-Smtp-Source: ACcGV61rp7OpDQ2IasyzvFWERR5L2HP4hQOBVz6xoNnORCgQ5SfXDH+NW8T9hPoXmRen2SI7MlQZww== X-Received: by 2002:a17:902:205:: with SMTP id 5-v6mr3503946plc.307.1539301327037; Thu, 11 Oct 2018 16:42:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 16:41:56 -0700 Message-Id: <20181011234159.11496-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011234159.11496-1-richard.henderson@linaro.org> References: <20181011234159.11496-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62f Subject: [Qemu-devel] [PATCH 4/7] target/ppc: Split out float_invalid_op_addsub X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/ppc/fpu_helper.c | 60 ++++++++++++++++++----------------------- 1 file changed, 26 insertions(+), 34 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 9ae55b1e93..111ce12a37 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -648,6 +648,17 @@ void helper_reset_fpstatus(CPUPPCState *env) set_float_exception_flags(0, &env->fp_status); } =20 +static void float_invalid_op_addsub(CPUPPCState *env, bool set_fpcc, + uintptr_t retaddr, int classes) +{ + if ((classes & ~is_neg) =3D=3D is_inf) { + /* Magnitude subtraction of infinities */ + float_invalid_op_vxisi(env, set_fpcc, retaddr); + } else if (classes & is_snan) { + float_invalid_op_vxsnan(env, retaddr); + } +} + /* fadd - fadd. */ float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2) { @@ -655,14 +666,9 @@ float64 helper_fadd(CPUPPCState *env, float64 arg1, fl= oat64 arg2) int status =3D get_float_exception_flags(&env->fp_status); =20 if (unlikely(status & float_flag_invalid)) { - if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) { - /* Magnitude subtraction of infinities */ - float_invalid_op_vxisi(env, 1, GETPC()); - } else if (float64_is_signaling_nan(arg1, &env->fp_status) || - float64_is_signaling_nan(arg2, &env->fp_status)) { - /* sNaN addition */ - float_invalid_op_vxsnan(env, GETPC()); - } + float_invalid_op_addsub(env, 1, GETPC(), + float64_classify(arg1) | + float64_classify(arg2)); } =20 return ret; @@ -675,14 +681,9 @@ float64 helper_fsub(CPUPPCState *env, float64 arg1, fl= oat64 arg2) int status =3D get_float_exception_flags(&env->fp_status); =20 if (unlikely(status & float_flag_invalid)) { - if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) { - /* Magnitude subtraction of infinities */ - float_invalid_op_vxisi(env, 1, GETPC()); - } else if (float64_is_signaling_nan(arg1, &env->fp_status) || - float64_is_signaling_nan(arg2, &env->fp_status)) { - /* sNaN addition */ - float_invalid_op_vxsnan(env, GETPC()); - } + float_invalid_op_addsub(env, 1, GETPC(), + float64_classify(arg1) | + float64_classify(arg2)); } =20 return ret; @@ -1803,12 +1804,9 @@ void helper_##name(CPUPPCState *env, uint32_t opcode= ) \ env->fp_status.float_exception_flags |=3D tstat.float_exception_fl= ags; \ = \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { = \ - if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) { = \ - float_invalid_op_vxisi(env, sfprf, GETPC()); = \ - } else if (tp##_is_signaling_nan(xa.fld, &tstat) || = \ - tp##_is_signaling_nan(xb.fld, &tstat)) { = \ - float_invalid_op_vxsnan(env, GETPC()); = \ - } = \ + float_invalid_op_addsub(env, sfprf, GETPC(), = \ + tp##_classify(xa.fld) | = \ + tp##_classify(xb.fld)); = \ } = \ = \ if (r2sp) { = \ @@ -1852,12 +1850,9 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t opcod= e) env->fp_status.float_exception_flags |=3D tstat.float_exception_flags; =20 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)= ) { - float_invalid_op_vxisi(env, 1, GETPC()); - } else if (float128_is_signaling_nan(xa.f128, &tstat) || - float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_vxsnan(env, GETPC()); - } + float_invalid_op_addsub(env, 1, GETPC(), + float128_classify(xa.f128) | + float128_classify(xb.f128)); } =20 helper_compute_fprf_float128(env, xt.f128); @@ -3518,12 +3513,9 @@ void helper_xssubqp(CPUPPCState *env, uint32_t opcod= e) env->fp_status.float_exception_flags |=3D tstat.float_exception_flags; =20 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)= ) { - float_invalid_op_vxisi(env, 1, GETPC()); - } else if (float128_is_signaling_nan(xa.f128, &tstat) || - float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_vxsnan(env, GETPC()); - } + float_invalid_op_addsub(env, 1, GETPC(), + float128_classify(xa.f128) | + float128_classify(xb.f128)); } =20 helper_compute_fprf_float128(env, xt.f128); --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539301634983379.44152344894246; Thu, 11 Oct 2018 16:47:14 -0700 (PDT) Received: from localhost ([::1]:37582 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAkfh-000559-T4 for importer@patchew.org; Thu, 11 Oct 2018 19:47:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54269) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAkar-0001oQ-Oz for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAkaq-0002JV-HV for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:13 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:41803) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAkao-0002Ga-BJ for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:12 -0400 Received: by mail-pg1-x52b.google.com with SMTP id 23-v6so4903914pgc.8 for ; Thu, 11 Oct 2018 16:42:09 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id o12-v6sm12258302pgv.7.2018.10.11.16.42.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 16:42:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uRAhsKb4wbHJPVgtVyUfypr8SUA1MJojDVWvlViH6F0=; b=PNK6Kren3CDGNpiVoU3puaeHBzdvw74w29AbFVRCFubyBMjs9BMwSXsJ41AHSqlUhN iL20nxVMVvZZyyY0dbpQLoZrk2anfCCz1R722E4DGfz2iTh3j++z7iovd3OHJkZ3znoT yf9LAYmpNbPk/gGi2qgBGEmCnvU0AgSEsstqQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uRAhsKb4wbHJPVgtVyUfypr8SUA1MJojDVWvlViH6F0=; b=IK7cdfXSpapAAolDbiUf3jePM7+0ZVTPHLdTINNoN8C0aw/vdht/Lb/9iowOH8Cu3f noC4NxFCxjULqoyoSQP0VqoQvD8akZL4het7sjvm2TcGUzJyKgAHDbjhSIjSY1uKYUO0 lYWs0IxdUqufmfp4WwGG6Uo6Ks6hDdv0reqa/Y9+1LUaDr+Mxt20PaPYC7o+mRXKjw8Q OFpQr0a2LM5g/JJE84Ln7KtNtVvQpSS1pf2TtbJppHT4uB43PHQy+7O7qSwl+WdwaSGA ND1UtCmmxU3H/pi5SSrNKJ2S4OBuwvsHcS3e/dVAEvd+7rNR2FShCnVMLFlGFaCEZFYb 2xlA== X-Gm-Message-State: ABuFfoiOFM9U7bth7nQUF688X213ZYXXNslQCpnKOtpU9Datyd9TQLHy 3hZ0oBoy6rVni+i8o09JwY2gQ4X9Id4= X-Google-Smtp-Source: ACcGV61eJn3SRvjpn4xnrKimnjsNwSYDntcvUiTIUeFXp5vEYLrDLjXq2tnFZ18E6DzsNaAi/Mthng== X-Received: by 2002:a62:8891:: with SMTP id l139-v6mr3596039pfd.198.1539301328502; Thu, 11 Oct 2018 16:42:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 16:41:57 -0700 Message-Id: <20181011234159.11496-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011234159.11496-1-richard.henderson@linaro.org> References: <20181011234159.11496-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52b Subject: [Qemu-devel] [PATCH 5/7] target/ppc: Split out float_invalid_op_mul X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/ppc/fpu_helper.c | 43 +++++++++++++++++++---------------------- 1 file changed, 20 insertions(+), 23 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 111ce12a37..ef251d062f 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -689,6 +689,17 @@ float64 helper_fsub(CPUPPCState *env, float64 arg1, fl= oat64 arg2) return ret; } =20 +static void float_invalid_op_mul(CPUPPCState *env, bool set_fprc, + uintptr_t retaddr, int classes) +{ + if ((classes & (is_zero | is_inf)) =3D=3D (is_zero | is_inf)) { + /* Multiplication of zero by infinity */ + float_invalid_op_vximz(env, set_fprc, retaddr); + } else if (classes & is_snan) { + float_invalid_op_vxsnan(env, retaddr); + } +} + /* fmul - fmul. */ float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2) { @@ -696,15 +707,9 @@ float64 helper_fmul(CPUPPCState *env, float64 arg1, fl= oat64 arg2) int status =3D get_float_exception_flags(&env->fp_status); =20 if (unlikely(status & float_flag_invalid)) { - if ((float64_is_infinity(arg1) && float64_is_zero(arg2)) || - (float64_is_zero(arg1) && float64_is_infinity(arg2))) { - /* Multiplication of zero by infinity */ - float_invalid_op_vximz(env, 1, GETPC()); - } else if (float64_is_signaling_nan(arg1, &env->fp_status) || - float64_is_signaling_nan(arg2, &env->fp_status)) { - /* sNaN multiplication */ - float_invalid_op_vxsnan(env, GETPC()); - } + float_invalid_op_mul(env, 1, GETPC(), + float64_classify(arg1) | + float64_classify(arg2)); } =20 return ret; @@ -1886,13 +1891,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ env->fp_status.float_exception_flags |=3D tstat.float_exception_fl= ags; \ = \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { = \ - if ((tp##_is_infinity(xa.fld) && tp##_is_zero(xb.fld)) || = \ - (tp##_is_infinity(xb.fld) && tp##_is_zero(xa.fld))) { = \ - float_invalid_op_vximz(env, sfprf, GETPC()); = \ - } else if (tp##_is_signaling_nan(xa.fld, &tstat) || = \ - tp##_is_signaling_nan(xb.fld, &tstat)) { = \ - float_invalid_op_vxsnan(env, GETPC()); = \ - } = \ + float_invalid_op_mul(env, sfprf, GETPC(), = \ + tp##_classify(xa.fld) | = \ + tp##_classify(xb.fld)); = \ } = \ = \ if (r2sp) { = \ @@ -1933,13 +1934,9 @@ void helper_xsmulqp(CPUPPCState *env, uint32_t opcod= e) env->fp_status.float_exception_flags |=3D tstat.float_exception_flags; =20 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - if ((float128_is_infinity(xa.f128) && float128_is_zero(xb.f128)) || - (float128_is_infinity(xb.f128) && float128_is_zero(xa.f128))) { - float_invalid_op_vximz(env, 1, GETPC()); - } else if (float128_is_signaling_nan(xa.f128, &tstat) || - float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_vxsnan(env, GETPC()); - } + float_invalid_op_mul(env, 1, GETPC(), + float128_classify(xa.f128) | + float128_classify(xb.f128)); } helper_compute_fprf_float128(env, xt.f128); =20 --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539301648932952.5859006079972; Thu, 11 Oct 2018 16:47:28 -0700 (PDT) Received: from localhost ([::1]:37583 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAkfv-0005FK-RB for importer@patchew.org; Thu, 11 Oct 2018 19:47:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54321) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAkat-0001po-Fw for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAkaq-0002K1-St for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:15 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:33528) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAkaq-0002Hj-IP for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:12 -0400 Received: by mail-pl1-x62f.google.com with SMTP id s4-v6so4986189plp.0 for ; Thu, 11 Oct 2018 16:42:11 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id o12-v6sm12258302pgv.7.2018.10.11.16.42.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 16:42:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rrqbySltHZh/y/niyNjXAqezkud1K+S4DIN9GBBTBW4=; b=cibegZFPMyi/FVk4pyMzBNJ1Ke3PIhA/g4PpXoBc28gSr4F3M5DoLbeRD++du6M9s9 7WhpPeE5vKoa/S4/lPalCEyT3fZeMsPJq7I70qA0uEMJne+7gnagNm9P3i+T3GfHhxPn dHxQTSOKIDX9gGU7NKXRE3QiNFQoValav18mQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rrqbySltHZh/y/niyNjXAqezkud1K+S4DIN9GBBTBW4=; b=Ev0fC6DtXBY6H1/sRH6XjR98Tq3TI96aBel9dEAt98n5YUfgwydiwmFblGDe9Zk4Jt HwlaCJkzndvhPDd7qBXnMAc/3vXUW10po3oUWlw+2FRTApUZOglca1Qyh61qweLCea/A 8Zh5Ra2lNzODsiZ0r5roBhD3NYLzGWxAkXUeo6zudIlzGvQFBcKYVMT35Hzs3uUMoguV 8hCrnEz51Ge5f8JrFb9ZiGWqYW0M+1DduZFbHuCz8FUomNh7OHEm0hMbC8oZvLUbSGPY BIOm5J6eKUn5FjzhL0nHqiWTHLy9/SM9IScDcdy8eGhp9plKj82TRxlZRrnAT8fxVCEb D5Xw== X-Gm-Message-State: ABuFfojZyyvk0DevURJL/9/JPmqLxTu6AT3BSct6A8YTyn6nQ0n7xCkk B1C4xo4FqpoK/PVA48xAhk9rUnXAYdY= X-Google-Smtp-Source: ACcGV62bqQkkHMEmtQK9C207FbE6PBTFtVkD2cUfU8dJbeZgT/cuH1VKs81JfF0DlH5zRgmqxj4O4g== X-Received: by 2002:a17:902:680e:: with SMTP id h14-v6mr3478209plk.177.1539301329914; Thu, 11 Oct 2018 16:42:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 16:41:58 -0700 Message-Id: <20181011234159.11496-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011234159.11496-1-richard.henderson@linaro.org> References: <20181011234159.11496-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62f Subject: [Qemu-devel] [PATCH 6/7] target/ppc: Split out float_invalid_op_div X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/ppc/fpu_helper.c | 52 +++++++++++++++++++---------------------- 1 file changed, 24 insertions(+), 28 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index ef251d062f..127c08bcec 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -715,6 +715,21 @@ float64 helper_fmul(CPUPPCState *env, float64 arg1, fl= oat64 arg2) return ret; } =20 +static void float_invalid_op_div(CPUPPCState *env, bool set_fprc, + uintptr_t retaddr, int classes) +{ + classes &=3D ~is_neg; + if (classes =3D=3D is_inf) { + /* Division of infinity by infinity */ + float_invalid_op_vxidi(env, set_fprc, retaddr); + } else if (classes =3D=3D is_zero) { + /* Division of zero by zero */ + float_invalid_op_vxzdz(env, set_fprc, retaddr); + } else if (classes & is_snan) { + float_invalid_op_vxsnan(env, retaddr); + } +} + /* fdiv - fdiv. */ float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2) { @@ -723,18 +738,9 @@ float64 helper_fdiv(CPUPPCState *env, float64 arg1, fl= oat64 arg2) =20 if (unlikely(status)) { if (status & float_flag_invalid) { - /* Determine what kind of invalid operation was seen. */ - if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) { - /* Division of infinity by infinity */ - float_invalid_op_vxidi(env, 1, GETPC()); - } else if (float64_is_zero(arg1) && float64_is_zero(arg2)) { - /* Division of zero by zero */ - float_invalid_op_vxzdz(env, 1, GETPC()); - } else if (float64_is_signaling_nan(arg1, &env->fp_status) || - float64_is_signaling_nan(arg2, &env->fp_status)) { - /* sNaN division */ - float_invalid_op_vxsnan(env, GETPC()); - } + float_invalid_op_div(env, 1, GETPC(), + float64_classify(arg1) | + float64_classify(arg2)); } if (status & float_flag_divbyzero) { float_zero_divide_excp(env, GETPC()); @@ -1969,14 +1975,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ env->fp_status.float_exception_flags |=3D tstat.float_exception_fl= ags; \ = \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { = \ - if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) { = \ - float_invalid_op_vxidi(env, sfprf, GETPC()); = \ - } else if (tp##_is_zero(xa.fld) && tp##_is_zero(xb.fld)) { = \ - float_invalid_op_vxzdz(env, sfprf, GETPC()); = \ - } else if (tp##_is_signaling_nan(xa.fld, &tstat) || = \ - tp##_is_signaling_nan(xb.fld, &tstat)) { = \ - float_invalid_op_vxsnan(env, GETPC()); = \ - } = \ + float_invalid_op_div(env, sfprf, GETPC(), = \ + tp##_classify(xa.fld) | = \ + tp##_classify(xb.fld)); = \ } = \ if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) = { \ float_zero_divide_excp(env, GETPC()); = \ @@ -2020,14 +2021,9 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t opcod= e) env->fp_status.float_exception_flags |=3D tstat.float_exception_flags; =20 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)= ) { - float_invalid_op_vxidi(env, 1, GETPC()); - } else if (float128_is_zero(xa.f128) && float128_is_zero(xb.f128))= { - float_invalid_op_vxzdz(env, 1, GETPC()); - } else if (float128_is_signaling_nan(xa.f128, &tstat) || - float128_is_signaling_nan(xb.f128, &tstat)) { - float_invalid_op_vxsnan(env, GETPC()); - } + float_invalid_op_div(env, 1, GETPC(), + float128_classify(xa.f128) | + float128_classify(xb.f128)); } if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { float_zero_divide_excp(env, GETPC()); --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539301791425187.22633310600725; Thu, 11 Oct 2018 16:49:51 -0700 (PDT) Received: from localhost ([::1]:37592 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAki8-0006qN-3J for importer@patchew.org; Thu, 11 Oct 2018 19:49:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54302) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAkat-0001pQ-4J for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAkaq-0002KD-VO for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:15 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:34587) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAkaq-0002IZ-LA for qemu-devel@nongnu.org; Thu, 11 Oct 2018 19:42:12 -0400 Received: by mail-pl1-x631.google.com with SMTP id f18-v6so4985337plr.1 for ; Thu, 11 Oct 2018 16:42:12 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id o12-v6sm12258302pgv.7.2018.10.11.16.42.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 16:42:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b1EdQq+2c3tOlxyFZkdYZBw9+bmacMlVweBGK41Fvg4=; b=SlqLG8BqWUMnGDcq/+GoM5tHPJ/EwGqCy2Afpdc4V8y7qqMFafXDKzVOulA5daZxqR mxeRn1674lm/tbqJHwh1KI71PRWG5LWnJkMRanNC1Yo2bRQx+hrtp4CExDD12qu5aIu4 5WVPaLALL/Lj0Xv7Dv1P/1GL+DwxKOuHmMmw0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b1EdQq+2c3tOlxyFZkdYZBw9+bmacMlVweBGK41Fvg4=; b=OKLvfUp9j0ViAoOoEycywwzPKckWaMZtpXkiLxnoCkP/HiDtIPmWcSbgEYiKcxnQBx zbGRmF7jXYCTvGnzmJ8HzQqYuPEBYMpKSq2VQpEP6Bppg2Ri5NJ1lKMIQptbQPXJSUPM +ucg7SP+5HNBojtukrvTmn5801y1KfibbUj49MDZp0a4/TTh1yCTynR/GyyyBmhRbDCR 3xP854FlX4MewFIlQ/khoyxU2OnTcNd4fgWhpmPplT1SNUfzhzuXiP2DcpnmGgl1oBwW R4BayGX7HaUrpe1hYTonb6YvLfp4MEseDBt3Ut13gcFWrLFkKoApKYKRHkdk0kkbF2MP Sfvg== X-Gm-Message-State: ABuFfohOU8XiHGnKnshTIGN6HA5LFo2tV+1b5tJFpCmWdmStx4FRNpee zv71UXfO9Pu5MJS3HJ+Jx0rGv3vgl3o= X-Google-Smtp-Source: ACcGV63NgQVA58mYEQygZ8ka65tBKFTd8VvmxCieEafXE/ZDYqU9i/VNnHObEEqFBg8/yc8qjxTu+Q== X-Received: by 2002:a17:902:b581:: with SMTP id a1-v6mr3503852pls.126.1539301331254; Thu, 11 Oct 2018 16:42:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 16:41:59 -0700 Message-Id: <20181011234159.11496-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011234159.11496-1-richard.henderson@linaro.org> References: <20181011234159.11496-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::631 Subject: [Qemu-devel] [PATCH 7/7] target/ppc: Split out float_invalid_cvt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/ppc/fpu_helper.c | 67 +++++++++++++++++------------------------ 1 file changed, 28 insertions(+), 39 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 127c08bcec..2ed4f42275 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -750,30 +750,30 @@ float64 helper_fdiv(CPUPPCState *env, float64 arg1, f= loat64 arg2) return ret; } =20 +static void float_invalid_cvt(CPUPPCState *env, bool set_fprc, + uintptr_t retaddr, int class1) +{ + float_invalid_op_vxcvi(env, set_fprc, retaddr); + if (class1 & is_snan) { + float_invalid_op_vxsnan(env, retaddr); + } +} =20 #define FPU_FCTI(op, cvt, nanval) \ -uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \ +uint64_t helper_##op(CPUPPCState *env, float64 arg) \ { \ - CPU_DoubleU farg; \ + uint64_t ret =3D float64_to_##cvt(arg, &env->fp_status); \ + int status =3D get_float_exception_flags(&env->fp_status); \ \ - farg.ll =3D arg; \ - farg.ll =3D float64_to_##cvt(farg.d, &env->fp_status); \ - \ - if (unlikely(env->fp_status.float_exception_flags)) { \ - if (float64_is_any_nan(arg)) { \ - float_invalid_op_vxcvi(env, 1, GETPC()); \ - if (float64_is_signaling_nan(arg, &env->fp_status)) { \ - float_invalid_op_vxsnan(env, GETPC()); \ - } \ - farg.ll =3D nanval; \ - } else if (env->fp_status.float_exception_flags & \ - float_flag_invalid) { \ - float_invalid_op_vxcvi(env, 1, GETPC()); \ + if (unlikely(status)) { \ + if (status & float_flag_invalid) { \ + float_invalid_cvt(env, 1, GETPC(), float64_classify(arg)); \ + ret =3D nanval; \ } \ do_float_check_status(env, GETPC()); \ } \ - return farg.ll; \ - } + return ret; \ +} =20 FPU_FCTI(fctiw, int32, 0x80000000U) FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000U) @@ -2965,6 +2965,7 @@ uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t = xb) #define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, rnan) = \ void helper_##op(CPUPPCState *env, uint32_t opcode) = \ { = \ + int all_flags =3D env->fp_status.float_exception_flags, flags; = \ ppc_vsr_t xt, xb; = \ int i; = \ = \ @@ -2972,22 +2973,18 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)= \ getVSR(xT(opcode), &xt, env); = \ = \ for (i =3D 0; i < nels; i++) { = \ - if (unlikely(stp##_is_any_nan(xb.sfld))) { = \ - if (stp##_is_signaling_nan(xb.sfld, &env->fp_status)) { = \ - float_invalid_op_vxsnan(env, GETPC()); = \ - } = \ - float_invalid_op_vxcvi(env, 0, GETPC()); = \ + env->fp_status.float_exception_flags =3D 0; = \ + xt.tfld =3D stp##_to_##ttp##_round_to_zero(xb.sfld, &env->fp_statu= s); \ + flags =3D env->fp_status.float_exception_flags; = \ + if (unlikely(flags & float_flag_invalid)) { = \ + float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb.sfld)); = \ xt.tfld =3D rnan; = \ - } else { = \ - xt.tfld =3D stp##_to_##ttp##_round_to_zero(xb.sfld, = \ - &env->fp_status); = \ - if (env->fp_status.float_exception_flags & float_flag_invalid)= { \ - float_invalid_op_vxcvi(env, 0, GETPC()); = \ - } = \ } = \ + all_flags |=3D flags; = \ } = \ = \ putVSR(xT(opcode), &xt, env); = \ + env->fp_status.float_exception_flags =3D all_flags; = \ do_float_check_status(env, GETPC()); = \ } =20 @@ -3025,18 +3022,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)= \ getVSR(rB(opcode) + 32, &xb, env); = \ memset(&xt, 0, sizeof(xt)); = \ = \ - if (unlikely(stp##_is_any_nan(xb.sfld))) { = \ - if (stp##_is_signaling_nan(xb.sfld, &env->fp_status)) { = \ - float_invalid_op_vxsnan(env, GETPC()); = \ - } = \ - float_invalid_op_vxcvi(env, 0, GETPC()); = \ + xt.tfld =3D stp##_to_##ttp##_round_to_zero(xb.sfld, &env->fp_status); = \ + if (env->fp_status.float_exception_flags & float_flag_invalid) { = \ + float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb.sfld)); = \ xt.tfld =3D rnan; = \ - } else { = \ - xt.tfld =3D stp##_to_##ttp##_round_to_zero(xb.sfld, = \ - &env->fp_status); = \ - if (env->fp_status.float_exception_flags & float_flag_invalid) { = \ - float_invalid_op_vxcvi(env, 0, GETPC()); = \ - } = \ } = \ = \ putVSR(rD(opcode) + 32, &xt, env); = \ --=20 2.17.1