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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YFQr/JNTa/QXkvyuZtso9GlnKeUMjxXJ1Iso8ke3tsU=; b=JvtRdgCEb6EhrzFeGlHZS40h4ZrJ+ZIi43MZHg0ggFMa+YdlPdVDrcxyjpD9KebvA1 MAg8Fl/PPMQPbIl8r7nyk5e6uPaSU1fNygB5lVDyhLu6ujOeCFaLgwm3KLRUKvA60iDl FzCHnODx9ulbKuZVg7fBaZCBDjRUmIWhvysGI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YFQr/JNTa/QXkvyuZtso9GlnKeUMjxXJ1Iso8ke3tsU=; b=tOw8eXBoU7CQVHU72ZZYyfGyxwX0qYAIm9oBF5wg/C8j8lOPmmIpFYhvyP0Y1g7mmJ c3M/qnkDjs46xOO+5v3YcTl40BcvA4xPDzTVGRSshsN/ONjihZmcPj3t4r5MNrKngXcU NpLNZsrNEiYVy4i+ZvBAtjX0HPQs0n7bb7iWzGeusI/qg0Gag87pI+hwSdLSxNCeNb4Z tfH17VclMnXoutCv2/wMSBkjseQghqeYCajfai8MJL3ezQS4YYm/OeMt0XLVL/JMRuq0 l66DTA9PKcMlFBWIm/gDXGBfUqtlOUWZtLVWBIHmKOgd9FyjL5zE8JBzouKL5wX36Bs/ 1lnA== X-Gm-Message-State: ABuFfoiJSGpjiGvvp6/IjHuUDrH9dLoqAt+0mR4ASabl3IpszJGb3uIq XDcSe/B0WdPLu1q+QFp7gpfG73eojzg= X-Google-Smtp-Source: ACcGV61SZUl4hK8iIqnaVLX3xXugqdd5pCUBcZY6L+uBAxQe+p1eSVxhoQyEBEUGwhuz19RFq8R2mA== X-Received: by 2002:a62:5251:: with SMTP id g78-v6mr3100667pfb.256.1539291137435; Thu, 11 Oct 2018 13:52:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:51:52 -0700 Message-Id: <20181011205206.3552-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 06/20] target/arm: Use gvec for NEON VDUP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Also introduces neon_element_offset to find the env offset of a specific element within a neon register. Signed-off-by: Richard Henderson --- target/arm/translate.c | 63 ++++++++++++++++++++++++------------------ 1 file changed, 36 insertions(+), 27 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d59ffa1c67..4ac526e298 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1585,6 +1585,25 @@ neon_reg_offset (int reg, int n) return vfp_reg_offset(0, sreg); } =20 +/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE, + * where 0 is the least significant end of the register. + */ +static inline long +neon_element_offset(int reg, int element, TCGMemOp size) +{ + int element_size =3D 1 << size; + int ofs =3D element * element_size; +#ifdef HOST_WORDS_BIGENDIAN + /* Calculate the offset assuming fully little-endian, + * then XOR to account for the order of the 8-byte units. + */ + if (element_size < 8) { + ofs ^=3D 8 - element_size; + } +#endif + return neon_reg_offset(reg, 0) + ofs; +} + static TCGv_i32 neon_load_reg(int reg, int pass) { TCGv_i32 tmp =3D tcg_temp_new_i32(); @@ -3432,17 +3451,10 @@ static int disas_vfp_insn(DisasContext *s, uint32_t= insn) tmp =3D load_reg(s, rd); if (insn & (1 << 23)) { /* VDUP */ - if (size =3D=3D 0) { - gen_neon_dup_u8(tmp, 0); - } else if (size =3D=3D 1) { - gen_neon_dup_low16(tmp); - } - for (n =3D 0; n <=3D pass * 2; n++) { - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp2, tmp); - neon_store_reg(rn, n, tmp2); - } - neon_store_reg(rn, n, tmp); + int vec_size =3D pass ? 16 : 8; + tcg_gen_gvec_dup_i32(size, neon_reg_offset(rn, 0), + vec_size, vec_size, tmp); + tcg_temp_free_i32(tmp); } else { /* VMOV */ switch (size) { @@ -7755,28 +7767,25 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) tcg_temp_free_i32(tmp); } else if ((insn & 0x380) =3D=3D 0) { /* VDUP */ + int element; + TCGMemOp size; + if ((insn & (7 << 16)) =3D=3D 0 || (q && (rd & 1))) { return 1; } - if (insn & (1 << 19)) { - tmp =3D neon_load_reg(rm, 1); - } else { - tmp =3D neon_load_reg(rm, 0); - } if (insn & (1 << 16)) { - gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8); + size =3D MO_8; + element =3D (insn >> 17) & 7; } else if (insn & (1 << 17)) { - if ((insn >> 18) & 1) - gen_neon_dup_high16(tmp); - else - gen_neon_dup_low16(tmp); + size =3D MO_16; + element =3D (insn >> 18) & 3; + } else { + size =3D MO_32; + element =3D (insn >> 19) & 1; } - for (pass =3D 0; pass < (q ? 4 : 2); pass++) { - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp2, tmp); - neon_store_reg(rd, pass, tmp2); - } - tcg_temp_free_i32(tmp); + tcg_gen_gvec_dup_mem(size, neon_reg_offset(rd, 0), + neon_element_offset(rm, element, size= ), + q ? 16 : 8, q ? 16 : 8); } else { return 1; } --=20 2.17.1