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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eLZcGiUeKPgvYZrKbYk4xKbhpVB1ppGUGYC7GHerwzo=; b=bslszRJp0ypQHhGp+YoTGxjR8/O8PkfR5zMBCJw8EtkjDg++FGL7bcTbQZinS4Gx/e uO0MEr6tCB7NNZOysA0z2GWmJGZg067Ja0z1adAq4Ahah5kNmOWUW0DEe7i88W5s/Wpx CrBPMRiYyQOJ4zOlNYQrQ3/F0JPkaMrH8Zhu4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eLZcGiUeKPgvYZrKbYk4xKbhpVB1ppGUGYC7GHerwzo=; b=ja1boNLrRyeBMVYlJzt0ypsoywgq2s+Dv3OqtLCyg9q0Q2uKhOJ44DdBeFQ6s0JI/S eZ0vxJQXzq4c3Gcbuo815g76txvzYs76qMqTZKCteltYgzB5HutgPeyKinLuK9Hs2ttw SN82Pc0MCqv8PV/cJsniwhsFLyw8NqZAxqg94jZwRhhTbqNuhQDw6SpnKgfyrUvJqONP riwT2dUXaC2YkCvAw61YxHyEVsuZG7I4LTgVrlEi2KgSqXiKizEVdDeJ6JITaPeRCSdf swtBDqqXzvsoJqGqFqXXD+M09KN1joCM7F0SgTPC/ORz4qoWWQz8UPeKLOtKDdy/6/eP B/lw== X-Gm-Message-State: ABuFfoirWw1jI/PnlKxME6ZnjQcNzzG07stnpq7AcvfgU6UdAHjmJWvX h1SsM8oNzZ1DPBfcM0LrwyFB1NgLey0= X-Google-Smtp-Source: ACcGV61vE3VpAQsPHAviqzz/cvJskr8e3yQv2yhLBYTGjrcWK8icaQV7gyQ3sm/oakgSyuvzW53npg== X-Received: by 2002:a63:f14a:: with SMTP id o10-v6mr2747764pgk.339.1539291151076; Thu, 11 Oct 2018 13:52:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:52:01 -0700 Message-Id: <20181011205206.3552-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52e Subject: [Qemu-devel] [PATCH 15/20] target/arm: Use gvec for NEON_3R_VML X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move mla_op and mls_op expanders from translate-a64.c. Signed-off-by: Richard Henderson --- target/arm/translate.h | 2 + target/arm/translate-a64.c | 106 ----------------------------- target/arm/translate.c | 134 ++++++++++++++++++++++++++++++++----- 3 files changed, 120 insertions(+), 122 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index ef44f0a5e5..d11d504301 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -195,6 +195,8 @@ static inline TCGv_i32 get_ahp_flag(void) extern const GVecGen3 bsl_op; extern const GVecGen3 bit_op; extern const GVecGen3 bif_op; +extern const GVecGen3 mla_op[4]; +extern const GVecGen3 mls_op[4]; extern const GVecGen2i ssra_op[4]; extern const GVecGen2i usra_op[4]; extern const GVecGen2i sri_op[4]; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f47c132e6c..94f7127c0e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10410,66 +10410,6 @@ static void disas_simd_3same_float(DisasContext *s= , uint32_t insn) } } =20 -static void gen_mla8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - gen_helper_neon_mul_u8(a, a, b); - gen_helper_neon_add_u8(d, d, a); -} - -static void gen_mla16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - gen_helper_neon_mul_u16(a, a, b); - gen_helper_neon_add_u16(d, d, a); -} - -static void gen_mla32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - tcg_gen_mul_i32(a, a, b); - tcg_gen_add_i32(d, d, a); -} - -static void gen_mla64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) -{ - tcg_gen_mul_i64(a, a, b); - tcg_gen_add_i64(d, d, a); -} - -static void gen_mla_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) -{ - tcg_gen_mul_vec(vece, a, a, b); - tcg_gen_add_vec(vece, d, d, a); -} - -static void gen_mls8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - gen_helper_neon_mul_u8(a, a, b); - gen_helper_neon_sub_u8(d, d, a); -} - -static void gen_mls16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - gen_helper_neon_mul_u16(a, a, b); - gen_helper_neon_sub_u16(d, d, a); -} - -static void gen_mls32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - tcg_gen_mul_i32(a, a, b); - tcg_gen_sub_i32(d, d, a); -} - -static void gen_mls64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) -{ - tcg_gen_mul_i64(a, a, b); - tcg_gen_sub_i64(d, d, a); -} - -static void gen_mls_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) -{ - tcg_gen_mul_vec(vece, a, a, b); - tcg_gen_sub_vec(vece, d, d, a); -} - /* Integer op subgroup of C3.6.16. */ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) { @@ -10488,52 +10428,6 @@ static void disas_simd_3same_int(DisasContext *s, = uint32_t insn) .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; - static const GVecGen3 mla_op[4] =3D { - { .fni4 =3D gen_mla8_i32, - .fniv =3D gen_mla_vec, - .opc =3D INDEX_op_mul_vec, - .load_dest =3D true, - .vece =3D MO_8 }, - { .fni4 =3D gen_mla16_i32, - .fniv =3D gen_mla_vec, - .opc =3D INDEX_op_mul_vec, - .load_dest =3D true, - .vece =3D MO_16 }, - { .fni4 =3D gen_mla32_i32, - .fniv =3D gen_mla_vec, - .opc =3D INDEX_op_mul_vec, - .load_dest =3D true, - .vece =3D MO_32 }, - { .fni8 =3D gen_mla64_i64, - .fniv =3D gen_mla_vec, - .opc =3D INDEX_op_mul_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, - .load_dest =3D true, - .vece =3D MO_64 }, - }; - static const GVecGen3 mls_op[4] =3D { - { .fni4 =3D gen_mls8_i32, - .fniv =3D gen_mls_vec, - .opc =3D INDEX_op_mul_vec, - .load_dest =3D true, - .vece =3D MO_8 }, - { .fni4 =3D gen_mls16_i32, - .fniv =3D gen_mls_vec, - .opc =3D INDEX_op_mul_vec, - .load_dest =3D true, - .vece =3D MO_16 }, - { .fni4 =3D gen_mls32_i32, - .fniv =3D gen_mls_vec, - .opc =3D INDEX_op_mul_vec, - .load_dest =3D true, - .vece =3D MO_32 }, - { .fni8 =3D gen_mls64_i64, - .fniv =3D gen_mls_vec, - .opc =3D INDEX_op_mul_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, - .load_dest =3D true, - .vece =3D MO_64 }, - }; =20 int is_q =3D extract32(insn, 30, 1); int u =3D extract32(insn, 29, 1); diff --git a/target/arm/translate.c b/target/arm/translate.c index 104b49543d..5008a24ffd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5468,7 +5468,7 @@ static void gen_neon_narrow_op(int op, int u, int siz= e, #define NEON_3R_VABA 15 #define NEON_3R_VADD_VSUB 16 #define NEON_3R_VTST_VCEQ 17 -#define NEON_3R_VML 18 /* VMLA, VMLAL, VMLS, VMLSL */ +#define NEON_3R_VML 18 /* VMLA, VMLS */ #define NEON_3R_VMUL 19 #define NEON_3R_VPMAX 20 #define NEON_3R_VPMIN 21 @@ -6032,6 +6032,117 @@ const GVecGen2i sli_op[4] =3D { .vece =3D MO_64 }, }; =20 +static void gen_mla8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u8(a, a, b); + gen_helper_neon_add_u8(d, d, a); +} + +static void gen_mls8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u8(a, a, b); + gen_helper_neon_sub_u8(d, d, a); +} + +static void gen_mla16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u16(a, a, b); + gen_helper_neon_add_u16(d, d, a); +} + +static void gen_mls16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u16(a, a, b); + gen_helper_neon_sub_u16(d, d, a); +} + +static void gen_mla32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_mul_i32(a, a, b); + tcg_gen_add_i32(d, d, a); +} + +static void gen_mls32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_mul_i32(a, a, b); + tcg_gen_sub_i32(d, d, a); +} + +static void gen_mla64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_mul_i64(a, a, b); + tcg_gen_add_i64(d, d, a); +} + +static void gen_mls64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_mul_i64(a, a, b); + tcg_gen_sub_i64(d, d, a); +} + +static void gen_mla_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) +{ + tcg_gen_mul_vec(vece, a, a, b); + tcg_gen_add_vec(vece, d, d, a); +} + +static void gen_mls_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) +{ + tcg_gen_mul_vec(vece, a, a, b); + tcg_gen_sub_vec(vece, d, d, a); +} + +/* Note that while NEON does not support VMLA and VMLS as 64-bit ops, + * these tables are shared with AArch64 which does support them. + */ +const GVecGen3 mla_op[4] =3D { + { .fni4 =3D gen_mla8_i32, + .fniv =3D gen_mla_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_8 }, + { .fni4 =3D gen_mla16_i32, + .fniv =3D gen_mla_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_16 }, + { .fni4 =3D gen_mla32_i32, + .fniv =3D gen_mla_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_32 }, + { .fni8 =3D gen_mla64_i64, + .fniv =3D gen_mla_vec, + .opc =3D INDEX_op_mul_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .load_dest =3D true, + .vece =3D MO_64 }, +}; + +const GVecGen3 mls_op[4] =3D { + { .fni4 =3D gen_mls8_i32, + .fniv =3D gen_mls_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_8 }, + { .fni4 =3D gen_mls16_i32, + .fniv =3D gen_mls_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_16 }, + { .fni4 =3D gen_mls32_i32, + .fniv =3D gen_mls_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_32 }, + { .fni8 =3D gen_mls64_i64, + .fniv =3D gen_mls_vec, + .opc =3D INDEX_op_mul_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .load_dest =3D true, + .vece =3D MO_64 }, +}; + /* Translate a NEON data processing instruction. Return nonzero if the instruction is invalid. We process data in a mixture of 32-bit and 64-bit chunks. @@ -6233,7 +6344,13 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) return 0; } break; + + case NEON_3R_VML: /* VMLA, VMLS */ + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size, + u ? &mls_op[size] : &mla_op[size]); + return 0; } + if (size =3D=3D 3) { /* 64-bit element instructions. */ for (pass =3D 0; pass < (q ? 2 : 1); pass++) { @@ -6435,21 +6552,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) } } break; - case NEON_3R_VML: /* VMLA, VMLAL, VMLS,VMLSL */ - switch (size) { - case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break; - case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break; - case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break; - default: abort(); - } - tcg_temp_free_i32(tmp2); - tmp2 =3D neon_load_reg(rd, pass); - if (u) { /* VMLS */ - gen_neon_rsb(size, tmp, tmp2); - } else { /* VMLA */ - gen_neon_add(size, tmp, tmp2); - } - break; case NEON_3R_VMUL: /* VMUL.P8; other cases already eliminated. */ gen_helper_neon_mul_p8(tmp, tmp, tmp2); --=20 2.17.1