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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UCjLvGDYtuODMoxEmWHRu54PGDreeQMV1QK7QOr2PKo=; b=NhfVVuNO8W/bs+fpTtnykRo7kNLA/H6Pb+V4y2/VbyCzgEOWnvXozY0pSYnH1PNa68 +uMpBr7hLsZyB+bH2domJtU3HMD/agR7VekYZX6MeVDA7RX1pveLYGUS7Y0558CP6yum As5ss5Y14SzpOZEcv+xqRs8BeeF9+ssuQkNjo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UCjLvGDYtuODMoxEmWHRu54PGDreeQMV1QK7QOr2PKo=; b=geymNtQ5kYIEWoVI0XJpsNy2w7mKihkonZgN+CJdDAFZeyyPuCsD6a/gFMZyccFKWs MFgqyMm6UFV5zngzf6pMb+ZyFEosnU/d7GgiSExTnvFgx405skNjwGeOQlfiQ9RT1AlM QmFIUVu6ALg6y4va6Jwzl3D42TY3s70d3jpGrG0k0KRkCXrg8T+0u1sgXGEbya+O8aol B1W1zHT09cnFohKUSTKxn+HjlrVt9bz9FavcHWTCRZYITym751J8mKRqe6i/r3EgOJA0 h/XR+s/q1sld6aMjllBR0fWWBEOCkIF8bMu3WrEQnsHSjhb4FSAdrjfozCDNtCTXEXWg awuA== X-Gm-Message-State: ABuFfojrVGmigWbd0UKJUxyACqt8F3OLjEBelZ9GFUByLU9BlTde+FCt 4eKbYkAF8w10vw5r+e7CvCztjkdRa/M= X-Google-Smtp-Source: ACcGV63L6XKQdLD96mUO5QUhhydbsdrCXyrjOTnJgG/tvAgkYBGa/7ImR+lUETxs7c9rJqvRSwcFjA== X-Received: by 2002:a17:902:b403:: with SMTP id x3-v6mr3040457plr.237.1539291146556; Thu, 11 Oct 2018 13:52:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:51:58 -0700 Message-Id: <20181011205206.3552-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 12/20] target/arm: Use gvec for VSHR, VSHL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate.c | 70 +++++++++++++++++++++++++++++------------- 1 file changed, 48 insertions(+), 22 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index e195efcc55..a16f323d52 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6373,8 +6373,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) size--; } shift =3D (insn >> 16) & ((1 << (3 + size)) - 1); - /* To avoid excessive duplication of ops we implement shift - by immediate using the variable shift operations. */ if (op < 8) { /* Shift by immediate: VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */ @@ -6386,37 +6384,62 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) } /* Right shifts are encoded as N - shift, where N is the element size in bits. */ - if (op <=3D 4) + if (op <=3D 4) { shift =3D shift - (1 << (size + 3)); + } + + switch (op) { + case 0: /* VSHR */ + /* Right shift comes here negative. */ + shift =3D -shift; + /* Shifts larger than the element size are architectur= ally + * valid. Unsigned results in all zeros; signed resul= ts + * in all sign bits. + */ + if (!u) { + tcg_gen_gvec_sari(size, rd_ofs, rm_ofs, + MIN(shift, (8 << size) - 1), + vec_size, vec_size); + } else if (shift >=3D 8 << size) { + tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size, 0); + } else { + tcg_gen_gvec_shri(size, rd_ofs, rm_ofs, shift, + vec_size, vec_size); + } + return 0; + + case 5: /* VSHL, VSLI */ + if (!u) { /* VSHL */ + /* Shifts larger than the element size are + * architecturally valid and results in zero. + */ + if (shift >=3D 8 << size) { + tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size,= 0); + } else { + tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift, + vec_size, vec_size); + } + return 0; + } + break; + } + if (size =3D=3D 3) { count =3D q + 1; } else { count =3D q ? 4: 2; } - switch (size) { - case 0: - imm =3D (uint8_t) shift; - imm |=3D imm << 8; - imm |=3D imm << 16; - break; - case 1: - imm =3D (uint16_t) shift; - imm |=3D imm << 16; - break; - case 2: - case 3: - imm =3D shift; - break; - default: - abort(); - } + + /* To avoid excessive duplication of ops we implement shift + * by immediate using the variable shift operations. + */ + imm =3D dup_const(size, shift); =20 for (pass =3D 0; pass < count; pass++) { if (size =3D=3D 3) { neon_load_reg64(cpu_V0, rm + pass); tcg_gen_movi_i64(cpu_V1, imm); switch (op) { - case 0: /* VSHR */ case 1: /* VSRA */ if (u) gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cp= u_V1); @@ -6447,6 +6470,8 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) cpu_V0, cpu_V1); } break; + default: + g_assert_not_reached(); } if (op =3D=3D 1 || op =3D=3D 3) { /* Accumulate. */ @@ -6475,7 +6500,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) tmp2 =3D tcg_temp_new_i32(); tcg_gen_movi_i32(tmp2, imm); switch (op) { - case 0: /* VSHR */ case 1: /* VSRA */ GEN_NEON_INTEGER_OP(shl); break; @@ -6513,6 +6537,8 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case 7: /* VQSHL */ GEN_NEON_INTEGER_OP_ENV(qshl); break; + default: + g_assert_not_reached(); } tcg_temp_free_i32(tmp2); =20 --=20 2.17.1