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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GCq6GLtd5YYBu/ORSkQACpXqajeyz6Fb7Yy9QHPeNAs=; b=TtR88TN1Z7tGBq4OJS6AXLXAXfxsJLQOkVcD88sd0a5Y544f0kuKchUaFr0LmgFmTJ XP3nfRYF35ixnXXaG1paVUEOPo3kKLNHksqd1wBVJkJ0INgj1/zYkHzjoxL31ii/f5/8 OcaRbSAEAT4r9jH/yt4PQ4oXRrkf/fWNkE23w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GCq6GLtd5YYBu/ORSkQACpXqajeyz6Fb7Yy9QHPeNAs=; b=VH8PvFcapKwLDiDKYNIX2lmos4Kv28I4jP30j+XIGtiA1X73kJjWGQEBQ0JpVwxrUC GLf97XnGVPzvCIohOlQJ4oVUQcEQax4y2ATbGdWep64LEYtXh7dZUTWsFylkOrLyr/F+ SdVCBkMCmHyAWeO8/1cW3F3vXlpWw/f/zeThiGG8EpXtOb8LF9ksSr+dHNq1VFiyTgKv Fs+Bi1N8aW+KsRZ2yB0kYagB/QOTCyy4ja6MZscz7+DE3TnYkI/EscVHopY7M+mj2CgX 6VQdfMBtHGA+TIEa9qaqKs+qwpqAwNQCR9dX6oswUaO4LJHUCL+BfAK9oYWv/ffcT/Af nccw== X-Gm-Message-State: ABuFfogf3ByiqruP+MFfGjKEeeVMyEuynB4E0QL63KgnZ1wugE/0haOB Ykf4nOdlpYIOYp8/3neS07fzw+VhB78= X-Google-Smtp-Source: ACcGV62OQj9v7a+Fl7qdSVHsTD64iZKpG8KCOM+WP6/Ul3aIPzXmjMoKaTDYmHqT87T3xCHh52dUFA== X-Received: by 2002:a17:902:d68e:: with SMTP id v14-v6mr3015205ply.140.1539291130331; Thu, 11 Oct 2018 13:52:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:51:47 -0700 Message-Id: <20181011205206.3552-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62e Subject: [Qemu-devel] [PATCH 01/20] target/arm: Hoist address increment for vector memory ops X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This can reduce the number of opcodes required for certain complex forms of load-multiple (e.g. ld4.16b). Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c403b12eb9..76b5ca3606 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3012,7 +3012,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) bool is_store =3D !extract32(insn, 22, 1); bool is_postidx =3D extract32(insn, 23, 1); bool is_q =3D extract32(insn, 30, 1); - TCGv_i64 tcg_addr, tcg_rn; + TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes; =20 int ebytes =3D 1 << size; int elements =3D (is_q ? 128 : 64) / (8 << size); @@ -3077,6 +3077,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) tcg_rn =3D cpu_reg_sp(s, rn); tcg_addr =3D tcg_temp_new_i64(); tcg_gen_mov_i64(tcg_addr, tcg_rn); + tcg_ebytes =3D tcg_const_i64(ebytes); =20 for (r =3D 0; r < rpt; r++) { int e; @@ -3101,7 +3102,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) clear_vec_high(s, is_q, tt); } } - tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes); + tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes); tt =3D (tt + 1) % 32; } } @@ -3115,6 +3116,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); } } + tcg_temp_free_i64(tcg_ebytes); tcg_temp_free_i64(tcg_addr); } =20 @@ -3157,7 +3159,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) bool replicate =3D false; int index =3D is_q << 3 | S << 2 | size; int ebytes, xs; - TCGv_i64 tcg_addr, tcg_rn; + TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes; =20 switch (scale) { case 3: @@ -3210,6 +3212,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) tcg_rn =3D cpu_reg_sp(s, rn); tcg_addr =3D tcg_temp_new_i64(); tcg_gen_mov_i64(tcg_addr, tcg_rn); + tcg_ebytes =3D tcg_const_i64(ebytes); =20 for (xs =3D 0; xs < selem; xs++) { if (replicate) { @@ -3252,7 +3255,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) do_vec_st(s, rt, index, tcg_addr, scale); } } - tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes); + tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes); rt =3D (rt + 1) % 32; } =20 @@ -3264,6 +3267,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); } } + tcg_temp_free_i64(tcg_ebytes); tcg_temp_free_i64(tcg_addr); } =20 --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539291278438947.3931759910976; Thu, 11 Oct 2018 13:54:38 -0700 (PDT) Received: from localhost ([::1]:37072 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhye-0007tf-SN for importer@patchew.org; Thu, 11 Oct 2018 16:54:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44990) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhwh-0006l2-2P for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAhwZ-0004j5-G2 for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:33 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:33669) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAhwM-0003D1-DK for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:17 -0400 Received: by mail-pg1-x534.google.com with SMTP id y18-v6so4746641pge.0 for ; Thu, 11 Oct 2018 13:52:13 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ahHHwkY/r6hC8r7wrxjlV68iRRvkXAnXssBuRUL9bNA=; b=ih5KKLKTJeH+qJ5O6f7ENroRtgYJYgiSiPu20mFi1IOGmmXd0n6I3oD3XMj6SP1/zk T+8bQzEM6bmNkbk15LgIaW29J2lpfFxiBZ66WOH/Ebc+f8ziNlC0ET7AJO4JADdmVCEs TWlD4JQsm49bT5t6NGXVJkMllvyjNfbFUQXdM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ahHHwkY/r6hC8r7wrxjlV68iRRvkXAnXssBuRUL9bNA=; b=SkAzmMulorZFpwV/DFLwRXKOdkuaGNVBBxl3U0CbA5IIyUJnR2o06Qtur4RTXRNjKP BkEUE0MPKFj3vYBoiK7SClx/MZjVhmwknwpCZ5v3+ODsAmPvGXy7TCDMCafh8HtbOtq9 h0e/Er+Y5WLlIdboVWbIV+U4LdiExz1L3AQfk/mkdeOnUUwERADwpjQRsXcR2wmgFIg3 IcJz9BONPmY4PiAuJt78X1R5NhB3pqrhns9Dl4pxlEHCUWis3de9dlchfYAwSyz5Gvmq 3ee5gyFi+ETC0MeDg91aZER75plXl1S758KTbWOKEn7Vf7GflwXsterYkWU55w6BO5O0 BvZQ== X-Gm-Message-State: ABuFfogr8yWeqOB1VYQzEOeAYzaD5gqwhroV17g+HX4TPv3FCT+sajRA 7t3Haddq46KtUyXdCz0zKl9RRooJA+4= X-Google-Smtp-Source: ACcGV63h1iNZ7fxvunwwyHTIaWGG53cLfP5pPEvlstrSNuJriKNlP8rdABTlrTL+0a3ktFJzIGoUgw== X-Received: by 2002:a63:9712:: with SMTP id n18-v6mr2865573pge.182.1539291131780; Thu, 11 Oct 2018 13:52:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:51:48 -0700 Message-Id: <20181011205206.3552-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::534 Subject: [Qemu-devel] [PATCH 02/20] target/arm: Don't call tcg_clear_temp_count X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is done generically in translator_loop. Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/translate-a64.c | 1 - target/arm/translate.c | 1 - 2 files changed, 2 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 76b5ca3606..ac9723c1b9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13899,7 +13899,6 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, =20 static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu) { - tcg_clear_temp_count(); } =20 static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) diff --git a/target/arm/translate.c b/target/arm/translate.c index 426db7828a..736880ee71 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12701,7 +12701,6 @@ static void arm_tr_tb_start(DisasContextBase *dcbas= e, CPUState *cpu) tcg_gen_movi_i32(tmp, 0); store_cpu_field(tmp, condexec_bits); } - tcg_clear_temp_count(); } =20 static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539291453552577.4578308338545; Thu, 11 Oct 2018 13:57:33 -0700 (PDT) Received: from localhost ([::1]:37091 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAi1U-0001qm-Fr for importer@patchew.org; Thu, 11 Oct 2018 16:57:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45127) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhwn-0006pt-Me for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAhwl-0005vB-Dg for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:41 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:47047) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAhwl-0003KD-03 for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:39 -0400 Received: by mail-pf1-x441.google.com with SMTP id r64-v6so4992246pfb.13 for ; Thu, 11 Oct 2018 13:52:14 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=q276Cj00zT1iWakpZyECyDDZxS4UysE8ylkjRlgyrFE=; b=JgMd/8x1tjrHcSPrQc1JbAsB1y4PmXc2xv3RfatAVzgvR/rhv0NRXAFqZagywdTMHN xaGUkKF2r/niEJz88gYwav7LOux9R13pTWuKh2r+G5clKT0DT5E+7z4KGyDLUw2rDV0g /ANiLAU+hbY48spf0McTkHVlCItl5asfMaWxA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q276Cj00zT1iWakpZyECyDDZxS4UysE8ylkjRlgyrFE=; b=LLpFa1JXHVfMGEoatmXwFDnGizJFTsMcFY8cD+vZMPUcd+gHiHFoyVOudS2BTbDE1Q 4UCOh7y0jQwDe/iPNtkG51LizUOKpmtuLfCx7zBIO5g0v7s0LMVs7uA8OnV3PGtZUqIq iaI2ctlokWbM0Na5Gaf3naX2FuGXGqKxr4XRakFDDeBs69hSmjLsCZFAcAWnkygFI5+U DkCHHZZouyabKObzwHR7M/6i4wx0chchwvSv0qRs/Pmuag98NPZF2V6gfN0sxvylHM43 L2oeIygC6fdI0co33fBgd9Ny6/CvWY72Hkr0oxJd1xeOZ8BrLNTGmAz/2SFqxCQLQdzj 1mUw== X-Gm-Message-State: ABuFfogdYPumoM/fcyU0OIZquTJVGGK6HZa7h8kUhcLzTgk7AYvt3Gr8 9kVt+LwUrp5y7BT3JZs5m94eDY0lP5U= X-Google-Smtp-Source: ACcGV606K61qW7Wj10wKxAuYvTrg0RmQ2/WJRXNUwZ2S+GlYxtS0RopSotlshJ1FZbQgS3+rjDTdFw== X-Received: by 2002:a63:78cc:: with SMTP id t195-v6mr2804610pgc.329.1539291133159; Thu, 11 Oct 2018 13:52:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:51:49 -0700 Message-Id: <20181011205206.3552-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 03/20] target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 28 +++------------------------- 1 file changed, 3 insertions(+), 25 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ac9723c1b9..fff99ca303 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3217,36 +3217,14 @@ static void disas_ldst_single_struct(DisasContext *= s, uint32_t insn) for (xs =3D 0; xs < selem; xs++) { if (replicate) { /* Load and replicate to all elements */ - uint64_t mulconst; TCGv_i64 tcg_tmp =3D tcg_temp_new_i64(); =20 tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), s->be_data + scale); - switch (scale) { - case 0: - mulconst =3D 0x0101010101010101ULL; - break; - case 1: - mulconst =3D 0x0001000100010001ULL; - break; - case 2: - mulconst =3D 0x0000000100000001ULL; - break; - case 3: - mulconst =3D 0; - break; - default: - g_assert_not_reached(); - } - if (mulconst) { - tcg_gen_muli_i64(tcg_tmp, tcg_tmp, mulconst); - } - write_vec_element(s, tcg_tmp, rt, 0, MO_64); - if (is_q) { - write_vec_element(s, tcg_tmp, rt, 1, MO_64); - } + tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt), + (is_q + 1) * 8, vec_full_reg_size(s), + tcg_tmp); tcg_temp_free_i64(tcg_tmp); - clear_vec_high(s, is_q, rt); } else { /* Load/store one element per register */ if (is_load) { --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539291935533194.29401872344283; Thu, 11 Oct 2018 14:05:35 -0700 (PDT) Received: from localhost ([::1]:37132 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAi9B-000828-H7 for importer@patchew.org; Thu, 11 Oct 2018 17:05:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45197) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhwq-0006sC-2O for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAhwm-0005zz-72 for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:43 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:40800) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAhwl-0003SW-Mi for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:39 -0400 Received: by mail-pf1-x443.google.com with SMTP id s5-v6so5005658pfj.7 for ; Thu, 11 Oct 2018 13:52:15 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Smv7/EDiE77NiuFaVj/NIlvKHR40VLp0vXf5RsdOZ4o=; b=ArsT5d70H3y9YxQJvWJMKD5lyxLZBdthWvekNUo3yoUPzC7GnsoIjhE6Gz+w4gXVIh 5QAOtiTHlz49Yzpm4PiUCYGVyFJ67NWOpMtxcITgX8hUZ+g+rSBss64JGm6KyeS3VRs+ wjWd3rKX23RkzDzQAjjQYjspqK+Hnycate/Y8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Smv7/EDiE77NiuFaVj/NIlvKHR40VLp0vXf5RsdOZ4o=; b=snMNOb4F9Q9AhojIPCUzaQiQSQaRlYMvP77xPHT9m1rZqzJwghkGsWrXh7pghY87gK +SDcynnawSBeILnK6nDfVzv6ZGZfDztfpFuzJJJz8XDImtJ+ov/dXExGa++QnV0GpfL3 atcboTqI646Wjb+FC+KICfxrwO1AnZWXXYl4U/aGXgAVfFB8ujeZvQy9Ksq/jhimyObD 4iQW4of7xGg/g+vQnRTRz43zEpPN8m4MkE2X0MZVqnfqo4Wbv0Pf3WbWbvYs4e2lnsUV xe4evY36xgn0Anfn0VN9JrV5MTdW40rOmRYegHf+/vya5bvZDuPTcvK95qbmsVK1nAoB VwbQ== X-Gm-Message-State: ABuFfoh7SOSSSz0DwmBEkpDW+qlMGXYuq5RuMjqYDhMfQ+9VEJNfHiHu 6uKW8RJInbDSgZZ2hI7qeElWOmg2VmE= X-Google-Smtp-Source: ACcGV62FK7GyOVQTD9G6dj/vRJdscU80s5Q9w9+GWlu/kb9aRJF2lv9sUBnnSp1kjYILSSIxceYTvA== X-Received: by 2002:aa7:86cc:: with SMTP id h12-v6mr3054589pfo.58.1539291134647; Thu, 11 Oct 2018 13:52:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:51:50 -0700 Message-Id: <20181011205206.3552-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 04/20] target/arm: Promote consecutive memory ops for aa64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For a sequence of loads or stores from a single register, little-endian operations can be promoted to an 8-byte op. This can reduce the number of operations by a factor of 8. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 66 +++++++++++++++++++++++--------------- 1 file changed, 40 insertions(+), 26 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fff99ca303..2f4041462e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1200,25 +1200,23 @@ static void write_vec_element_i32(DisasContext *s, = TCGv_i32 tcg_src, =20 /* Store from vector register to memory */ static void do_vec_st(DisasContext *s, int srcidx, int element, - TCGv_i64 tcg_addr, int size) + TCGv_i64 tcg_addr, int size, TCGMemOp endian) { - TCGMemOp memop =3D s->be_data + size; TCGv_i64 tcg_tmp =3D tcg_temp_new_i64(); =20 read_vec_element(s, tcg_tmp, srcidx, element, size); - tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop); + tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size= ); =20 tcg_temp_free_i64(tcg_tmp); } =20 /* Load from memory to vector register */ static void do_vec_ld(DisasContext *s, int destidx, int element, - TCGv_i64 tcg_addr, int size) + TCGv_i64 tcg_addr, int size, TCGMemOp endian) { - TCGMemOp memop =3D s->be_data + size; TCGv_i64 tcg_tmp =3D tcg_temp_new_i64(); =20 - tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop); + tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size= ); write_vec_element(s, tcg_tmp, destidx, element, size); =20 tcg_temp_free_i64(tcg_tmp); @@ -3013,9 +3011,10 @@ static void disas_ldst_multiple_struct(DisasContext = *s, uint32_t insn) bool is_postidx =3D extract32(insn, 23, 1); bool is_q =3D extract32(insn, 30, 1); TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes; + TCGMemOp endian =3D s->be_data; =20 - int ebytes =3D 1 << size; - int elements =3D (is_q ? 128 : 64) / (8 << size); + int ebytes; /* bytes per element */ + int elements; /* elements per vector */ int rpt; /* num iterations */ int selem; /* structure elements */ int r; @@ -3074,6 +3073,20 @@ static void disas_ldst_multiple_struct(DisasContext = *s, uint32_t insn) gen_check_sp_alignment(s); } =20 + /* For our purposes, bytes are always little-endian. */ + if (size =3D=3D 0) { + endian =3D MO_LE; + } + + /* Consecutive little-endian elements from a single register + * can be promoted to a larger little-endian operation. + */ + if (selem =3D=3D 1 && endian =3D=3D MO_LE) { + size =3D 3; + } + ebytes =3D 1 << size; + elements =3D (is_q ? 16 : 8) / ebytes; + tcg_rn =3D cpu_reg_sp(s, rn); tcg_addr =3D tcg_temp_new_i64(); tcg_gen_mov_i64(tcg_addr, tcg_rn); @@ -3082,32 +3095,33 @@ static void disas_ldst_multiple_struct(DisasContext= *s, uint32_t insn) for (r =3D 0; r < rpt; r++) { int e; for (e =3D 0; e < elements; e++) { - int tt =3D (rt + r) % 32; int xs; for (xs =3D 0; xs < selem; xs++) { + int tt =3D (rt + r + xs) % 32; if (is_store) { - do_vec_st(s, tt, e, tcg_addr, size); + do_vec_st(s, tt, e, tcg_addr, size, endian); } else { - do_vec_ld(s, tt, e, tcg_addr, size); - - /* For non-quad operations, setting a slice of the low - * 64 bits of the register clears the high 64 bits (in - * the ARM ARM pseudocode this is implicit in the fact - * that 'rval' is a 64 bit wide variable). - * For quad operations, we might still need to zero the - * high bits of SVE. We optimize by noticing that we = only - * need to do this the first time we touch a register. - */ - if (e =3D=3D 0 && (r =3D=3D 0 || xs =3D=3D selem - 1))= { - clear_vec_high(s, is_q, tt); - } + do_vec_ld(s, tt, e, tcg_addr, size, endian); } tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes); - tt =3D (tt + 1) % 32; } } } =20 + if (!is_store) { + /* For non-quad operations, setting a slice of the low + * 64 bits of the register clears the high 64 bits (in + * the ARM ARM pseudocode this is implicit in the fact + * that 'rval' is a 64 bit wide variable). + * For quad operations, we might still need to zero the + * high bits of SVE. + */ + for (r =3D 0; r < rpt * selem; r++) { + int tt =3D (rt + r) % 32; + clear_vec_high(s, is_q, tt); + } + } + if (is_postidx) { int rm =3D extract32(insn, 16, 5); if (rm =3D=3D 31) { @@ -3228,9 +3242,9 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) } else { /* Load/store one element per register */ if (is_load) { - do_vec_ld(s, rt, index, tcg_addr, scale); + do_vec_ld(s, rt, index, tcg_addr, scale, s->be_data); } else { - do_vec_st(s, rt, index, tcg_addr, scale); + do_vec_st(s, rt, index, tcg_addr, scale, s->be_data); } } tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes); --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539291453930767.86015465243; Thu, 11 Oct 2018 13:57:33 -0700 (PDT) Received: from localhost ([::1]:37090 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAi1U-0001p8-L2 for importer@patchew.org; Thu, 11 Oct 2018 16:57:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45118) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhwn-0006pk-K1 for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAhwl-0005w9-HO for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:41 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:37117) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAhwl-0003ah-56 for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:39 -0400 Received: by mail-pg1-x544.google.com with SMTP id c10-v6so4737621pgq.4 for ; Thu, 11 Oct 2018 13:52:17 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Eh9OlKYTt5u3h4AcWHRP0whFwqAPQbJfzAwKMgaXlLg=; b=bHNcHRx4MeSky8rNKnNt4NE3SXN+qWbOCmobG6MZqJTp01f5gVeZXxs/nVCaCqGt4L J6vW1ua1Bo1uAi/StVRYrblfLkjvGYiivvVxqV+NdCFw56Dn4QPxXR2mc9ZAVx1xF2Lg eVodsZIyMRJvu4Ngao5XWIV5k/SN6YWVkJkNc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Eh9OlKYTt5u3h4AcWHRP0whFwqAPQbJfzAwKMgaXlLg=; b=pOn7myfGUL+wfTBBPcjxIjXoGs2YKFu1Oei8wdNc7W67UR3N+X6imrccHDNtwzuVY6 IMJJa6OXggP+q/iF/UbmPZTFYyVqgB6DBYyL2+Djc2QG1BZnK3xebfBRequhiI3C5VSP E1WIUF7W3Ey8rTBfHGpzSq9D7U/KPQ4LLp92cT0b7sE7EYjVZXAhTZP8m644Q0O26mQa nJ/uG+8w343PLWCKHMq6y7T2DnsQIQZrlWCrdUz7XpC2z4elqHnkg7ykWud2TijUUN4r tZxkXjYBc1Xbk6K9IHVLLlxvI5mjLzRGLNG2S7aMsCu5Wal2UilzwcA7a33s/FUWAiHs 9WkA== X-Gm-Message-State: ABuFfojTbWCV9EYYQODNT05d8ktAYT3gqkiVu0cCWIBRQexSunVeJwid ddu+9b3IVT8hIiKoHcQq11ZU1ZOgmQw= X-Google-Smtp-Source: ACcGV60d1A8omNVRxbXHSilnFn3WZW/OXDoxXA1wkpgmobY27+nYOiAIGWqSsRyAwF1xAkTLomL4/Q== X-Received: by 2002:a62:64d5:: with SMTP id y204-v6mr3072528pfb.187.1539291135997; Thu, 11 Oct 2018 13:52:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:51:51 -0700 Message-Id: <20181011205206.3552-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 05/20] target/arm: Mark some arrays const X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/translate.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 736880ee71..d59ffa1c67 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -72,7 +72,7 @@ static TCGv_i64 cpu_F0d, cpu_F1d; =20 #include "exec/gen-icount.h" =20 -static const char *regnames[] =3D +static const char * const regnames[] =3D { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; =20 @@ -4907,7 +4907,7 @@ static struct { int nregs; int interleave; int spacing; -} neon_ls_element_type[11] =3D { +} const neon_ls_element_type[11] =3D { {4, 4, 1}, {4, 4, 2}, {4, 1, 1}, @@ -13089,7 +13089,7 @@ void gen_intermediate_code(CPUState *cpu, Translati= onBlock *tb) translator_loop(ops, &dc.base, cpu, tb); } =20 -static const char *cpu_mode_names[16] =3D { +static const char * const cpu_mode_names[16] =3D { "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt", "???", "???", "hyp", "und", "???", "???", "???", "sys" }; --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539291620931218.02692299532976; Thu, 11 Oct 2018 14:00:20 -0700 (PDT) Received: from localhost ([::1]:37106 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAi48-0004Cu-Jy for importer@patchew.org; Thu, 11 Oct 2018 17:00:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45145) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhwo-0006qV-Aw for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAhwl-0005wg-LH for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:42 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:43825) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAhwl-0003kq-7R for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:39 -0400 Received: by mail-pf1-x444.google.com with SMTP id p24-v6so4994676pff.10 for ; Thu, 11 Oct 2018 13:52:18 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YFQr/JNTa/QXkvyuZtso9GlnKeUMjxXJ1Iso8ke3tsU=; b=JvtRdgCEb6EhrzFeGlHZS40h4ZrJ+ZIi43MZHg0ggFMa+YdlPdVDrcxyjpD9KebvA1 MAg8Fl/PPMQPbIl8r7nyk5e6uPaSU1fNygB5lVDyhLu6ujOeCFaLgwm3KLRUKvA60iDl FzCHnODx9ulbKuZVg7fBaZCBDjRUmIWhvysGI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YFQr/JNTa/QXkvyuZtso9GlnKeUMjxXJ1Iso8ke3tsU=; b=tOw8eXBoU7CQVHU72ZZYyfGyxwX0qYAIm9oBF5wg/C8j8lOPmmIpFYhvyP0Y1g7mmJ c3M/qnkDjs46xOO+5v3YcTl40BcvA4xPDzTVGRSshsN/ONjihZmcPj3t4r5MNrKngXcU NpLNZsrNEiYVy4i+ZvBAtjX0HPQs0n7bb7iWzGeusI/qg0Gag87pI+hwSdLSxNCeNb4Z tfH17VclMnXoutCv2/wMSBkjseQghqeYCajfai8MJL3ezQS4YYm/OeMt0XLVL/JMRuq0 l66DTA9PKcMlFBWIm/gDXGBfUqtlOUWZtLVWBIHmKOgd9FyjL5zE8JBzouKL5wX36Bs/ 1lnA== X-Gm-Message-State: ABuFfoiJSGpjiGvvp6/IjHuUDrH9dLoqAt+0mR4ASabl3IpszJGb3uIq XDcSe/B0WdPLu1q+QFp7gpfG73eojzg= X-Google-Smtp-Source: ACcGV61SZUl4hK8iIqnaVLX3xXugqdd5pCUBcZY6L+uBAxQe+p1eSVxhoQyEBEUGwhuz19RFq8R2mA== X-Received: by 2002:a62:5251:: with SMTP id g78-v6mr3100667pfb.256.1539291137435; Thu, 11 Oct 2018 13:52:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:51:52 -0700 Message-Id: <20181011205206.3552-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 06/20] target/arm: Use gvec for NEON VDUP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Also introduces neon_element_offset to find the env offset of a specific element within a neon register. Signed-off-by: Richard Henderson --- target/arm/translate.c | 63 ++++++++++++++++++++++++------------------ 1 file changed, 36 insertions(+), 27 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d59ffa1c67..4ac526e298 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1585,6 +1585,25 @@ neon_reg_offset (int reg, int n) return vfp_reg_offset(0, sreg); } =20 +/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE, + * where 0 is the least significant end of the register. + */ +static inline long +neon_element_offset(int reg, int element, TCGMemOp size) +{ + int element_size =3D 1 << size; + int ofs =3D element * element_size; +#ifdef HOST_WORDS_BIGENDIAN + /* Calculate the offset assuming fully little-endian, + * then XOR to account for the order of the 8-byte units. + */ + if (element_size < 8) { + ofs ^=3D 8 - element_size; + } +#endif + return neon_reg_offset(reg, 0) + ofs; +} + static TCGv_i32 neon_load_reg(int reg, int pass) { TCGv_i32 tmp =3D tcg_temp_new_i32(); @@ -3432,17 +3451,10 @@ static int disas_vfp_insn(DisasContext *s, uint32_t= insn) tmp =3D load_reg(s, rd); if (insn & (1 << 23)) { /* VDUP */ - if (size =3D=3D 0) { - gen_neon_dup_u8(tmp, 0); - } else if (size =3D=3D 1) { - gen_neon_dup_low16(tmp); - } - for (n =3D 0; n <=3D pass * 2; n++) { - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp2, tmp); - neon_store_reg(rn, n, tmp2); - } - neon_store_reg(rn, n, tmp); + int vec_size =3D pass ? 16 : 8; + tcg_gen_gvec_dup_i32(size, neon_reg_offset(rn, 0), + vec_size, vec_size, tmp); + tcg_temp_free_i32(tmp); } else { /* VMOV */ switch (size) { @@ -7755,28 +7767,25 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) tcg_temp_free_i32(tmp); } else if ((insn & 0x380) =3D=3D 0) { /* VDUP */ + int element; + TCGMemOp size; + if ((insn & (7 << 16)) =3D=3D 0 || (q && (rd & 1))) { return 1; } - if (insn & (1 << 19)) { - tmp =3D neon_load_reg(rm, 1); - } else { - tmp =3D neon_load_reg(rm, 0); - } if (insn & (1 << 16)) { - gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8); + size =3D MO_8; + element =3D (insn >> 17) & 7; } else if (insn & (1 << 17)) { - if ((insn >> 18) & 1) - gen_neon_dup_high16(tmp); - else - gen_neon_dup_low16(tmp); + size =3D MO_16; + element =3D (insn >> 18) & 3; + } else { + size =3D MO_32; + element =3D (insn >> 19) & 1; } - for (pass =3D 0; pass < (q ? 4 : 2); pass++) { - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp2, tmp); - neon_store_reg(rd, pass, tmp2); - } - tcg_temp_free_i32(tmp); + tcg_gen_gvec_dup_mem(size, neon_reg_offset(rd, 0), + neon_element_offset(rm, element, size= ), + q ? 16 : 8, q ? 16 : 8); } else { return 1; } --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539291771634775.4155870011375; Thu, 11 Oct 2018 14:02:51 -0700 (PDT) Received: from localhost ([::1]:37122 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAi6c-00067Y-Iw for importer@patchew.org; Thu, 11 Oct 2018 17:02:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45177) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhwp-0006rX-Br for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAhwm-00060Z-7r for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:43 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:46461) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAhwl-0003tU-NU for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:39 -0400 Received: by mail-pf1-x430.google.com with SMTP id r64-v6so4992364pfb.13 for ; Thu, 11 Oct 2018 13:52:20 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tj0Mk6BZv5h6kitrvfOx4xu0tRJ4I4R9MOqUXqh/uhw=; b=cPyiYcLavaFrsK7bYRwsF5TaIvdZtXbwAOluLwBXmjJ+lw5R39f+AfwclW4qTxQC/t uFLSmgZMn1/Eazbx3p3yR4P04CU13aF22dHMrXXk+G/TbTto9Dbi0hY3VDECoMoinYUZ jOIg1501Dx0+o6ATvvltzpvjnQDLVUgi0WQtg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tj0Mk6BZv5h6kitrvfOx4xu0tRJ4I4R9MOqUXqh/uhw=; b=OJFUaFQIEZ616HVkPqe7XfR8IA5+tAhFLSmCRctDE51SdcyjRxzrddI+dqBX87nvRI qVXIOKwFanqZA6tk6O27h1dqWhYV042FTfcAT8/1i5nzKLZGC6RLk8dpP2USW3qHgGz4 1ElKJSILh0hJklhNddg9K7b9MH+D8w7OqTkFiUe32FZUU8m08bhhTRp9ThKQzipEPB7Q h4bTdADsJjR3ZkQxn93Qx4FLjDfKubO0VpDRLnB+u3r4LvcxgmwOAXaifTReVHwo8EIK LmNAwGErol9FYHE/WBVUHhXuzjsuAw/6CjahxEaroPrVA7OuuuyuBOtFakG2vXvh6r4F A6PA== X-Gm-Message-State: ABuFfoihXO+EnZeShac9nYvtrT5ZiynadXYLwu3cRwy6Aj7hXCrcDOAY Wxaj3yQY/M9k4gpxZNEEAhjFGX8in5E= X-Google-Smtp-Source: ACcGV62pcF4Lhl+yHSpHpeEtsp2wC3EeDbuCa623igE/FtGNxilk+FEfKjZVrv7afEmqzXJ6u3PCTw== X-Received: by 2002:a62:1551:: with SMTP id 78-v6mr3086771pfv.178.1539291138759; Thu, 11 Oct 2018 13:52:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:51:53 -0700 Message-Id: <20181011205206.3552-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::430 Subject: [Qemu-devel] [PATCH 07/20] target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate.c | 67 ++++++++++++++++++++++++------------------ 1 file changed, 39 insertions(+), 28 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4ac526e298..109689a286 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6641,7 +6641,8 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) return 1; } } else { /* (insn & 0x00380080) =3D=3D 0 */ - int invert; + int invert, reg_ofs, vec_size; + if (q && (rd & 1)) { return 1; } @@ -6681,8 +6682,9 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) break; case 14: imm |=3D (imm << 8) | (imm << 16) | (imm << 24); - if (invert) + if (invert) { imm =3D ~imm; + } break; case 15: if (invert) { @@ -6692,36 +6694,45 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); break; } - if (invert) + if (invert) { imm =3D ~imm; + } =20 - for (pass =3D 0; pass < (q ? 4 : 2); pass++) { - if (op & 1 && op < 12) { - tmp =3D neon_load_reg(rd, pass); - if (invert) { - /* The immediate value has already been inverted, = so - BIC becomes AND. */ - tcg_gen_andi_i32(tmp, tmp, imm); - } else { - tcg_gen_ori_i32(tmp, tmp, imm); - } + reg_ofs =3D neon_reg_offset(rd, 0); + vec_size =3D q ? 16 : 8; + + if (op & 1 && op < 12) { + if (invert) { + /* The immediate value has already been inverted, + * so BIC becomes AND. + */ + tcg_gen_gvec_andi(MO_32, reg_ofs, reg_ofs, imm, + vec_size, vec_size); } else { - /* VMOV, VMVN. */ - tmp =3D tcg_temp_new_i32(); - if (op =3D=3D 14 && invert) { - int n; - uint32_t val; - val =3D 0; - for (n =3D 0; n < 4; n++) { - if (imm & (1 << (n + (pass & 1) * 4))) - val |=3D 0xff << (n * 8); - } - tcg_gen_movi_i32(tmp, val); - } else { - tcg_gen_movi_i32(tmp, imm); - } + tcg_gen_gvec_ori(MO_32, reg_ofs, reg_ofs, imm, + vec_size, vec_size); + } + } else { + /* VMOV, VMVN. */ + if (op =3D=3D 14 && invert) { + TCGv_i64 t64 =3D tcg_temp_new_i64(); + + for (pass =3D 0; pass <=3D q; ++pass) { + uint64_t val =3D 0; + int n; + + for (n =3D 0; n < 8; n++) { + if (imm & (1 << (n + pass * 8))) { + val |=3D 0xffull << (n * 8); + } + } + tcg_gen_movi_i64(t64, val); + neon_store_reg64(t64, rd + pass); + } + tcg_temp_free_i64(t64); + } else { + tcg_gen_gvec_dup32i(reg_ofs, vec_size, vec_size, imm); } - neon_store_reg(rd, pass, tmp); } } } else { /* (insn & 0x00800010 =3D=3D 0x00800000) */ --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539291541431552.9828122494788; Thu, 11 Oct 2018 13:59:01 -0700 (PDT) Received: from localhost ([::1]:37093 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAi2o-0002yT-En for importer@patchew.org; Thu, 11 Oct 2018 16:58:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45267) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhws-0006ux-KO for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAhwm-00060d-8W for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:46 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:39342) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAhwl-00043n-Ks for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:39 -0400 Received: by mail-pf1-x432.google.com with SMTP id c25-v6so5005451pfe.6 for ; Thu, 11 Oct 2018 13:52:21 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hJD19gJ8na3mOz8QxC2v9IPsBo/TKnufUX231NVMcbE=; b=BpM0aBv4wJqkY5ytq06QAHN8EWr7ruAFyeqR1PZrlCqnwdf2/viToBcLMXUfrEOBUs 32bIuXvZJ0u6jZkYeQr1K08GWiGZmA9DYPiMcRI4qruGpEc4JPiVwsuZ8SEvjnHn8E3f r/vf/MyYVZLep7UvGDJ5g7iqg3TOYkN4Hk0E0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hJD19gJ8na3mOz8QxC2v9IPsBo/TKnufUX231NVMcbE=; b=C2TgXXHWiXTBWpAAwsH6kmx7pD+mLz+ODvNtR2vnk6IuKADtZ4X0RB0c9lWsOy1Uyg Ux5YUWO8TNvvUzJQqaF6MawZY/KH6guniW/xVycHCRdhIZIg86lJoPkS4j71pThGiMUw f8NN6v1DlgwEyiXvIOl5ptd/VjHfd4iZx6jzZK5leZKp5qdA03onwrFOs9pSHEYgug5z u0QNqmK4SQQUk2gnc/qvVpVrTF/eBZ3mD4+AqM3FXgOXR5ZYUvbvO2UUOk/+AeeDWd9q Ccd+U0wJX4saEAcCjl6fwoqMd5q+vHJi9Ut1xQRnhBvPo9JpjKTb5LXzXh+cUD/WyPA8 QDyA== X-Gm-Message-State: ABuFfoigIq81UQLIHbqytmU07r8Lz3pET0u/Usxwjtuc/j+njvQQxGSk EQ3Dg5UuAB4g/XDIVdihw6tnd5zlkas= X-Google-Smtp-Source: ACcGV60ROo4m94S2om9mB0xQMZpSDC9EKaqGKADcF2loj2VRmvK8U0cYWVef9iYVgoAPPAGGlWzxRQ== X-Received: by 2002:a63:e601:: with SMTP id g1-v6mr2852980pgh.290.1539291140322; Thu, 11 Oct 2018 13:52:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:51:54 -0700 Message-Id: <20181011205206.3552-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::432 Subject: [Qemu-devel] [PATCH 08/20] target/arm: Use gvec for NEON_3R_LOGIC insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move expanders for VBSL, VBIT, and VBIF from translate-a64.c. Signed-off-by: Richard Henderson --- target/arm/translate.h | 6 +- target/arm/translate-a64.c | 61 -------------- target/arm/translate.c | 162 +++++++++++++++++++++++++++---------- 3 files changed, 123 insertions(+), 106 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index ad911de98c..7cc2685104 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -191,6 +191,11 @@ static inline TCGv_i32 get_ahp_flag(void) return ret; } =20 +/* Vector operations shared between ARM and AArch64. */ +extern const GVecGen3 bsl_op; +extern const GVecGen3 bit_op; +extern const GVecGen3 bif_op; + #define FORWARD_FEATURE(NAME) \ static inline bool aa32_dc_feature_##NAME(DisasContext *dc) \ { return aa32_feature_##NAME(dc->cpu); } @@ -209,5 +214,4 @@ FORWARD_FEATURE(dp) FORWARD_FEATURE(fp16_arith) =20 #undef FORWARD_FEATURE - #endif /* TARGET_ARM_TRANSLATE_H */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2f4041462e..a115546a6a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10392,70 +10392,9 @@ static void disas_simd_three_reg_diff(DisasContext= *s, uint32_t insn) } } =20 -static void gen_bsl_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) -{ - tcg_gen_xor_i64(rn, rn, rm); - tcg_gen_and_i64(rn, rn, rd); - tcg_gen_xor_i64(rd, rm, rn); -} - -static void gen_bit_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) -{ - tcg_gen_xor_i64(rn, rn, rd); - tcg_gen_and_i64(rn, rn, rm); - tcg_gen_xor_i64(rd, rd, rn); -} - -static void gen_bif_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) -{ - tcg_gen_xor_i64(rn, rn, rd); - tcg_gen_andc_i64(rn, rn, rm); - tcg_gen_xor_i64(rd, rd, rn); -} - -static void gen_bsl_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec = rm) -{ - tcg_gen_xor_vec(vece, rn, rn, rm); - tcg_gen_and_vec(vece, rn, rn, rd); - tcg_gen_xor_vec(vece, rd, rm, rn); -} - -static void gen_bit_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec = rm) -{ - tcg_gen_xor_vec(vece, rn, rn, rd); - tcg_gen_and_vec(vece, rn, rn, rm); - tcg_gen_xor_vec(vece, rd, rd, rn); -} - -static void gen_bif_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec = rm) -{ - tcg_gen_xor_vec(vece, rn, rn, rd); - tcg_gen_andc_vec(vece, rn, rn, rm); - tcg_gen_xor_vec(vece, rd, rd, rn); -} - /* Logic op (opcode =3D=3D 3) subgroup of C3.6.16. */ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) { - static const GVecGen3 bsl_op =3D { - .fni8 =3D gen_bsl_i64, - .fniv =3D gen_bsl_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, - .load_dest =3D true - }; - static const GVecGen3 bit_op =3D { - .fni8 =3D gen_bit_i64, - .fniv =3D gen_bit_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, - .load_dest =3D true - }; - static const GVecGen3 bif_op =3D { - .fni8 =3D gen_bif_i64, - .fniv =3D gen_bif_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, - .load_dest =3D true - }; - int rd =3D extract32(insn, 0, 5); int rn =3D extract32(insn, 5, 5); int rm =3D extract32(insn, 16, 5); diff --git a/target/arm/translate.c b/target/arm/translate.c index 109689a286..4ab9f69b01 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5262,14 +5262,6 @@ static int disas_neon_ls_insn(DisasContext *s, uint3= 2_t insn) return 0; } =20 -/* Bitwise select. dest =3D c ? t : f. Clobbers T and F. */ -static void gen_neon_bsl(TCGv_i32 dest, TCGv_i32 t, TCGv_i32 f, TCGv_i32 c) -{ - tcg_gen_and_i32(t, t, c); - tcg_gen_andc_i32(f, f, c); - tcg_gen_or_i32(dest, t, f); -} - static inline void gen_neon_narrow(int size, TCGv_i32 dest, TCGv_i64 src) { switch (size) { @@ -5712,6 +5704,73 @@ static int do_v81_helper(DisasContext *s, gen_helper= _gvec_3_ptr *fn, return 1; } =20 +/* + * Expanders for VBitOps_VBIF, VBIT, VBSL. + */ +static void gen_bsl_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) +{ + tcg_gen_xor_i64(rn, rn, rm); + tcg_gen_and_i64(rn, rn, rd); + tcg_gen_xor_i64(rd, rm, rn); +} + +static void gen_bit_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) +{ + tcg_gen_xor_i64(rn, rn, rd); + tcg_gen_and_i64(rn, rn, rm); + tcg_gen_xor_i64(rd, rd, rn); +} + +static void gen_bif_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) +{ + tcg_gen_xor_i64(rn, rn, rd); + tcg_gen_andc_i64(rn, rn, rm); + tcg_gen_xor_i64(rd, rd, rn); +} + +static void gen_bsl_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec = rm) +{ + tcg_gen_xor_vec(vece, rn, rn, rm); + tcg_gen_and_vec(vece, rn, rn, rd); + tcg_gen_xor_vec(vece, rd, rm, rn); +} + +static void gen_bit_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec = rm) +{ + tcg_gen_xor_vec(vece, rn, rn, rd); + tcg_gen_and_vec(vece, rn, rn, rm); + tcg_gen_xor_vec(vece, rd, rd, rn); +} + +static void gen_bif_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec = rm) +{ + tcg_gen_xor_vec(vece, rn, rn, rd); + tcg_gen_andc_vec(vece, rn, rn, rm); + tcg_gen_xor_vec(vece, rd, rd, rn); +} + +const GVecGen3 bsl_op =3D { + .fni8 =3D gen_bsl_i64, + .fniv =3D gen_bsl_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .load_dest =3D true +}; + +const GVecGen3 bit_op =3D { + .fni8 =3D gen_bit_i64, + .fniv =3D gen_bit_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .load_dest =3D true +}; + +const GVecGen3 bif_op =3D { + .fni8 =3D gen_bif_i64, + .fniv =3D gen_bif_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .load_dest =3D true +}; + + /* Translate a NEON data processing instruction. Return nonzero if the instruction is invalid. We process data in a mixture of 32-bit and 64-bit chunks. @@ -5721,13 +5780,14 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) { int op; int q; - int rd, rn, rm; + int rd, rn, rm, rd_ofs, rn_ofs, rm_ofs; int size; int shift; int pass; int count; int pairwise; int u; + int vec_size; uint32_t imm, mask; TCGv_i32 tmp, tmp2, tmp3, tmp4, tmp5; TCGv_ptr ptr1, ptr2, ptr3; @@ -5751,6 +5811,11 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) VFP_DREG_N(rn, insn); VFP_DREG_M(rm, insn); size =3D (insn >> 20) & 3; + vec_size =3D q ? 16 : 8; + rd_ofs =3D neon_reg_offset(rd, 0); + rn_ofs =3D neon_reg_offset(rn, 0); + rm_ofs =3D neon_reg_offset(rm, 0); + if ((insn & (1 << 23)) =3D=3D 0) { /* Three register same length. */ op =3D ((insn >> 7) & 0x1e) | ((insn >> 4) & 1); @@ -5841,8 +5906,51 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) q, rd, rn, rm); } return 1; + + case NEON_3R_LOGIC: /* Logic ops. */ + switch ((u << 2) | size) { + case 0: /* VAND */ + tcg_gen_gvec_and(0, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); + break; + case 1: /* VBIC */ + tcg_gen_gvec_andc(0, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); + break; + case 2: + if (rn =3D=3D rm) { + /* VMOV */ + tcg_gen_gvec_mov(0, rd_ofs, rn_ofs, vec_size, vec_size= ); + } else { + /* VORR */ + tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); + } + break; + case 3: /* VORN */ + tcg_gen_gvec_orc(0, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); + break; + case 4: /* VEOR */ + tcg_gen_gvec_xor(0, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); + break; + case 5: /* VBSL */ + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size, &bsl_op); + break; + case 6: /* VBIT */ + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size, &bit_op); + break; + case 7: /* VBIF */ + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size, &bif_op); + break; + } + return 0; } - if (size =3D=3D 3 && op !=3D NEON_3R_LOGIC) { + if (size =3D=3D 3) { /* 64-bit element instructions. */ for (pass =3D 0; pass < (q ? 2 : 1); pass++) { neon_load_reg64(cpu_V0, rn + pass); @@ -6000,40 +6108,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) case NEON_3R_VRHADD: GEN_NEON_INTEGER_OP(rhadd); break; - case NEON_3R_LOGIC: /* Logic ops. */ - switch ((u << 2) | size) { - case 0: /* VAND */ - tcg_gen_and_i32(tmp, tmp, tmp2); - break; - case 1: /* BIC */ - tcg_gen_andc_i32(tmp, tmp, tmp2); - break; - case 2: /* VORR */ - tcg_gen_or_i32(tmp, tmp, tmp2); - break; - case 3: /* VORN */ - tcg_gen_orc_i32(tmp, tmp, tmp2); - break; - case 4: /* VEOR */ - tcg_gen_xor_i32(tmp, tmp, tmp2); - break; - case 5: /* VBSL */ - tmp3 =3D neon_load_reg(rd, pass); - gen_neon_bsl(tmp, tmp, tmp2, tmp3); - tcg_temp_free_i32(tmp3); - break; - case 6: /* VBIT */ - tmp3 =3D neon_load_reg(rd, pass); - gen_neon_bsl(tmp, tmp, tmp3, tmp2); - tcg_temp_free_i32(tmp3); - break; - case 7: /* VBIF */ - tmp3 =3D neon_load_reg(rd, pass); - gen_neon_bsl(tmp, tmp3, tmp, tmp2); - tcg_temp_free_i32(tmp3); - break; - } - break; case NEON_3R_VHSUB: GEN_NEON_INTEGER_OP(hsub); break; --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15392914524372.9290804364889027; Thu, 11 Oct 2018 13:57:32 -0700 (PDT) Received: from localhost ([::1]:37089 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAi1T-0001om-8P for importer@patchew.org; Thu, 11 Oct 2018 16:57:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45007) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhwj-0006lw-EN for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAhwh-0005Xf-5j for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:37 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:43486) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAhwf-0004EA-5W for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:33 -0400 Received: by mail-pg1-x532.google.com with SMTP id 80-v6so4721210pgh.10 for ; Thu, 11 Oct 2018 13:52:23 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::532 Subject: [Qemu-devel] [PATCH 09/20] target/arm: Use gvec for NEON_3R_VADD_VSUB insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate.c | 29 ++++++++++------------------- 1 file changed, 10 insertions(+), 19 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4ab9f69b01..4dcd7123e9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5949,6 +5949,16 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) break; } return 0; + + case NEON_3R_VADD_VSUB: + if (u) { + tcg_gen_gvec_sub(size, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); + } else { + tcg_gen_gvec_add(size, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); + } + return 0; } if (size =3D=3D 3) { /* 64-bit element instructions. */ @@ -6006,13 +6016,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) cpu_V1, cpu_V0); } break; - case NEON_3R_VADD_VSUB: - if (u) { - tcg_gen_sub_i64(CPU_V001); - } else { - tcg_gen_add_i64(CPU_V001); - } - break; default: abort(); } @@ -6147,18 +6150,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) tmp2 =3D neon_load_reg(rd, pass); gen_neon_add(size, tmp, tmp2); break; - case NEON_3R_VADD_VSUB: - if (!u) { /* VADD */ - gen_neon_add(size, tmp, tmp2); - } else { /* VSUB */ - switch (size) { - case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break; - case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break; - case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break; - default: abort(); - } - } - break; case NEON_3R_VTST_VCEQ: if (!u) { /* VTST */ switch (size) { --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539292083675879.335366626312; Thu, 11 Oct 2018 14:08:03 -0700 (PDT) Received: from localhost ([::1]:37148 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAiBe-0001XW-Hs for importer@patchew.org; Thu, 11 Oct 2018 17:08:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45194) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhwq-0006s6-02 for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAhwm-00063p-LX for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:43 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:36418) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAhwm-0004La-Cy for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:40 -0400 Received: by mail-pf1-x42f.google.com with SMTP id l81-v6so5011778pfg.3 for ; Thu, 11 Oct 2018 13:52:24 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZgCQfNDDv73oCAjrYwd3E50LsnVqhyPZQcU35qeKmnc=; b=CbM/4cpMMPVgz/6j8G95ul0OIn8MXTrEMZoBwqYhoBlt4hz6f+1YgObvXgYXKGZzxs tj37Ns7Yph+sRnqoaMtp6Su1HuyD+4fE5Fg9WuZIP2qdi6qSrfNdIB7iGWgqmF7J45Ln W9LWafU5JSc2xBs5gCuu0ts0Sjq7ty5NVMda0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZgCQfNDDv73oCAjrYwd3E50LsnVqhyPZQcU35qeKmnc=; b=RwXMomVJxaZ1w/ToDHaySdTnkJQfnlNEq44afXJY+eEQVhNgtmEIBkrLN+rsOXivkC cYnQP1XrrptKIwOrCAx4GgWD5yYyi68EwBYFGfj6DAah0cxUA6sZxdSfuT1SMAkqlXZe D1XEVjqmG1NbxyqGbxuGgqiDY8011P6Ep1smKYsea3QXU/1CkAj7Po6y4UFC7pQZU+DL qziwdWsP61b+hDCApN1P21ecjA+xCxylzbUUFsc2YS6v4BN9O7rqCxK9/l8ObSNDU4VF 6rvcT/NZGbfzrD1B18qN/fcCQ83ZarAEIwoMatHq4IJc4G88fU9y6nnkbTrFSE+Me531 n6qA== X-Gm-Message-State: ABuFfoinyEKEcVLkoN4qjQkVY8WgwswckwP7/ExUS8kJSBSoK7bths9E 6JNuEv8xhRK9nBVJfoSz5wClBU09C+0= X-Google-Smtp-Source: ACcGV622OUB90nTUV5grMZpiDNPbwGItdjQMm4/RpyvU2ynCGv42qk7Z6rRVBlPBnGT/C0XRw7R1SA== X-Received: by 2002:a62:8dcd:: with SMTP id p74-v6mr3166928pfk.217.1539291143521; Thu, 11 Oct 2018 13:52:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:51:56 -0700 Message-Id: <20181011205206.3552-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42f Subject: [Qemu-devel] [PATCH 10/20] target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4dcd7123e9..fae132791a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7501,6 +7501,14 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) tcg_temp_free_ptr(ptr1); tcg_temp_free_ptr(ptr2); break; + + case NEON_2RM_VMVN: + tcg_gen_gvec_not(0, rd_ofs, rm_ofs, vec_size, vec_size= ); + break; + case NEON_2RM_VNEG: + tcg_gen_gvec_neg(size, rd_ofs, rm_ofs, vec_size, vec_s= ize); + break; + default: elementwise: for (pass =3D 0; pass < (q ? 4 : 2); pass++) { @@ -7541,9 +7549,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case NEON_2RM_VCNT: gen_helper_neon_cnt_u8(tmp, tmp); break; - case NEON_2RM_VMVN: - tcg_gen_not_i32(tmp, tmp); - break; case NEON_2RM_VQABS: switch (size) { case 0: @@ -7616,11 +7621,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) default: abort(); } break; - case NEON_2RM_VNEG: - tmp2 =3D tcg_const_i32(0); - gen_neon_rsb(size, tmp, tmp2); - tcg_temp_free_i32(tmp2); - break; case NEON_2RM_VCGT0_F: { TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539291619435551.4899073591411; Thu, 11 Oct 2018 14:00:19 -0700 (PDT) Received: from localhost ([::1]:37101 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAi46-0004Ao-6z for importer@patchew.org; Thu, 11 Oct 2018 17:00:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45128) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhwn-0006pu-N1 for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAhwk-0005qW-HE for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:41 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:35122) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAhwk-0004Vi-54 for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:38 -0400 Received: by mail-pl1-x62c.google.com with SMTP id f8-v6so4800477plb.2 for ; Thu, 11 Oct 2018 13:52:26 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LNgl33bcGYxCeXHpbio/Rlmde9MWJEOYAK1mblGiRdQ=; b=UAjOBOvOve0vBvxVslb6RUoxja2q+Mocn/qwOk4ptmsy2dhj7tPxM+mBDlnMTw2TNS J3F8/2zOMHDcM3NSXnuW/ZsXaqM5AQLcd8jlscPmlaNXh0xaX62YLOHJoJNh2OaQNbWR w/i5g7+NJQv4cCS8WorM15kLI7YKhYeLGjVYk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LNgl33bcGYxCeXHpbio/Rlmde9MWJEOYAK1mblGiRdQ=; b=mA80G1lBbOZYnTwSesUenToHHMmJChh7wa3lIcRXTihTmiwvtMui6QtL0zRuzu6Yhk sRAZiJHAHek4CLKrOQoXunITPaPoLC3s9be0G3QGp160LBro4WKEfDXuAfH88pUNVIn+ 9/0DF/NeXZIW/WAQhXWgjYVcvCi08NXXI5sCb3z9fAdNmvPGkUa5aL89PqCOhGIH4CKg AJ4QX3XO69HoiK5qlui034AbewCcupBUcaKaoNK2tQGdrQejBagzxlmHCkVgnU+Dh9BH pJr4YonmqNGfZ9TvIYuXl8dxdecmvuVI2bK3EyPr2OjyAkBFA/hDJlXeOssNyggOuRq0 wolg== X-Gm-Message-State: ABuFfoiDQ0Hs8N9FAITk1sG6/DYav6nRe/2INtdsEN+FST8K8KzHoxda 1tta5f2nRKJe5tGmGVmYm0Ra26+eW7g= X-Google-Smtp-Source: ACcGV626Ld51HZG69hhqOOOPbtKG8qRD4/4/hvcrd0Bi5MNPer18+HQyud+rhsVgHOokLoMoi7Waow== X-Received: by 2002:a17:902:8a93:: with SMTP id p19-v6mr2970180plo.41.1539291145090; Thu, 11 Oct 2018 13:52:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:51:57 -0700 Message-Id: <20181011205206.3552-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62c Subject: [Qemu-devel] [PATCH 11/20] target/arm: Use gvec for NEON_3R_VMUL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index fae132791a..e195efcc55 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5959,6 +5959,19 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) vec_size, vec_size); } return 0; + + case NEON_3R_VMUL: /* VMUL */ + if (u) { + /* Polynomial case allows only P8 and is handled below. */ + if (size !=3D 0) { + return 1; + } + } else { + tcg_gen_gvec_mul(size, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); + return 0; + } + break; } if (size =3D=3D 3) { /* 64-bit element instructions. */ @@ -6065,12 +6078,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) return 1; } break; - case NEON_3R_VMUL: - if (u && (size !=3D 0)) { - /* UNDEF on invalid size for polynomial subcase */ - return 1; - } - break; case NEON_3R_VFM_VQRDMLSH: if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) { return 1; @@ -6183,16 +6190,8 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) } break; case NEON_3R_VMUL: - if (u) { /* polynomial */ - gen_helper_neon_mul_p8(tmp, tmp, tmp2); - } else { /* Integer */ - switch (size) { - case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break; - case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break; - case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break; - default: abort(); - } - } + /* VMUL.P8; other cases already eliminated. */ + gen_helper_neon_mul_p8(tmp, tmp, tmp2); break; case NEON_3R_VPMAX: GEN_NEON_INTEGER_OP(pmax); --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539291783662734.431834601986; Thu, 11 Oct 2018 14:03:03 -0700 (PDT) Received: from localhost ([::1]:37124 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAi6k-0006Aq-GO for importer@patchew.org; Thu, 11 Oct 2018 17:02:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45193) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhwp-0006s3-V7 for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAhwl-0005xJ-Og for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:43 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:35778) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAhwl-0004jE-8Q for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:39 -0400 Received: by mail-pl1-x641.google.com with SMTP id f8-v6so4800498plb.2 for ; Thu, 11 Oct 2018 13:52:27 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UCjLvGDYtuODMoxEmWHRu54PGDreeQMV1QK7QOr2PKo=; b=NhfVVuNO8W/bs+fpTtnykRo7kNLA/H6Pb+V4y2/VbyCzgEOWnvXozY0pSYnH1PNa68 +uMpBr7hLsZyB+bH2domJtU3HMD/agR7VekYZX6MeVDA7RX1pveLYGUS7Y0558CP6yum As5ss5Y14SzpOZEcv+xqRs8BeeF9+ssuQkNjo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UCjLvGDYtuODMoxEmWHRu54PGDreeQMV1QK7QOr2PKo=; b=geymNtQ5kYIEWoVI0XJpsNy2w7mKihkonZgN+CJdDAFZeyyPuCsD6a/gFMZyccFKWs MFgqyMm6UFV5zngzf6pMb+ZyFEosnU/d7GgiSExTnvFgx405skNjwGeOQlfiQ9RT1AlM QmFIUVu6ALg6y4va6Jwzl3D42TY3s70d3jpGrG0k0KRkCXrg8T+0u1sgXGEbya+O8aol B1W1zHT09cnFohKUSTKxn+HjlrVt9bz9FavcHWTCRZYITym751J8mKRqe6i/r3EgOJA0 h/XR+s/q1sld6aMjllBR0fWWBEOCkIF8bMu3WrEQnsHSjhb4FSAdrjfozCDNtCTXEXWg awuA== X-Gm-Message-State: ABuFfojrVGmigWbd0UKJUxyACqt8F3OLjEBelZ9GFUByLU9BlTde+FCt 4eKbYkAF8w10vw5r+e7CvCztjkdRa/M= X-Google-Smtp-Source: ACcGV63L6XKQdLD96mUO5QUhhydbsdrCXyrjOTnJgG/tvAgkYBGa/7ImR+lUETxs7c9rJqvRSwcFjA== X-Received: by 2002:a17:902:b403:: with SMTP id x3-v6mr3040457plr.237.1539291146556; Thu, 11 Oct 2018 13:52:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:51:58 -0700 Message-Id: <20181011205206.3552-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 12/20] target/arm: Use gvec for VSHR, VSHL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate.c | 70 +++++++++++++++++++++++++++++------------- 1 file changed, 48 insertions(+), 22 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index e195efcc55..a16f323d52 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6373,8 +6373,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) size--; } shift =3D (insn >> 16) & ((1 << (3 + size)) - 1); - /* To avoid excessive duplication of ops we implement shift - by immediate using the variable shift operations. */ if (op < 8) { /* Shift by immediate: VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */ @@ -6386,37 +6384,62 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) } /* Right shifts are encoded as N - shift, where N is the element size in bits. */ - if (op <=3D 4) + if (op <=3D 4) { shift =3D shift - (1 << (size + 3)); + } + + switch (op) { + case 0: /* VSHR */ + /* Right shift comes here negative. */ + shift =3D -shift; + /* Shifts larger than the element size are architectur= ally + * valid. Unsigned results in all zeros; signed resul= ts + * in all sign bits. + */ + if (!u) { + tcg_gen_gvec_sari(size, rd_ofs, rm_ofs, + MIN(shift, (8 << size) - 1), + vec_size, vec_size); + } else if (shift >=3D 8 << size) { + tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size, 0); + } else { + tcg_gen_gvec_shri(size, rd_ofs, rm_ofs, shift, + vec_size, vec_size); + } + return 0; + + case 5: /* VSHL, VSLI */ + if (!u) { /* VSHL */ + /* Shifts larger than the element size are + * architecturally valid and results in zero. + */ + if (shift >=3D 8 << size) { + tcg_gen_gvec_dup8i(rd_ofs, vec_size, vec_size,= 0); + } else { + tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift, + vec_size, vec_size); + } + return 0; + } + break; + } + if (size =3D=3D 3) { count =3D q + 1; } else { count =3D q ? 4: 2; } - switch (size) { - case 0: - imm =3D (uint8_t) shift; - imm |=3D imm << 8; - imm |=3D imm << 16; - break; - case 1: - imm =3D (uint16_t) shift; - imm |=3D imm << 16; - break; - case 2: - case 3: - imm =3D shift; - break; - default: - abort(); - } + + /* To avoid excessive duplication of ops we implement shift + * by immediate using the variable shift operations. + */ + imm =3D dup_const(size, shift); =20 for (pass =3D 0; pass < count; pass++) { if (size =3D=3D 3) { neon_load_reg64(cpu_V0, rm + pass); tcg_gen_movi_i64(cpu_V1, imm); switch (op) { - case 0: /* VSHR */ case 1: /* VSRA */ if (u) gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cp= u_V1); @@ -6447,6 +6470,8 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) cpu_V0, cpu_V1); } break; + default: + g_assert_not_reached(); } if (op =3D=3D 1 || op =3D=3D 3) { /* Accumulate. */ @@ -6475,7 +6500,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) tmp2 =3D tcg_temp_new_i32(); tcg_gen_movi_i32(tmp2, imm); switch (op) { - case 0: /* VSHR */ case 1: /* VSRA */ GEN_NEON_INTEGER_OP(shl); break; @@ -6513,6 +6537,8 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case 7: /* VQSHL */ GEN_NEON_INTEGER_OP_ENV(qshl); break; + default: + g_assert_not_reached(); } tcg_temp_free_i32(tmp2); =20 --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539291782527464.50019754209995; Thu, 11 Oct 2018 14:03:02 -0700 (PDT) Received: from localhost ([::1]:37123 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAi6k-0006Ad-Er for importer@patchew.org; Thu, 11 Oct 2018 17:02:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45132) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhwn-0006py-OW for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAhwk-0005q6-Ek for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:41 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:34092) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAhwj-0004v0-Lg for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:38 -0400 Received: by mail-pl1-x643.google.com with SMTP id f18-v6so4805266plr.1 for ; Thu, 11 Oct 2018 13:52:29 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SVZWxGM/+QSi72cJ3hdj7+1OLNZyp9zTeJBbg4Deg/w=; b=eXadpvQKF7DBGqLLUK4RW+9fPZQuHjOafDIQyvsuwu/9nk1W9AR8bNF4xR7uAbD3y9 5gmkrubMV39U4tVrFTS6dQNGx/7zgJO0rqUD8VfwXjxgMeQrzHuVksKF3GJgCLv/OHhG OHFWaeOEifeOHPqXUYTuzqE1iYgSzEhOqsED0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SVZWxGM/+QSi72cJ3hdj7+1OLNZyp9zTeJBbg4Deg/w=; b=VgsudFtHkAqcTLr1ZZmVKxx8dQ5rZWyGnryeVdwW79hLjbSJrCbF5tGr4bv6cO7yy+ fkEQem2hTXu+Vf4HSiHYmM311TlI1xVYaAn3bc/bbY1o1KtYtD9KNltMM2D/wHbaJT7R 7EH764uGvZ5grsGjztYCRoaSKWigdw8HAxkmYO1z4OlX9VeBmjR7qKrr3lTUKjhggryS HEg73oww3tzbu73PFS+F7YVE113zuHm2/aJa6BafBNbi2Vx75rhf+5QZtLXyDyU+A/AT UjRuXLe+BlAUQS9BietvbqcUfI8ds9BVG0HhUlRwnj1uICPCzRFHVdVqSDt7xXS3TZYo 2V+A== X-Gm-Message-State: ABuFfoi7UFFl2zRpp1QAknhlBqeXXeCAFkrD1iqeyftkp5xgffgLbLIm 9YpE9HFUDUMuS8RM256dOoqAPpzwjx8= X-Google-Smtp-Source: ACcGV6333VoPwFkn64ON0I+dXpLrHf9h90WXqMeZKBRFnUlC94t/zbFgQaV4QuqBy3anQg35ttyjdg== X-Received: by 2002:a17:902:7442:: with SMTP id e2-v6mr3015964plt.314.1539291148066; Thu, 11 Oct 2018 13:52:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:51:59 -0700 Message-Id: <20181011205206.3552-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH 13/20] target/arm: Use gvec for VSRA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move ssra_op and usra_op expanders from translate-a64.c. Signed-off-by: Richard Henderson --- target/arm/translate.h | 2 + target/arm/translate-a64.c | 106 ---------------------------- target/arm/translate.c | 139 ++++++++++++++++++++++++++++++++++--- 3 files changed, 130 insertions(+), 117 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 7cc2685104..8487b349ef 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -195,6 +195,8 @@ static inline TCGv_i32 get_ahp_flag(void) extern const GVecGen3 bsl_op; extern const GVecGen3 bit_op; extern const GVecGen3 bif_op; +extern const GVecGen2i ssra_op[4]; +extern const GVecGen2i usra_op[4]; =20 #define FORWARD_FEATURE(NAME) \ static inline bool aa32_dc_feature_##NAME(DisasContext *dc) \ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a115546a6a..1a9ae6d5f4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9392,66 +9392,6 @@ static void disas_simd_scalar_two_reg_misc(DisasCont= ext *s, uint32_t insn) } } =20 -static void gen_ssra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) -{ - tcg_gen_vec_sar8i_i64(a, a, shift); - tcg_gen_vec_add8_i64(d, d, a); -} - -static void gen_ssra16_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) -{ - tcg_gen_vec_sar16i_i64(a, a, shift); - tcg_gen_vec_add16_i64(d, d, a); -} - -static void gen_ssra32_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift) -{ - tcg_gen_sari_i32(a, a, shift); - tcg_gen_add_i32(d, d, a); -} - -static void gen_ssra64_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) -{ - tcg_gen_sari_i64(a, a, shift); - tcg_gen_add_i64(d, d, a); -} - -static void gen_ssra_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh) -{ - tcg_gen_sari_vec(vece, a, a, sh); - tcg_gen_add_vec(vece, d, d, a); -} - -static void gen_usra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) -{ - tcg_gen_vec_shr8i_i64(a, a, shift); - tcg_gen_vec_add8_i64(d, d, a); -} - -static void gen_usra16_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) -{ - tcg_gen_vec_shr16i_i64(a, a, shift); - tcg_gen_vec_add16_i64(d, d, a); -} - -static void gen_usra32_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift) -{ - tcg_gen_shri_i32(a, a, shift); - tcg_gen_add_i32(d, d, a); -} - -static void gen_usra64_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) -{ - tcg_gen_shri_i64(a, a, shift); - tcg_gen_add_i64(d, d, a); -} - -static void gen_usra_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh) -{ - tcg_gen_shri_vec(vece, a, a, sh); - tcg_gen_add_vec(vece, d, d, a); -} - static void gen_shr8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) { uint64_t mask =3D dup_const(MO_8, 0xff >> shift); @@ -9507,52 +9447,6 @@ static void gen_shr_ins_vec(unsigned vece, TCGv_vec = d, TCGv_vec a, int64_t sh) static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u, int immh, int immb, int opcode, int rn, i= nt rd) { - static const GVecGen2i ssra_op[4] =3D { - { .fni8 =3D gen_ssra8_i64, - .fniv =3D gen_ssra_vec, - .load_dest =3D true, - .opc =3D INDEX_op_sari_vec, - .vece =3D MO_8 }, - { .fni8 =3D gen_ssra16_i64, - .fniv =3D gen_ssra_vec, - .load_dest =3D true, - .opc =3D INDEX_op_sari_vec, - .vece =3D MO_16 }, - { .fni4 =3D gen_ssra32_i32, - .fniv =3D gen_ssra_vec, - .load_dest =3D true, - .opc =3D INDEX_op_sari_vec, - .vece =3D MO_32 }, - { .fni8 =3D gen_ssra64_i64, - .fniv =3D gen_ssra_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, - .load_dest =3D true, - .opc =3D INDEX_op_sari_vec, - .vece =3D MO_64 }, - }; - static const GVecGen2i usra_op[4] =3D { - { .fni8 =3D gen_usra8_i64, - .fniv =3D gen_usra_vec, - .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, - .vece =3D MO_8, }, - { .fni8 =3D gen_usra16_i64, - .fniv =3D gen_usra_vec, - .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, - .vece =3D MO_16, }, - { .fni4 =3D gen_usra32_i32, - .fniv =3D gen_usra_vec, - .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, - .vece =3D MO_32, }, - { .fni8 =3D gen_usra64_i64, - .fniv =3D gen_usra_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, - .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, - .vece =3D MO_64, }, - }; static const GVecGen2i sri_op[4] =3D { { .fni8 =3D gen_shr8_ins_i64, .fniv =3D gen_shr_ins_vec, diff --git a/target/arm/translate.c b/target/arm/translate.c index a16f323d52..da95851370 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5770,6 +5770,113 @@ const GVecGen3 bif_op =3D { .load_dest =3D true }; =20 +static void gen_ssra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) +{ + tcg_gen_vec_sar8i_i64(a, a, shift); + tcg_gen_vec_add8_i64(d, d, a); +} + +static void gen_ssra16_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) +{ + tcg_gen_vec_sar16i_i64(a, a, shift); + tcg_gen_vec_add16_i64(d, d, a); +} + +static void gen_ssra32_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift) +{ + tcg_gen_sari_i32(a, a, shift); + tcg_gen_add_i32(d, d, a); +} + +static void gen_ssra64_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) +{ + tcg_gen_sari_i64(a, a, shift); + tcg_gen_add_i64(d, d, a); +} + +static void gen_ssra_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh) +{ + tcg_gen_sari_vec(vece, a, a, sh); + tcg_gen_add_vec(vece, d, d, a); +} + +const GVecGen2i ssra_op[4] =3D { + { .fni8 =3D gen_ssra8_i64, + .fniv =3D gen_ssra_vec, + .load_dest =3D true, + .opc =3D INDEX_op_sari_vec, + .vece =3D MO_8 }, + { .fni8 =3D gen_ssra16_i64, + .fniv =3D gen_ssra_vec, + .load_dest =3D true, + .opc =3D INDEX_op_sari_vec, + .vece =3D MO_16 }, + { .fni4 =3D gen_ssra32_i32, + .fniv =3D gen_ssra_vec, + .load_dest =3D true, + .opc =3D INDEX_op_sari_vec, + .vece =3D MO_32 }, + { .fni8 =3D gen_ssra64_i64, + .fniv =3D gen_ssra_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .load_dest =3D true, + .opc =3D INDEX_op_sari_vec, + .vece =3D MO_64 }, +}; + +static void gen_usra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) +{ + tcg_gen_vec_shr8i_i64(a, a, shift); + tcg_gen_vec_add8_i64(d, d, a); +} + +static void gen_usra16_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) +{ + tcg_gen_vec_shr16i_i64(a, a, shift); + tcg_gen_vec_add16_i64(d, d, a); +} + +static void gen_usra32_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift) +{ + tcg_gen_shri_i32(a, a, shift); + tcg_gen_add_i32(d, d, a); +} + +static void gen_usra64_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) +{ + tcg_gen_shri_i64(a, a, shift); + tcg_gen_add_i64(d, d, a); +} + +static void gen_usra_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh) +{ + tcg_gen_shri_vec(vece, a, a, sh); + tcg_gen_add_vec(vece, d, d, a); +} + +const GVecGen2i usra_op[4] =3D { + { .fni8 =3D gen_usra8_i64, + .fniv =3D gen_usra_vec, + .load_dest =3D true, + .opc =3D INDEX_op_shri_vec, + .vece =3D MO_8, }, + { .fni8 =3D gen_usra16_i64, + .fniv =3D gen_usra_vec, + .load_dest =3D true, + .opc =3D INDEX_op_shri_vec, + .vece =3D MO_16, }, + { .fni4 =3D gen_usra32_i32, + .fniv =3D gen_usra_vec, + .load_dest =3D true, + .opc =3D INDEX_op_shri_vec, + .vece =3D MO_32, }, + { .fni8 =3D gen_usra64_i64, + .fniv =3D gen_usra_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .load_dest =3D true, + .opc =3D INDEX_op_shri_vec, + .vece =3D MO_64, }, +}; =20 /* Translate a NEON data processing instruction. Return nonzero if the instruction is invalid. @@ -6408,6 +6515,25 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) } return 0; =20 + case 1: /* VSRA */ + /* Right shift comes here negative. */ + shift =3D -shift; + /* Shifts larger than the element size are architectur= ally + * valid. Unsigned results in all zeros; signed resul= ts + * in all sign bits. + */ + if (!u) { + tcg_gen_gvec_2i(rd_ofs, rm_ofs, vec_size, vec_size, + MIN(shift, (8 << size) - 1), + &ssra_op[size]); + } else if (shift >=3D 8 << size) { + /* rd +=3D 0 */ + } else { + tcg_gen_gvec_2i(rd_ofs, rm_ofs, vec_size, vec_size, + shift, &usra_op[size]); + } + return 0; + case 5: /* VSHL, VSLI */ if (!u) { /* VSHL */ /* Shifts larger than the element size are @@ -6440,12 +6566,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) neon_load_reg64(cpu_V0, rm + pass); tcg_gen_movi_i64(cpu_V1, imm); switch (op) { - case 1: /* VSRA */ - if (u) - gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cp= u_V1); - else - gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cp= u_V1); - break; case 2: /* VRSHR */ case 3: /* VRSRA */ if (u) @@ -6473,7 +6593,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) default: g_assert_not_reached(); } - if (op =3D=3D 1 || op =3D=3D 3) { + if (op =3D=3D 3) { /* Accumulate. */ neon_load_reg64(cpu_V1, rd + pass); tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1); @@ -6500,9 +6620,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) tmp2 =3D tcg_temp_new_i32(); tcg_gen_movi_i32(tmp2, imm); switch (op) { - case 1: /* VSRA */ - GEN_NEON_INTEGER_OP(shl); - break; case 2: /* VRSHR */ case 3: /* VRSRA */ GEN_NEON_INTEGER_OP(rshl); @@ -6542,7 +6659,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) } tcg_temp_free_i32(tmp2); =20 - if (op =3D=3D 1 || op =3D=3D 3) { + if (op =3D=3D 3) { /* Accumulate. */ tmp2 =3D neon_load_reg(rd, pass); gen_neon_add(size, tmp, tmp2); --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539292087779377.3737932106535; Thu, 11 Oct 2018 14:08:07 -0700 (PDT) Received: from localhost ([::1]:37149 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAiBf-0001Yv-70 for importer@patchew.org; Thu, 11 Oct 2018 17:08:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45141) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhwo-0006qQ-8R for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAhwl-0005wG-Jk for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:42 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:46740) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAhwl-00055K-17 for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:39 -0400 Received: by mail-pg1-x542.google.com with SMTP id a5-v6so4715096pgv.13 for ; Thu, 11 Oct 2018 13:52:30 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UlzYxI9WYrN93NptToDFcy8fLt/eX4gWcP95G/CzGnw=; b=D02MS9Dsn1wFtdrWY6TLZ1m3mv/0JkVwPy5BMdTWWjyHkuZP/tIdw9gLWP25GCw27w WTXrxFjx2aMOa9DD89JYpH5TG6/KeBoLxUK0nYUsFm5T2h4qHUz8uPUdLYPtDWuVLuIZ bkwFWadqwjx+eccyRB7aTqU5UZJ8T1ELjnPhg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UlzYxI9WYrN93NptToDFcy8fLt/eX4gWcP95G/CzGnw=; b=Si/smfmuaZ+FwGTDxtc5WukfkX/fjlfRs3Cc+SkkqYOye+mimKjcPpOWkagBqcssTX JmElXhBOtGP3NfTg1oE8vbqTR8jai9VYklAEYymQm7yxDR7zc7zVYFQHpXZnbiGkvjne 5sxyoaxqIf9ms1b3+lvLd5n0MuHHSB9/NaxNXLwTPFzo7MaMSfwtBOs9Bt5A1nd7a5Xd nvgF9bjNk/910Ma3RL0ZNw2AGXPLlxnCQw6eirh6iccF6ZIvf6t3BahXqFZ/2jm3IbSI AsKGqGT5Pz8RqXPJL/205SF3OnGHjLnVWDo0ZhIscu6HbixJy7Uie2hJStG+n/JiQ4rR P06Q== X-Gm-Message-State: ABuFfojjeS5I8HPEY7iY0qvxTMRDU337rv9ZyB/481dM5kiITqDs/Vsh M4rM51P/JrPje09U7c65gA5MDiQRZ50= X-Google-Smtp-Source: ACcGV61ufS9iIAUeP47o5icsNDL5SlZjVDBwByCnWjgkSklpsGQVZNCvVX8Dy7k4EZTVtGXDnCZAwA== X-Received: by 2002:a63:4a0e:: with SMTP id x14-v6mr2772644pga.34.1539291149597; Thu, 11 Oct 2018 13:52:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:52:00 -0700 Message-Id: <20181011205206.3552-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 14/20] target/arm: Use gvec for VSRI, VSLI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move shi_op and sli_op expanders from translate-a64.c. Signed-off-by: Richard Henderson --- target/arm/translate.h | 2 + target/arm/translate-a64.c | 152 +---------------------- target/arm/translate.c | 244 ++++++++++++++++++++++++++----------- 3 files changed, 179 insertions(+), 219 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 8487b349ef..ef44f0a5e5 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -197,6 +197,8 @@ extern const GVecGen3 bit_op; extern const GVecGen3 bif_op; extern const GVecGen2i ssra_op[4]; extern const GVecGen2i usra_op[4]; +extern const GVecGen2i sri_op[4]; +extern const GVecGen2i sli_op[4]; =20 #define FORWARD_FEATURE(NAME) \ static inline bool aa32_dc_feature_##NAME(DisasContext *dc) \ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1a9ae6d5f4..f47c132e6c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9392,85 +9392,10 @@ static void disas_simd_scalar_two_reg_misc(DisasCon= text *s, uint32_t insn) } } =20 -static void gen_shr8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) -{ - uint64_t mask =3D dup_const(MO_8, 0xff >> shift); - TCGv_i64 t =3D tcg_temp_new_i64(); - - tcg_gen_shri_i64(t, a, shift); - tcg_gen_andi_i64(t, t, mask); - tcg_gen_andi_i64(d, d, ~mask); - tcg_gen_or_i64(d, d, t); - tcg_temp_free_i64(t); -} - -static void gen_shr16_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) -{ - uint64_t mask =3D dup_const(MO_16, 0xffff >> shift); - TCGv_i64 t =3D tcg_temp_new_i64(); - - tcg_gen_shri_i64(t, a, shift); - tcg_gen_andi_i64(t, t, mask); - tcg_gen_andi_i64(d, d, ~mask); - tcg_gen_or_i64(d, d, t); - tcg_temp_free_i64(t); -} - -static void gen_shr32_ins_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift) -{ - tcg_gen_shri_i32(a, a, shift); - tcg_gen_deposit_i32(d, d, a, 0, 32 - shift); -} - -static void gen_shr64_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) -{ - tcg_gen_shri_i64(a, a, shift); - tcg_gen_deposit_i64(d, d, a, 0, 64 - shift); -} - -static void gen_shr_ins_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t= sh) -{ - uint64_t mask =3D (2ull << ((8 << vece) - 1)) - 1; - TCGv_vec t =3D tcg_temp_new_vec_matching(d); - TCGv_vec m =3D tcg_temp_new_vec_matching(d); - - tcg_gen_dupi_vec(vece, m, mask ^ (mask >> sh)); - tcg_gen_shri_vec(vece, t, a, sh); - tcg_gen_and_vec(vece, d, d, m); - tcg_gen_or_vec(vece, d, d, t); - - tcg_temp_free_vec(t); - tcg_temp_free_vec(m); -} - /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u, int immh, int immb, int opcode, int rn, i= nt rd) { - static const GVecGen2i sri_op[4] =3D { - { .fni8 =3D gen_shr8_ins_i64, - .fniv =3D gen_shr_ins_vec, - .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, - .vece =3D MO_8 }, - { .fni8 =3D gen_shr16_ins_i64, - .fniv =3D gen_shr_ins_vec, - .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, - .vece =3D MO_16 }, - { .fni4 =3D gen_shr32_ins_i32, - .fniv =3D gen_shr_ins_vec, - .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, - .vece =3D MO_32 }, - { .fni8 =3D gen_shr64_ins_i64, - .fniv =3D gen_shr_ins_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, - .load_dest =3D true, - .opc =3D INDEX_op_shri_vec, - .vece =3D MO_64 }, - }; - int size =3D 32 - clz32(immh) - 1; int immhb =3D immh << 3 | immb; int shift =3D 2 * (8 << size) - immhb; @@ -9566,85 +9491,10 @@ static void handle_vec_simd_shri(DisasContext *s, b= ool is_q, bool is_u, clear_vec_high(s, is_q, rd); } =20 -static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) -{ - uint64_t mask =3D dup_const(MO_8, 0xff << shift); - TCGv_i64 t =3D tcg_temp_new_i64(); - - tcg_gen_shli_i64(t, a, shift); - tcg_gen_andi_i64(t, t, mask); - tcg_gen_andi_i64(d, d, ~mask); - tcg_gen_or_i64(d, d, t); - tcg_temp_free_i64(t); -} - -static void gen_shl16_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) -{ - uint64_t mask =3D dup_const(MO_16, 0xffff << shift); - TCGv_i64 t =3D tcg_temp_new_i64(); - - tcg_gen_shli_i64(t, a, shift); - tcg_gen_andi_i64(t, t, mask); - tcg_gen_andi_i64(d, d, ~mask); - tcg_gen_or_i64(d, d, t); - tcg_temp_free_i64(t); -} - -static void gen_shl32_ins_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift) -{ - tcg_gen_deposit_i32(d, d, a, shift, 32 - shift); -} - -static void gen_shl64_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) -{ - tcg_gen_deposit_i64(d, d, a, shift, 64 - shift); -} - -static void gen_shl_ins_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t= sh) -{ - uint64_t mask =3D (1ull << sh) - 1; - TCGv_vec t =3D tcg_temp_new_vec_matching(d); - TCGv_vec m =3D tcg_temp_new_vec_matching(d); - - tcg_gen_dupi_vec(vece, m, mask); - tcg_gen_shli_vec(vece, t, a, sh); - tcg_gen_and_vec(vece, d, d, m); - tcg_gen_or_vec(vece, d, d, t); - - tcg_temp_free_vec(t); - tcg_temp_free_vec(m); -} - /* SHL/SLI - Vector shift left */ static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert, int immh, int immb, int opcode, int rn, i= nt rd) { - static const GVecGen2i shi_op[4] =3D { - { .fni8 =3D gen_shl8_ins_i64, - .fniv =3D gen_shl_ins_vec, - .opc =3D INDEX_op_shli_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, - .load_dest =3D true, - .vece =3D MO_8 }, - { .fni8 =3D gen_shl16_ins_i64, - .fniv =3D gen_shl_ins_vec, - .opc =3D INDEX_op_shli_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, - .load_dest =3D true, - .vece =3D MO_16 }, - { .fni4 =3D gen_shl32_ins_i32, - .fniv =3D gen_shl_ins_vec, - .opc =3D INDEX_op_shli_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, - .load_dest =3D true, - .vece =3D MO_32 }, - { .fni8 =3D gen_shl64_ins_i64, - .fniv =3D gen_shl_ins_vec, - .opc =3D INDEX_op_shli_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, - .load_dest =3D true, - .vece =3D MO_64 }, - }; int size =3D 32 - clz32(immh) - 1; int immhb =3D immh << 3 | immb; int shift =3D immhb - (8 << size); @@ -9664,7 +9514,7 @@ static void handle_vec_simd_shli(DisasContext *s, boo= l is_q, bool insert, } =20 if (insert) { - gen_gvec_op2i(s, is_q, rd, rn, shift, &shi_op[size]); + gen_gvec_op2i(s, is_q, rd, rn, shift, &sli_op[size]); } else { gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shli, size); } diff --git a/target/arm/translate.c b/target/arm/translate.c index da95851370..104b49543d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5878,6 +5878,160 @@ const GVecGen2i usra_op[4] =3D { .vece =3D MO_64, }, }; =20 +static void gen_shr8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) +{ + uint64_t mask =3D dup_const(MO_8, 0xff >> shift); + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_shri_i64(t, a, shift); + tcg_gen_andi_i64(t, t, mask); + tcg_gen_andi_i64(d, d, ~mask); + tcg_gen_or_i64(d, d, t); + tcg_temp_free_i64(t); +} + +static void gen_shr16_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) +{ + uint64_t mask =3D dup_const(MO_16, 0xffff >> shift); + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_shri_i64(t, a, shift); + tcg_gen_andi_i64(t, t, mask); + tcg_gen_andi_i64(d, d, ~mask); + tcg_gen_or_i64(d, d, t); + tcg_temp_free_i64(t); +} + +static void gen_shr32_ins_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift) +{ + tcg_gen_shri_i32(a, a, shift); + tcg_gen_deposit_i32(d, d, a, 0, 32 - shift); +} + +static void gen_shr64_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) +{ + tcg_gen_shri_i64(a, a, shift); + tcg_gen_deposit_i64(d, d, a, 0, 64 - shift); +} + +static void gen_shr_ins_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t= sh) +{ + if (sh =3D=3D 0) { + tcg_gen_mov_vec(d, a); + } else { + TCGv_vec t =3D tcg_temp_new_vec_matching(d); + TCGv_vec m =3D tcg_temp_new_vec_matching(d); + + tcg_gen_dupi_vec(vece, m, MAKE_64BIT_MASK((8 << vece) - sh, sh)); + tcg_gen_shri_vec(vece, t, a, sh); + tcg_gen_and_vec(vece, d, d, m); + tcg_gen_or_vec(vece, d, d, t); + + tcg_temp_free_vec(t); + tcg_temp_free_vec(m); + } +} + +const GVecGen2i sri_op[4] =3D { + { .fni8 =3D gen_shr8_ins_i64, + .fniv =3D gen_shr_ins_vec, + .load_dest =3D true, + .opc =3D INDEX_op_shri_vec, + .vece =3D MO_8 }, + { .fni8 =3D gen_shr16_ins_i64, + .fniv =3D gen_shr_ins_vec, + .load_dest =3D true, + .opc =3D INDEX_op_shri_vec, + .vece =3D MO_16 }, + { .fni4 =3D gen_shr32_ins_i32, + .fniv =3D gen_shr_ins_vec, + .load_dest =3D true, + .opc =3D INDEX_op_shri_vec, + .vece =3D MO_32 }, + { .fni8 =3D gen_shr64_ins_i64, + .fniv =3D gen_shr_ins_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .load_dest =3D true, + .opc =3D INDEX_op_shri_vec, + .vece =3D MO_64 }, +}; + +static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) +{ + uint64_t mask =3D dup_const(MO_8, 0xff << shift); + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_shli_i64(t, a, shift); + tcg_gen_andi_i64(t, t, mask); + tcg_gen_andi_i64(d, d, ~mask); + tcg_gen_or_i64(d, d, t); + tcg_temp_free_i64(t); +} + +static void gen_shl16_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) +{ + uint64_t mask =3D dup_const(MO_16, 0xffff << shift); + TCGv_i64 t =3D tcg_temp_new_i64(); + + tcg_gen_shli_i64(t, a, shift); + tcg_gen_andi_i64(t, t, mask); + tcg_gen_andi_i64(d, d, ~mask); + tcg_gen_or_i64(d, d, t); + tcg_temp_free_i64(t); +} + +static void gen_shl32_ins_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift) +{ + tcg_gen_deposit_i32(d, d, a, shift, 32 - shift); +} + +static void gen_shl64_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) +{ + tcg_gen_deposit_i64(d, d, a, shift, 64 - shift); +} + +static void gen_shl_ins_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t= sh) +{ + if (sh =3D=3D 0) { + tcg_gen_mov_vec(d, a); + } else { + TCGv_vec t =3D tcg_temp_new_vec_matching(d); + TCGv_vec m =3D tcg_temp_new_vec_matching(d); + + tcg_gen_dupi_vec(vece, m, MAKE_64BIT_MASK(0, sh)); + tcg_gen_shli_vec(vece, t, a, sh); + tcg_gen_and_vec(vece, d, d, m); + tcg_gen_or_vec(vece, d, d, t); + + tcg_temp_free_vec(t); + tcg_temp_free_vec(m); + } +} + +const GVecGen2i sli_op[4] =3D { + { .fni8 =3D gen_shl8_ins_i64, + .fniv =3D gen_shl_ins_vec, + .load_dest =3D true, + .opc =3D INDEX_op_shli_vec, + .vece =3D MO_8 }, + { .fni8 =3D gen_shl16_ins_i64, + .fniv =3D gen_shl_ins_vec, + .load_dest =3D true, + .opc =3D INDEX_op_shli_vec, + .vece =3D MO_16 }, + { .fni4 =3D gen_shl32_ins_i32, + .fniv =3D gen_shl_ins_vec, + .load_dest =3D true, + .opc =3D INDEX_op_shli_vec, + .vece =3D MO_32 }, + { .fni8 =3D gen_shl64_ins_i64, + .fniv =3D gen_shl_ins_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .load_dest =3D true, + .opc =3D INDEX_op_shli_vec, + .vece =3D MO_64 }, +}; + /* Translate a NEON data processing instruction. Return nonzero if the instruction is invalid. We process data in a mixture of 32-bit and 64-bit chunks. @@ -5895,7 +6049,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) int pairwise; int u; int vec_size; - uint32_t imm, mask; + uint32_t imm; TCGv_i32 tmp, tmp2, tmp3, tmp4, tmp5; TCGv_ptr ptr1, ptr2, ptr3; TCGv_i64 tmp64; @@ -6534,8 +6688,27 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) } return 0; =20 + case 4: /* VSRI */ + if (!u) { + return 1; + } + /* Right shift comes here negative. */ + shift =3D -shift; + /* Shift out of range leaves destination unchanged. */ + if (shift < 8 << size) { + tcg_gen_gvec_2i(rd_ofs, rm_ofs, vec_size, vec_size, + shift, &sri_op[size]); + } + return 0; + case 5: /* VSHL, VSLI */ - if (!u) { /* VSHL */ + if (u) { /* VSLI */ + /* Shift out of range leaves destination unchanged= . */ + if (shift < 8 << size) { + tcg_gen_gvec_2i(rd_ofs, rm_ofs, vec_size, + vec_size, shift, &sli_op[size]= ); + } + } else { /* VSHL */ /* Shifts larger than the element size are * architecturally valid and results in zero. */ @@ -6545,9 +6718,8 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift, vec_size, vec_size); } - return 0; } - break; + return 0; } =20 if (size =3D=3D 3) { @@ -6573,10 +6745,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) else gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, c= pu_V1); break; - case 4: /* VSRI */ - case 5: /* VSHL, VSLI */ - gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1= ); - break; case 6: /* VQSHLU */ gen_helper_neon_qshlu_s64(cpu_V0, cpu_env, cpu_V0, cpu_V1); @@ -6597,21 +6765,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) /* Accumulate. */ neon_load_reg64(cpu_V1, rd + pass); tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1); - } else if (op =3D=3D 4 || (op =3D=3D 5 && u)) { - /* Insert */ - neon_load_reg64(cpu_V1, rd + pass); - uint64_t mask; - if (shift < -63 || shift > 63) { - mask =3D 0; - } else { - if (op =3D=3D 4) { - mask =3D 0xffffffffffffffffull >> -shi= ft; - } else { - mask =3D 0xffffffffffffffffull << shif= t; - } - } - tcg_gen_andi_i64(cpu_V1, cpu_V1, ~mask); - tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); } neon_store_reg64(cpu_V0, rd + pass); } else { /* size < 3 */ @@ -6624,15 +6777,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) case 3: /* VRSRA */ GEN_NEON_INTEGER_OP(rshl); break; - case 4: /* VSRI */ - case 5: /* VSHL, VSLI */ - switch (size) { - case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2)= ; break; - case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2= ); break; - case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2= ); break; - default: abort(); - } - break; case 6: /* VQSHLU */ switch (size) { case 0: @@ -6664,42 +6808,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) tmp2 =3D neon_load_reg(rd, pass); gen_neon_add(size, tmp, tmp2); tcg_temp_free_i32(tmp2); - } else if (op =3D=3D 4 || (op =3D=3D 5 && u)) { - /* Insert */ - switch (size) { - case 0: - if (op =3D=3D 4) - mask =3D 0xff >> -shift; - else - mask =3D (uint8_t)(0xff << shift); - mask |=3D mask << 8; - mask |=3D mask << 16; - break; - case 1: - if (op =3D=3D 4) - mask =3D 0xffff >> -shift; - else - mask =3D (uint16_t)(0xffff << shift); - mask |=3D mask << 16; - break; - case 2: - if (shift < -31 || shift > 31) { - mask =3D 0; - } else { - if (op =3D=3D 4) - mask =3D 0xffffffffu >> -shift; - else - mask =3D 0xffffffffu << shift; - } - break; - default: - abort(); - } - tmp2 =3D neon_load_reg(rd, pass); - tcg_gen_andi_i32(tmp, tmp, mask); - tcg_gen_andi_i32(tmp2, tmp2, ~mask); - tcg_gen_or_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); } neon_store_reg(rd, pass, tmp); } --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153929227386013.457850853091713; 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eLZcGiUeKPgvYZrKbYk4xKbhpVB1ppGUGYC7GHerwzo=; b=bslszRJp0ypQHhGp+YoTGxjR8/O8PkfR5zMBCJw8EtkjDg++FGL7bcTbQZinS4Gx/e uO0MEr6tCB7NNZOysA0z2GWmJGZg067Ja0z1adAq4Ahah5kNmOWUW0DEe7i88W5s/Wpx CrBPMRiYyQOJ4zOlNYQrQ3/F0JPkaMrH8Zhu4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eLZcGiUeKPgvYZrKbYk4xKbhpVB1ppGUGYC7GHerwzo=; b=ja1boNLrRyeBMVYlJzt0ypsoywgq2s+Dv3OqtLCyg9q0Q2uKhOJ44DdBeFQ6s0JI/S eZ0vxJQXzq4c3Gcbuo815g76txvzYs76qMqTZKCteltYgzB5HutgPeyKinLuK9Hs2ttw SN82Pc0MCqv8PV/cJsniwhsFLyw8NqZAxqg94jZwRhhTbqNuhQDw6SpnKgfyrUvJqONP riwT2dUXaC2YkCvAw61YxHyEVsuZG7I4LTgVrlEi2KgSqXiKizEVdDeJ6JITaPeRCSdf swtBDqqXzvsoJqGqFqXXD+M09KN1joCM7F0SgTPC/ORz4qoWWQz8UPeKLOtKDdy/6/eP B/lw== X-Gm-Message-State: ABuFfoirWw1jI/PnlKxME6ZnjQcNzzG07stnpq7AcvfgU6UdAHjmJWvX h1SsM8oNzZ1DPBfcM0LrwyFB1NgLey0= X-Google-Smtp-Source: ACcGV61vE3VpAQsPHAviqzz/cvJskr8e3yQv2yhLBYTGjrcWK8icaQV7gyQ3sm/oakgSyuvzW53npg== X-Received: by 2002:a63:f14a:: with SMTP id o10-v6mr2747764pgk.339.1539291151076; Thu, 11 Oct 2018 13:52:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:52:01 -0700 Message-Id: <20181011205206.3552-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52e Subject: [Qemu-devel] [PATCH 15/20] target/arm: Use gvec for NEON_3R_VML X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move mla_op and mls_op expanders from translate-a64.c. Signed-off-by: Richard Henderson --- target/arm/translate.h | 2 + target/arm/translate-a64.c | 106 ----------------------------- target/arm/translate.c | 134 ++++++++++++++++++++++++++++++++----- 3 files changed, 120 insertions(+), 122 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index ef44f0a5e5..d11d504301 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -195,6 +195,8 @@ static inline TCGv_i32 get_ahp_flag(void) extern const GVecGen3 bsl_op; extern const GVecGen3 bit_op; extern const GVecGen3 bif_op; +extern const GVecGen3 mla_op[4]; +extern const GVecGen3 mls_op[4]; extern const GVecGen2i ssra_op[4]; extern const GVecGen2i usra_op[4]; extern const GVecGen2i sri_op[4]; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f47c132e6c..94f7127c0e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10410,66 +10410,6 @@ static void disas_simd_3same_float(DisasContext *s= , uint32_t insn) } } =20 -static void gen_mla8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - gen_helper_neon_mul_u8(a, a, b); - gen_helper_neon_add_u8(d, d, a); -} - -static void gen_mla16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - gen_helper_neon_mul_u16(a, a, b); - gen_helper_neon_add_u16(d, d, a); -} - -static void gen_mla32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - tcg_gen_mul_i32(a, a, b); - tcg_gen_add_i32(d, d, a); -} - -static void gen_mla64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) -{ - tcg_gen_mul_i64(a, a, b); - tcg_gen_add_i64(d, d, a); -} - -static void gen_mla_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) -{ - tcg_gen_mul_vec(vece, a, a, b); - tcg_gen_add_vec(vece, d, d, a); -} - -static void gen_mls8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - gen_helper_neon_mul_u8(a, a, b); - gen_helper_neon_sub_u8(d, d, a); -} - -static void gen_mls16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - gen_helper_neon_mul_u16(a, a, b); - gen_helper_neon_sub_u16(d, d, a); -} - -static void gen_mls32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - tcg_gen_mul_i32(a, a, b); - tcg_gen_sub_i32(d, d, a); -} - -static void gen_mls64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) -{ - tcg_gen_mul_i64(a, a, b); - tcg_gen_sub_i64(d, d, a); -} - -static void gen_mls_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) -{ - tcg_gen_mul_vec(vece, a, a, b); - tcg_gen_sub_vec(vece, d, d, a); -} - /* Integer op subgroup of C3.6.16. */ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) { @@ -10488,52 +10428,6 @@ static void disas_simd_3same_int(DisasContext *s, = uint32_t insn) .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, .vece =3D MO_64 }, }; - static const GVecGen3 mla_op[4] =3D { - { .fni4 =3D gen_mla8_i32, - .fniv =3D gen_mla_vec, - .opc =3D INDEX_op_mul_vec, - .load_dest =3D true, - .vece =3D MO_8 }, - { .fni4 =3D gen_mla16_i32, - .fniv =3D gen_mla_vec, - .opc =3D INDEX_op_mul_vec, - .load_dest =3D true, - .vece =3D MO_16 }, - { .fni4 =3D gen_mla32_i32, - .fniv =3D gen_mla_vec, - .opc =3D INDEX_op_mul_vec, - .load_dest =3D true, - .vece =3D MO_32 }, - { .fni8 =3D gen_mla64_i64, - .fniv =3D gen_mla_vec, - .opc =3D INDEX_op_mul_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, - .load_dest =3D true, - .vece =3D MO_64 }, - }; - static const GVecGen3 mls_op[4] =3D { - { .fni4 =3D gen_mls8_i32, - .fniv =3D gen_mls_vec, - .opc =3D INDEX_op_mul_vec, - .load_dest =3D true, - .vece =3D MO_8 }, - { .fni4 =3D gen_mls16_i32, - .fniv =3D gen_mls_vec, - .opc =3D INDEX_op_mul_vec, - .load_dest =3D true, - .vece =3D MO_16 }, - { .fni4 =3D gen_mls32_i32, - .fniv =3D gen_mls_vec, - .opc =3D INDEX_op_mul_vec, - .load_dest =3D true, - .vece =3D MO_32 }, - { .fni8 =3D gen_mls64_i64, - .fniv =3D gen_mls_vec, - .opc =3D INDEX_op_mul_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, - .load_dest =3D true, - .vece =3D MO_64 }, - }; =20 int is_q =3D extract32(insn, 30, 1); int u =3D extract32(insn, 29, 1); diff --git a/target/arm/translate.c b/target/arm/translate.c index 104b49543d..5008a24ffd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5468,7 +5468,7 @@ static void gen_neon_narrow_op(int op, int u, int siz= e, #define NEON_3R_VABA 15 #define NEON_3R_VADD_VSUB 16 #define NEON_3R_VTST_VCEQ 17 -#define NEON_3R_VML 18 /* VMLA, VMLAL, VMLS, VMLSL */ +#define NEON_3R_VML 18 /* VMLA, VMLS */ #define NEON_3R_VMUL 19 #define NEON_3R_VPMAX 20 #define NEON_3R_VPMIN 21 @@ -6032,6 +6032,117 @@ const GVecGen2i sli_op[4] =3D { .vece =3D MO_64 }, }; =20 +static void gen_mla8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u8(a, a, b); + gen_helper_neon_add_u8(d, d, a); +} + +static void gen_mls8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u8(a, a, b); + gen_helper_neon_sub_u8(d, d, a); +} + +static void gen_mla16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u16(a, a, b); + gen_helper_neon_add_u16(d, d, a); +} + +static void gen_mls16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + gen_helper_neon_mul_u16(a, a, b); + gen_helper_neon_sub_u16(d, d, a); +} + +static void gen_mla32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_mul_i32(a, a, b); + tcg_gen_add_i32(d, d, a); +} + +static void gen_mls32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_mul_i32(a, a, b); + tcg_gen_sub_i32(d, d, a); +} + +static void gen_mla64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_mul_i64(a, a, b); + tcg_gen_add_i64(d, d, a); +} + +static void gen_mls64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_mul_i64(a, a, b); + tcg_gen_sub_i64(d, d, a); +} + +static void gen_mla_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) +{ + tcg_gen_mul_vec(vece, a, a, b); + tcg_gen_add_vec(vece, d, d, a); +} + +static void gen_mls_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) +{ + tcg_gen_mul_vec(vece, a, a, b); + tcg_gen_sub_vec(vece, d, d, a); +} + +/* Note that while NEON does not support VMLA and VMLS as 64-bit ops, + * these tables are shared with AArch64 which does support them. + */ +const GVecGen3 mla_op[4] =3D { + { .fni4 =3D gen_mla8_i32, + .fniv =3D gen_mla_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_8 }, + { .fni4 =3D gen_mla16_i32, + .fniv =3D gen_mla_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_16 }, + { .fni4 =3D gen_mla32_i32, + .fniv =3D gen_mla_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_32 }, + { .fni8 =3D gen_mla64_i64, + .fniv =3D gen_mla_vec, + .opc =3D INDEX_op_mul_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .load_dest =3D true, + .vece =3D MO_64 }, +}; + +const GVecGen3 mls_op[4] =3D { + { .fni4 =3D gen_mls8_i32, + .fniv =3D gen_mls_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_8 }, + { .fni4 =3D gen_mls16_i32, + .fniv =3D gen_mls_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_16 }, + { .fni4 =3D gen_mls32_i32, + .fniv =3D gen_mls_vec, + .opc =3D INDEX_op_mul_vec, + .load_dest =3D true, + .vece =3D MO_32 }, + { .fni8 =3D gen_mls64_i64, + .fniv =3D gen_mls_vec, + .opc =3D INDEX_op_mul_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .load_dest =3D true, + .vece =3D MO_64 }, +}; + /* Translate a NEON data processing instruction. Return nonzero if the instruction is invalid. We process data in a mixture of 32-bit and 64-bit chunks. @@ -6233,7 +6344,13 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) return 0; } break; + + case NEON_3R_VML: /* VMLA, VMLS */ + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size, + u ? &mls_op[size] : &mla_op[size]); + return 0; } + if (size =3D=3D 3) { /* 64-bit element instructions. */ for (pass =3D 0; pass < (q ? 2 : 1); pass++) { @@ -6435,21 +6552,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) } } break; - case NEON_3R_VML: /* VMLA, VMLAL, VMLS,VMLSL */ - switch (size) { - case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break; - case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break; - case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break; - default: abort(); - } - tcg_temp_free_i32(tmp2); - tmp2 =3D neon_load_reg(rd, pass); - if (u) { /* VMLS */ - gen_neon_rsb(size, tmp, tmp2); - } else { /* VMLA */ - gen_neon_add(size, tmp, tmp2); - } - break; case NEON_3R_VMUL: /* VMUL.P8; other cases already eliminated. */ gen_helper_neon_mul_p8(tmp, tmp, tmp2); --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539292080945733.512900007254; Thu, 11 Oct 2018 14:08:00 -0700 (PDT) Received: from localhost ([::1]:37147 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAiBb-0001Vr-Ki for importer@patchew.org; Thu, 11 Oct 2018 17:07:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45223) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhwq-0006sy-Sw for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAhwm-00061F-BM for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:44 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:38848) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAhwl-0005MX-RX for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:40 -0400 Received: by mail-pl1-x62a.google.com with SMTP id q19-v6so1704736pll.5 for ; Thu, 11 Oct 2018 13:52:33 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0Tbn/EsVE/RPCeV4S7D1uWQwZWFX3IHE7HdNnmB5KSY=; b=d06ldaIN6xhgE8Igm81vxJON5IwZKxWeir6Z/pBTCRoaCGBEwKwNk3DwXMM/NSLann Qp0s1KBle8TZ14+sYMQPACatyqV0rARYNcaBupcqbwKG0TLZ24sASQILhYn9adgKYvMc 0PJSGMvLg8Sa90fnuOn7V6yFbqlb0KJKCc6ho= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0Tbn/EsVE/RPCeV4S7D1uWQwZWFX3IHE7HdNnmB5KSY=; b=MPEwAVfB35fkr8ynucXoh6Bgk9nfGGN6ww/VgXgxJ8MYvtqa+AWg0OH3/BuG3yiHjc NbzTaqqoT/35vyAyc7bhsDcLeJv4YvtOC6n4RPjDItPaxJrkuXjFdNUVcNUftcGaQyf6 NeOz83egNohIdRJ1yBMMGqdIKYeqfiBYF/6gU0ahYeMBeFhA9yrR952gthmSkdCL7qQr KuNnKluvTxu+liLAft9k3fNc6P2CeqAI1S4Zb6AutZ0CZTiHxOONLF8ya8sc6wWRZ3vB q866/NXuBEAnCu8lDg/UehvUFK2uIHl0snyhOGaIzBs10dQn/RydNq81tcnmSe9DBMk8 tEiw== X-Gm-Message-State: ABuFfohhguQJIhuv0owF/WelB2mqM/Da0Gqiw4Ex620F2KnBGtq8f0sO r6+J39m6AnMCpV1hebdkCmgqYeU6fes= X-Google-Smtp-Source: ACcGV624uPDcSPCrn8cY5+DdFtiZy4VrfwaRgHwl3P6tAlW6xv2F0raF2zj0Q/+OyUcrE4eu/SJeRQ== X-Received: by 2002:a17:902:5a4d:: with SMTP id f13-v6mr3036652plm.114.1539291152641; Thu, 11 Oct 2018 13:52:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:52:02 -0700 Message-Id: <20181011205206.3552-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62a Subject: [Qemu-devel] [PATCH 16/20] target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move cmtst_op expanders from translate-a64.c. Signed-off-by: Richard Henderson --- target/arm/translate.h | 2 + target/arm/translate-a64.c | 38 ------------------ target/arm/translate.c | 81 +++++++++++++++++++++++++++----------- 3 files changed, 60 insertions(+), 61 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index d11d504301..eb7ecbebe5 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -197,10 +197,12 @@ extern const GVecGen3 bit_op; extern const GVecGen3 bif_op; extern const GVecGen3 mla_op[4]; extern const GVecGen3 mls_op[4]; +extern const GVecGen3 cmtst_op[4]; extern const GVecGen2i ssra_op[4]; extern const GVecGen2i usra_op[4]; extern const GVecGen2i sri_op[4]; extern const GVecGen2i sli_op[4]; +void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); =20 #define FORWARD_FEATURE(NAME) \ static inline bool aa32_dc_feature_##NAME(DisasContext *dc) \ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 94f7127c0e..b6f54e66fb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -8031,28 +8031,6 @@ static void disas_simd_scalar_three_reg_diff(DisasCo= ntext *s, uint32_t insn) } } =20 -/* CMTST : test is "if (X & Y !=3D 0)". */ -static void gen_cmtst_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) -{ - tcg_gen_and_i32(d, a, b); - tcg_gen_setcondi_i32(TCG_COND_NE, d, d, 0); - tcg_gen_neg_i32(d, d); -} - -static void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) -{ - tcg_gen_and_i64(d, a, b); - tcg_gen_setcondi_i64(TCG_COND_NE, d, d, 0); - tcg_gen_neg_i64(d, d); -} - -static void gen_cmtst_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec = b) -{ - tcg_gen_and_vec(vece, d, a, b); - tcg_gen_dupi_vec(vece, a, 0); - tcg_gen_cmp_vec(TCG_COND_NE, vece, d, d, a); -} - static void handle_3same_64(DisasContext *s, int opcode, bool u, TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg= _rm) { @@ -10413,22 +10391,6 @@ static void disas_simd_3same_float(DisasContext *s= , uint32_t insn) /* Integer op subgroup of C3.6.16. */ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) { - static const GVecGen3 cmtst_op[4] =3D { - { .fni4 =3D gen_helper_neon_tst_u8, - .fniv =3D gen_cmtst_vec, - .vece =3D MO_8 }, - { .fni4 =3D gen_helper_neon_tst_u16, - .fniv =3D gen_cmtst_vec, - .vece =3D MO_16 }, - { .fni4 =3D gen_cmtst_i32, - .fniv =3D gen_cmtst_vec, - .vece =3D MO_32 }, - { .fni8 =3D gen_cmtst_i64, - .fniv =3D gen_cmtst_vec, - .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, - .vece =3D MO_64 }, - }; - int is_q =3D extract32(insn, 30, 1); int u =3D extract32(insn, 29, 1); int size =3D extract32(insn, 22, 2); diff --git a/target/arm/translate.c b/target/arm/translate.c index 5008a24ffd..a9bd93bba1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6143,6 +6143,44 @@ const GVecGen3 mls_op[4] =3D { .vece =3D MO_64 }, }; =20 +/* CMTST : test is "if (X & Y !=3D 0)". */ +static void gen_cmtst_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_and_i32(d, a, b); + tcg_gen_setcondi_i32(TCG_COND_NE, d, d, 0); + tcg_gen_neg_i32(d, d); +} + +void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_and_i64(d, a, b); + tcg_gen_setcondi_i64(TCG_COND_NE, d, d, 0); + tcg_gen_neg_i64(d, d); +} + +static void gen_cmtst_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec = b) +{ + tcg_gen_and_vec(vece, d, a, b); + tcg_gen_dupi_vec(vece, a, 0); + tcg_gen_cmp_vec(TCG_COND_NE, vece, d, d, a); +} + +const GVecGen3 cmtst_op[4] =3D { + { .fni4 =3D gen_helper_neon_tst_u8, + .fniv =3D gen_cmtst_vec, + .vece =3D MO_8 }, + { .fni4 =3D gen_helper_neon_tst_u16, + .fniv =3D gen_cmtst_vec, + .vece =3D MO_16 }, + { .fni4 =3D gen_cmtst_i32, + .fniv =3D gen_cmtst_vec, + .vece =3D MO_32 }, + { .fni8 =3D gen_cmtst_i64, + .fniv =3D gen_cmtst_vec, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, +}; + /* Translate a NEON data processing instruction. Return nonzero if the instruction is invalid. We process data in a mixture of 32-bit and 64-bit chunks. @@ -6349,6 +6387,26 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size, u ? &mls_op[size] : &mla_op[size]); return 0; + + case NEON_3R_VTST_VCEQ: + if (u) { /* VCEQ */ + tcg_gen_gvec_cmp(TCG_COND_EQ, size, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); + } else { /* VTST */ + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size, &cmtst_op[size]); + } + return 0; + + case NEON_3R_VCGT: + tcg_gen_gvec_cmp(u ? TCG_COND_GTU : TCG_COND_GT, size, + rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size); + return 0; + + case NEON_3R_VCGE: + tcg_gen_gvec_cmp(u ? TCG_COND_GEU : TCG_COND_GE, size, + rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size); + return 0; } =20 if (size =3D=3D 3) { @@ -6502,12 +6560,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) case NEON_3R_VQSUB: GEN_NEON_INTEGER_OP_ENV(qsub); break; - case NEON_3R_VCGT: - GEN_NEON_INTEGER_OP(cgt); - break; - case NEON_3R_VCGE: - GEN_NEON_INTEGER_OP(cge); - break; case NEON_3R_VSHL: GEN_NEON_INTEGER_OP(shl); break; @@ -6535,23 +6587,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) tmp2 =3D neon_load_reg(rd, pass); gen_neon_add(size, tmp, tmp2); break; - case NEON_3R_VTST_VCEQ: - if (!u) { /* VTST */ - switch (size) { - case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break; - case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break; - case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break; - default: abort(); - } - } else { /* VCEQ */ - switch (size) { - case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break; - case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break; - case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break; - default: abort(); - } - } - break; case NEON_3R_VMUL: /* VMUL.P8; other cases already eliminated. */ gen_helper_neon_mul_p8(tmp, tmp, tmp2); --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539291298169748.4269149464411; Thu, 11 Oct 2018 13:54:58 -0700 (PDT) Received: from localhost ([::1]:37074 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhyv-00087J-9K for importer@patchew.org; Thu, 11 Oct 2018 16:54:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45121) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhwn-0006po-LY for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAhwk-0005se-RX for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:41 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:42105) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAhwk-0005UB-A7 for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:38 -0400 Received: by mail-pg1-x530.google.com with SMTP id i4-v6so4724898pgq.9 for ; Thu, 11 Oct 2018 13:52:35 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.32 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cvRkZzylpccO4n3sFiEt4kh2YWk5/bo+faK+QPTLakc=; b=HUk0vDadyyvn9TWYmV89p5lSjvUMG63KI0NfoULkVegJ2wTJuFrF5pX0lzxI2nAVKg ixfGlqwoYPSkPKqzq8VNm6eIl5CdyrH4TQI9KxSwqNgkj2rylw3yylGMheR9LUgQ3U0I rU9iNT9qXB07DkrUno170HCzA0iI869yjB/Zs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cvRkZzylpccO4n3sFiEt4kh2YWk5/bo+faK+QPTLakc=; b=SB/51cI8/ILmP0nSyZCVTD1VMNJ+pItTcaFqTOydbUBsL0iXoWRFDnfagQo8+Qxx4R lDPN4CA47IFIaUvWm0yZk5B5OPfVyf2WzxOtek2HVDiDxz6kYpX/Hy+9umrVuLnQq4sy dUSIMpsNFFUMrIhqzs63oLG2mbiK1ZBc8YSyK+Bk8jyulx1jWF6a0T38xG6PduaztyFG biVjHFrdPB0lrIPGTM/Zf2LBVgJPAY0yO+97fs5ygpA8A7g1oLaWe83ZTL5r/0u7NMXz oa6AKrV9kaijxlPb+eMS8ZqFJeImyDarTJKjNDh4qifOurzItceu5Lzxq1gtqIJyr8Wo 9Lqw== X-Gm-Message-State: ABuFfognjhHgWBtnUbCZytVb92GU1o+T3MqZXKANQ0LPxkMvdfVYiaR1 d/Sos/hboZsjxIx0LSeE0uARapmO57U= X-Google-Smtp-Source: ACcGV60HzxQNI8RV/b7SDGjWcGk1KE0imVylQqPpv1qDYa6H6+TZ7nb4A9RgqG2n55By3Bbc2DKrgw== X-Received: by 2002:a62:509a:: with SMTP id g26-v6mr3076239pfj.62.1539291153937; Thu, 11 Oct 2018 13:52:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:52:03 -0700 Message-Id: <20181011205206.3552-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::530 Subject: [Qemu-devel] [PATCH 17/20] target/arm: Use gvec for NEON VLD all lanes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/translate.c | 81 ++++++++++++++---------------------------- 1 file changed, 26 insertions(+), 55 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index a9bd93bba1..1e79a1eec0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2993,19 +2993,6 @@ static void gen_vfp_msr(TCGv_i32 tmp) tcg_temp_free_i32(tmp); } =20 -static void gen_neon_dup_u8(TCGv_i32 var, int shift) -{ - TCGv_i32 tmp =3D tcg_temp_new_i32(); - if (shift) - tcg_gen_shri_i32(var, var, shift); - tcg_gen_ext8u_i32(var, var); - tcg_gen_shli_i32(tmp, var, 8); - tcg_gen_or_i32(var, var, tmp); - tcg_gen_shli_i32(tmp, var, 16); - tcg_gen_or_i32(var, var, tmp); - tcg_temp_free_i32(tmp); -} - static void gen_neon_dup_low16(TCGv_i32 var) { TCGv_i32 tmp =3D tcg_temp_new_i32(); @@ -3024,28 +3011,6 @@ static void gen_neon_dup_high16(TCGv_i32 var) tcg_temp_free_i32(tmp); } =20 -static TCGv_i32 gen_load_and_replicate(DisasContext *s, TCGv_i32 addr, int= size) -{ - /* Load a single Neon element and replicate into a 32 bit TCG reg */ - TCGv_i32 tmp =3D tcg_temp_new_i32(); - switch (size) { - case 0: - gen_aa32_ld8u(s, tmp, addr, get_mem_index(s)); - gen_neon_dup_u8(tmp, 0); - break; - case 1: - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); - gen_neon_dup_low16(tmp); - break; - case 2: - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - break; - default: /* Avoid compiler warnings. */ - abort(); - } - return tmp; -} - static int handle_vsel(uint32_t insn, uint32_t rd, uint32_t rn, uint32_t r= m, uint32_t dp) { @@ -4949,6 +4914,7 @@ static int disas_neon_ls_insn(DisasContext *s, uint32= _t insn) int load; int shift; int n; + int vec_size; TCGv_i32 addr; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -5118,28 +5084,33 @@ static int disas_neon_ls_insn(DisasContext *s, uint= 32_t insn) } addr =3D tcg_temp_new_i32(); load_reg_var(s, addr, rn); - if (nregs =3D=3D 1) { - /* VLD1 to all lanes: bit 5 indicates how many Dregs to wr= ite */ - tmp =3D gen_load_and_replicate(s, addr, size); - tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0)); - tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1)); - if (insn & (1 << 5)) { - tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 0= )); - tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 1= )); - } - tcg_temp_free_i32(tmp); - } else { - /* VLD2/3/4 to all lanes: bit 5 indicates register stride = */ - stride =3D (insn & (1 << 5)) ? 2 : 1; - for (reg =3D 0; reg < nregs; reg++) { - tmp =3D gen_load_and_replicate(s, addr, size); - tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0)); - tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1)); - tcg_temp_free_i32(tmp); - tcg_gen_addi_i32(addr, addr, 1 << size); - rd +=3D stride; + + /* VLD1 to all lanes: bit 5 indicates how many Dregs to write. + * VLD2/3/4 to all lanes: bit 5 indicates register stride. + */ + stride =3D insn & (1 << 5) ? 2 : 1; + vec_size =3D nregs =3D=3D 1 ? stride * 8 : 8; + + tmp =3D tcg_temp_new_i32(); + for (reg =3D 0; reg < nregs; reg++) { + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), + s->be_data | size); + if ((rd & 1) && vec_size =3D=3D 16) { + /* We cannot write 16 bytes at once because the + * destination is unaligned. + */ + tcg_gen_gvec_dup_i32(size, neon_reg_offset(rd, 0), + 8, 8, tmp); + tcg_gen_gvec_mov(0, neon_reg_offset(rd + 1, 0), + neon_reg_offset(rd, 0), 8, 8); + } else { + tcg_gen_gvec_dup_i32(size, neon_reg_offset(rd, 0), + vec_size, vec_size, tmp); } + tcg_gen_addi_i32(addr, addr, 1 << size); + rd +=3D stride; } + tcg_temp_free_i32(tmp); tcg_temp_free_i32(addr); stride =3D (1 << size) * nregs; } else { --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539291621037106.16632679069915; Thu, 11 Oct 2018 14:00:21 -0700 (PDT) Received: from localhost ([::1]:37100 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAi44-00048H-Jq for importer@patchew.org; Thu, 11 Oct 2018 17:00:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45122) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhwn-0006pr-Lq for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAhwl-0005ux-Cq for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:41 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:36424) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAhwk-0005d6-Su for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:39 -0400 Received: by mail-pf1-x435.google.com with SMTP id l81-v6so5011983pfg.3 for ; Thu, 11 Oct 2018 13:52:36 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zdE4q8LpLXaAekQeUtxbcMeL3xVr4K+/hq+3vvQudb4=; b=HTk0aGWqHEb2Ayv1X7VXqC4Ag0SmQePwyiWe/bPMe4OVudQ6us0c1HIV/qiXzaYwNV 1UT6cqkEajmhz6ScI8Aez4EoVZzm7Bq1ofubfAp2sf5POhmMu1xdQBXLpsmA4JngPK8s CYy0U7IMDYTOOd7tvXN7ncJaki31mBxzdMH5g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zdE4q8LpLXaAekQeUtxbcMeL3xVr4K+/hq+3vvQudb4=; b=cY164ykhWXtNli6egroK6lzT/ENU0/LF4sExNURXfodbnTJkIz7VcyX/Po49m3JHwZ XW9oC7g70Iqb+/eJmdehoM9gDCv2vwPbE3GbsBX9xxWB2NFsMtO/5/Qk9BN3y3TcpH/T e32lWzxUICAYk0op839O/9koXAwWBvH+2OOjsf+Pigte3MGuJpxMCSSQcUEHb/B6cIVX YUx+CJnggWTjLPGl1bH5dDbD7BG2BEBaeEJYmZMr1FAwtwrKWcMEBwRiiNv8t2r6EK7o QgGrvztuXNcrho1G8u70u9gOJ4QTaUzjskiGJw+S3MnWJb28IuKpYQAf2wZVt01XAvV1 Au6Q== X-Gm-Message-State: ABuFfogCMXn3H6IhhKoa6qIHghPL5BJWZEwRWLsvjz2r1EuLFgDO3Eq+ +ag+G5DeebbSw/s3A1GncLgdsjSlWl8= X-Google-Smtp-Source: ACcGV61rkPtBc9jxzTTdwrvs34FnfGbBR6O8qy6jncEVEB4qAW42K2YxqFEkSbTlFYjGtxEmrXCYYg== X-Received: by 2002:a62:9850:: with SMTP id q77-v6mr3036346pfd.249.1539291155509; Thu, 11 Oct 2018 13:52:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:52:04 -0700 Message-Id: <20181011205206.3552-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::435 Subject: [Qemu-devel] [PATCH 18/20] target/arm: Reorg NEON VLD/VST all elements X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Instead of shifts and masks, use direct loads and stores from the neon register file. Mirror the iteration structure of the ARM pseudocode more closely. Correct the parameters of the VLD2 A2 insn. Signed-off-by: Richard Henderson --- target/arm/translate.c | 170 ++++++++++++++++++----------------------- 1 file changed, 74 insertions(+), 96 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 1e79a1eec0..12a744b3c3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1611,12 +1611,56 @@ static TCGv_i32 neon_load_reg(int reg, int pass) return tmp; } =20 +static void neon_load_element64(TCGv_i64 var, int reg, int ele, TCGMemOp m= op) +{ + long offset =3D neon_element_offset(reg, ele, mop & MO_SIZE); + + switch (mop) { + case MO_UB: + tcg_gen_ld8u_i64(var, cpu_env, offset); + break; + case MO_UW: + tcg_gen_ld16u_i64(var, cpu_env, offset); + break; + case MO_UL: + tcg_gen_ld32u_i64(var, cpu_env, offset); + break; + case MO_Q: + tcg_gen_ld_i64(var, cpu_env, offset); + break; + default: + g_assert_not_reached(); + } +} + static void neon_store_reg(int reg, int pass, TCGv_i32 var) { tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass)); tcg_temp_free_i32(var); } =20 +static void neon_store_element64(int reg, int ele, TCGMemOp size, TCGv_i64= var) +{ + long offset =3D neon_element_offset(reg, ele, size); + + switch (size) { + case MO_8: + tcg_gen_st8_i64(var, cpu_env, offset); + break; + case MO_16: + tcg_gen_st16_i64(var, cpu_env, offset); + break; + case MO_32: + tcg_gen_st32_i64(var, cpu_env, offset); + break; + case MO_64: + tcg_gen_st_i64(var, cpu_env, offset); + break; + default: + g_assert_not_reached(); + } +} + static inline void neon_load_reg64(TCGv_i64 var, int reg) { tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg)); @@ -4885,16 +4929,16 @@ static struct { int interleave; int spacing; } const neon_ls_element_type[11] =3D { - {4, 4, 1}, - {4, 4, 2}, + {1, 4, 1}, + {1, 4, 2}, {4, 1, 1}, - {4, 2, 1}, - {3, 3, 1}, - {3, 3, 2}, + {2, 2, 2}, + {1, 3, 1}, + {1, 3, 2}, {3, 1, 1}, {1, 1, 1}, - {2, 2, 1}, - {2, 2, 2}, + {1, 2, 1}, + {1, 2, 2}, {2, 1, 1} }; =20 @@ -4915,6 +4959,8 @@ static int disas_neon_ls_insn(DisasContext *s, uint32= _t insn) int shift; int n; int vec_size; + int mmu_idx; + TCGMemOp endian; TCGv_i32 addr; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -4936,6 +4982,8 @@ static int disas_neon_ls_insn(DisasContext *s, uint32= _t insn) rn =3D (insn >> 16) & 0xf; rm =3D insn & 0xf; load =3D (insn & (1 << 21)) !=3D 0; + endian =3D s->be_data; + mmu_idx =3D get_mem_index(s); if ((insn & (1 << 23)) =3D=3D 0) { /* Load store all elements. */ op =3D (insn >> 8) & 0xf; @@ -4960,104 +5008,34 @@ static int disas_neon_ls_insn(DisasContext *s, uin= t32_t insn) nregs =3D neon_ls_element_type[op].nregs; interleave =3D neon_ls_element_type[op].interleave; spacing =3D neon_ls_element_type[op].spacing; - if (size =3D=3D 3 && (interleave | spacing) !=3D 1) + if (size =3D=3D 3 && (interleave | spacing) !=3D 1) { return 1; + } + tmp64 =3D tcg_temp_new_i64(); addr =3D tcg_temp_new_i32(); + tmp2 =3D tcg_const_i32(1 << size); load_reg_var(s, addr, rn); - stride =3D (1 << size) * interleave; for (reg =3D 0; reg < nregs; reg++) { - if (interleave > 2 || (interleave =3D=3D 2 && nregs =3D=3D 2))= { - load_reg_var(s, addr, rn); - tcg_gen_addi_i32(addr, addr, (1 << size) * reg); - } else if (interleave =3D=3D 2 && nregs =3D=3D 4 && reg =3D=3D= 2) { - load_reg_var(s, addr, rn); - tcg_gen_addi_i32(addr, addr, 1 << size); - } - if (size =3D=3D 3) { - tmp64 =3D tcg_temp_new_i64(); - if (load) { - gen_aa32_ld64(s, tmp64, addr, get_mem_index(s)); - neon_store_reg64(tmp64, rd); - } else { - neon_load_reg64(tmp64, rd); - gen_aa32_st64(s, tmp64, addr, get_mem_index(s)); - } - tcg_temp_free_i64(tmp64); - tcg_gen_addi_i32(addr, addr, stride); - } else { - for (pass =3D 0; pass < 2; pass++) { - if (size =3D=3D 2) { - if (load) { - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - neon_store_reg(rd, pass, tmp); - } else { - tmp =3D neon_load_reg(rd, pass); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_gen_addi_i32(addr, addr, stride); - } else if (size =3D=3D 1) { - if (load) { - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); - tcg_gen_addi_i32(addr, addr, stride); - tmp2 =3D tcg_temp_new_i32(); - gen_aa32_ld16u(s, tmp2, addr, get_mem_index(s)= ); - tcg_gen_addi_i32(addr, addr, stride); - tcg_gen_shli_i32(tmp2, tmp2, 16); - tcg_gen_or_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - neon_store_reg(rd, pass, tmp); - } else { - tmp =3D neon_load_reg(rd, pass); - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_shri_i32(tmp2, tmp, 16); - gen_aa32_st16(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - tcg_gen_addi_i32(addr, addr, stride); - gen_aa32_st16(s, tmp2, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp2); - tcg_gen_addi_i32(addr, addr, stride); - } - } else /* size =3D=3D 0 */ { - if (load) { - tmp2 =3D NULL; - for (n =3D 0; n < 4; n++) { - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld8u(s, tmp, addr, get_mem_index(= s)); - tcg_gen_addi_i32(addr, addr, stride); - if (n =3D=3D 0) { - tmp2 =3D tmp; - } else { - tcg_gen_shli_i32(tmp, tmp, n * 8); - tcg_gen_or_i32(tmp2, tmp2, tmp); - tcg_temp_free_i32(tmp); - } - } - neon_store_reg(rd, pass, tmp2); - } else { - tmp2 =3D neon_load_reg(rd, pass); - for (n =3D 0; n < 4; n++) { - tmp =3D tcg_temp_new_i32(); - if (n =3D=3D 0) { - tcg_gen_mov_i32(tmp, tmp2); - } else { - tcg_gen_shri_i32(tmp, tmp2, n * 8); - } - gen_aa32_st8(s, tmp, addr, get_mem_index(s= )); - tcg_temp_free_i32(tmp); - tcg_gen_addi_i32(addr, addr, stride); - } - tcg_temp_free_i32(tmp2); - } + for (n =3D 0; n < 8 >> size; n++) { + int xs; + for (xs =3D 0; xs < interleave; xs++) { + int tt =3D rd + reg + spacing * xs; + + if (load) { + gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | = size); + neon_store_element64(tt, n, size, tmp64); + } else { + neon_load_element64(tmp64, tt, n, size); + gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | = size); } + tcg_gen_add_i32(addr, addr, tmp2); } } - rd +=3D spacing; } tcg_temp_free_i32(addr); - stride =3D nregs * 8; + tcg_temp_free_i32(tmp2); + tcg_temp_free_i64(tmp64); + stride =3D nregs * interleave * 8; } else { size =3D (insn >> 10) & 3; if (size =3D=3D 3) { --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539291936743117.221691403048; Thu, 11 Oct 2018 14:05:36 -0700 (PDT) Received: from localhost ([::1]:37134 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAi9C-00083r-B0 for importer@patchew.org; Thu, 11 Oct 2018 17:05:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45208) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhwq-0006sT-Ca for qemu-devel@nongnu.org; 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AYK/ZIQW1EHNbmquJ4sIeiHZrTd+Lp6TndyiSWMD0Po=; b=gr0wORELwwK5xV0KI3V3fJVbFdlE8Jz2QPrzoZhsjK69/EYPjGpwGmW2WOhBsubeBx z31BWkznaG88KcSdElMR3/9VPabuzB881rfjqzEAhlEzVUSnnkM6JRlfSwM+bgDD8egv nQE/OUJkvB+UN6SFhQFoRtecZpW0NU5RTqvrc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AYK/ZIQW1EHNbmquJ4sIeiHZrTd+Lp6TndyiSWMD0Po=; b=d+hskyr5RJm3r4QgLPJOW1s+9Kc6ANGFsjRYrqnWxskouSgEq+uPf5F/H5+6CkyD2g D6AP/Oop6YfqYTFBz5nN1xC0QKbcKdMGeIgYm0iDOhduNtEf0rXzBoUpXZsGXcFxj8y+ +GjTalQkqDYSFvi3ScKolQ8MLB7SX2S1epjYRxzGAl3zB/UX8z9z9wK56crz4FREgkwh K8i/x22vBWPgrz5rBWP2WLhTmjk4BQIx+i+lNZVzwPnU7QtGrNOPPUWwEipgMaObcN2p L6f/IrYD+971O/6xT0BL5JFPqh/fLZX1rkzuFlQbN006By6+IDkWziP+10Dc9SjEHl1c 2Fkg== X-Gm-Message-State: ABuFfojC+0btmm08Wqad31jZtB7SCmzPjZ7VTLAem1b0teSfd2YmnjHT PyJkhlZeh5XKAouf7rR8rp6DJ8bSkPs= X-Google-Smtp-Source: ACcGV63oJbOJY0xptl46CJrVOhDjM0gUBrj0HblOCayEH1jE8ovlK3NA4gkXHMrIxXEmqDhmNT6Hcg== X-Received: by 2002:a17:902:2:: with SMTP id 2-v6mr3095516pla.178.1539291156975; Thu, 11 Oct 2018 13:52:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:52:05 -0700 Message-Id: <20181011205206.3552-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH 19/20] target/arm: Promote consecutive memory ops for aa32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For a sequence of loads or stores from a single register, little-endian operations can be promoted to an 8-byte op. This can reduce the number of operations by a factor of 8. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/translate.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index 12a744b3c3..09f2d648b7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5011,6 +5011,16 @@ static int disas_neon_ls_insn(DisasContext *s, uint3= 2_t insn) if (size =3D=3D 3 && (interleave | spacing) !=3D 1) { return 1; } + /* For our purposes, bytes are always little-endian. */ + if (size =3D=3D 0) { + endian =3D MO_LE; + } + /* Consecutive little-endian elements from a single register + * can be promoted to a larger little-endian operation. + */ + if (interleave =3D=3D 1 && endian =3D=3D MO_LE) { + size =3D 3; + } tmp64 =3D tcg_temp_new_i64(); addr =3D tcg_temp_new_i32(); tmp2 =3D tcg_const_i32(1 << size); --=20 2.17.1 From nobody Thu Nov 6 03:30:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539291936734403.1687975008289; Thu, 11 Oct 2018 14:05:36 -0700 (PDT) Received: from localhost ([::1]:37135 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAi9C-00084T-L8 for importer@patchew.org; Thu, 11 Oct 2018 17:05:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45236) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gAhwr-0006tM-A5 for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gAhwn-00066o-2N for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:45 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:37227) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gAhwm-0005u6-MY for qemu-devel@nongnu.org; Thu, 11 Oct 2018 16:52:40 -0400 Received: by mail-pl1-x62f.google.com with SMTP id u6-v6so2053111plz.4 for ; Thu, 11 Oct 2018 13:52:39 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id h87-v6sm34707866pfj.78.2018.10.11.13.52.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 11 Oct 2018 13:52:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rDKWSDsHnXKsG+gGOJjJuwO3ik11nLW/phwkZ4yrPio=; b=UNltMMyNo+CYGstCInQvOCgL05VaYyFB4QdLfgpP2dwRvhrmKXOVAiaQ6W8smhw7jK 71dYfjv56ukT9Dy2qaxUXQACOlzyhz2stH/wP5TAqB53Q/j5i3GE9R6wSpQZ1g5VRDDj qRq6aLQyARgcetqqGZjYWfH21re4tzGI7mjm8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rDKWSDsHnXKsG+gGOJjJuwO3ik11nLW/phwkZ4yrPio=; b=Al1Vfe9aIvCSSKvdh5HV0NqhXmTyq+n1L3u4qOP7/sC0OlUZEeaZvUc+EGsBNkh7kh tMXm4uG7nYzYDlE6UYd+enjCVWltdoQ6rjbq4Aoao1Q/smy/jgRg40mPQnDr3yr1D2iZ tb8A3feCq6pc5qWZjacei4LfDs/G0Qc4sg0B9UsKlaV1YD6S54/OjDA9wXXOcvaiCp8n zFNfrirEVtwVZEvT0P57oiVm1XyJ3gdotG50RfUH7H3EBoeNSqbwt3aq0Dop05IoGszj XRI9MBLOT4H0/WEY1vC90ouSK4a8tmJnOLlhoOtFLzyVwRoklqH29iR2yXq3Ct/o96PJ jsTw== X-Gm-Message-State: ABuFfoiBvQ3lOUt2lbcwMhiutgyNTLx8ZuXTt5CfEBb2Y6bC1ZeSPfkd DUtGL+Lhve1OwO/cZhJZnM5rluSwpzg= X-Google-Smtp-Source: ACcGV63DcL0bYUYQcP4V+PdEzvrQ5JrkWQuW2gtmhXnT+dnOm7qsCFiRlC8PFXouTdzvlwhBwARIjw== X-Received: by 2002:a17:902:30a3:: with SMTP id v32-v6mr2949036plb.277.1539291158398; Thu, 11 Oct 2018 13:52:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 11 Oct 2018 13:52:06 -0700 Message-Id: <20181011205206.3552-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181011205206.3552-1-richard.henderson@linaro.org> References: <20181011205206.3552-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62f Subject: [Qemu-devel] [PATCH 20/20] target/arm: Reorg NEON VLD/VST single element to one lane X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Instead of shifts and masks, use direct loads and stores from the neon register file. Signed-off-by: Richard Henderson --- target/arm/translate.c | 92 +++++++++++++++++++++++------------------- 1 file changed, 50 insertions(+), 42 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 09f2d648b7..0b21c2d201 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1611,6 +1611,25 @@ static TCGv_i32 neon_load_reg(int reg, int pass) return tmp; } =20 +static void neon_load_element(TCGv_i32 var, int reg, int ele, TCGMemOp mop) +{ + long offset =3D neon_element_offset(reg, ele, mop & MO_SIZE); + + switch (mop) { + case MO_UB: + tcg_gen_ld8u_i32(var, cpu_env, offset); + break; + case MO_UW: + tcg_gen_ld16u_i32(var, cpu_env, offset); + break; + case MO_UL: + tcg_gen_ld_i32(var, cpu_env, offset); + break; + default: + g_assert_not_reached(); + } +} + static void neon_load_element64(TCGv_i64 var, int reg, int ele, TCGMemOp m= op) { long offset =3D neon_element_offset(reg, ele, mop & MO_SIZE); @@ -1639,6 +1658,25 @@ static void neon_store_reg(int reg, int pass, TCGv_i= 32 var) tcg_temp_free_i32(var); } =20 +static void neon_store_element(int reg, int ele, TCGMemOp size, TCGv_i32 v= ar) +{ + long offset =3D neon_element_offset(reg, ele, size); + + switch (size) { + case MO_8: + tcg_gen_st8_i32(var, cpu_env, offset); + break; + case MO_16: + tcg_gen_st16_i32(var, cpu_env, offset); + break; + case MO_32: + tcg_gen_st_i32(var, cpu_env, offset); + break; + default: + g_assert_not_reached(); + } +} + static void neon_store_element64(int reg, int ele, TCGMemOp size, TCGv_i64= var) { long offset =3D neon_element_offset(reg, ele, size); @@ -4954,9 +4992,7 @@ static int disas_neon_ls_insn(DisasContext *s, uint32= _t insn) int stride; int size; int reg; - int pass; int load; - int shift; int n; int vec_size; int mmu_idx; @@ -5104,18 +5140,18 @@ static int disas_neon_ls_insn(DisasContext *s, uint= 32_t insn) } else { /* Single element. */ int idx =3D (insn >> 4) & 0xf; - pass =3D (insn >> 7) & 1; + int reg_idx; switch (size) { case 0: - shift =3D ((insn >> 5) & 3) * 8; + reg_idx =3D (insn >> 5) & 7; stride =3D 1; break; case 1: - shift =3D ((insn >> 6) & 1) * 16; + reg_idx =3D (insn >> 6) & 3; stride =3D (insn & (1 << 5)) ? 2 : 1; break; case 2: - shift =3D 0; + reg_idx =3D (insn >> 7) & 1; stride =3D (insn & (1 << 6)) ? 2 : 1; break; default: @@ -5155,52 +5191,24 @@ static int disas_neon_ls_insn(DisasContext *s, uint= 32_t insn) */ return 1; } + tmp =3D tcg_temp_new_i32(); addr =3D tcg_temp_new_i32(); load_reg_var(s, addr, rn); for (reg =3D 0; reg < nregs; reg++) { if (load) { - tmp =3D tcg_temp_new_i32(); - switch (size) { - case 0: - gen_aa32_ld8u(s, tmp, addr, get_mem_index(s)); - break; - case 1: - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); - break; - case 2: - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - break; - default: /* Avoid compiler warnings. */ - abort(); - } - if (size !=3D 2) { - tmp2 =3D neon_load_reg(rd, pass); - tcg_gen_deposit_i32(tmp, tmp2, tmp, - shift, size ? 16 : 8); - tcg_temp_free_i32(tmp2); - } - neon_store_reg(rd, pass, tmp); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), + s->be_data | size); + neon_store_element(rd, reg_idx, size, tmp); } else { /* Store */ - tmp =3D neon_load_reg(rd, pass); - if (shift) - tcg_gen_shri_i32(tmp, tmp, shift); - switch (size) { - case 0: - gen_aa32_st8(s, tmp, addr, get_mem_index(s)); - break; - case 1: - gen_aa32_st16(s, tmp, addr, get_mem_index(s)); - break; - case 2: - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - break; - } - tcg_temp_free_i32(tmp); + neon_load_element(tmp, rd, reg_idx, size); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), + s->be_data | size); } rd +=3D stride; tcg_gen_addi_i32(addr, addr, 1 << size); } tcg_temp_free_i32(addr); + tcg_temp_free_i32(tmp); stride =3D nregs * (1 << size); } } --=20 2.17.1