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X-Received-From: 2607:f8b0:4864:20::c33 Subject: [Qemu-devel] [PATCH v6 04/14] target/arm: Swap PMU values before/after migrations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , qemu-devel@nongnu.org, Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Because of the PMU's design, many register accesses have side effects which are inter-related, meaning that the normal method of saving CP registers can result in inconsistent state. These side-effects are largely handled in *op_start and *op_finish functions which can be called globally once before and after the state is saved/restored. By doing this and adding raw read/write functions for the affected registers, we avoid such inconsistencies. Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 6 ++++-- target/arm/machine.c | 19 +++++++++++++++++++ 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8ca4d30797..12c53e54e9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1379,11 +1379,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 0, .access =3D PL0_RW, .accessfn =3D pmreg_access_ccntr, .type =3D ARM_CP_IO, - .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, }, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_ccnt), + .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, + .raw_readfn =3D raw_read, .raw_writefn =3D raw_write, }, #endif { .name =3D "PMCCFILTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 15, .opc2 =3D 7, - .writefn =3D pmccfiltr_write, + .writefn =3D pmccfiltr_write, .raw_writefn =3D raw_write, .access =3D PL0_RW, .accessfn =3D pmreg_access, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.pmccfiltr_el0), diff --git a/target/arm/machine.c b/target/arm/machine.c index ff4ec22bf7..8139b25be5 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -584,6 +584,8 @@ static int cpu_pre_save(void *opaque) { ARMCPU *cpu =3D opaque; =20 + pmccntr_sync(&cpu->env); + if (kvm_enabled()) { if (!write_kvmstate_to_list(cpu)) { /* This should never fail */ @@ -605,6 +607,19 @@ static int cpu_pre_save(void *opaque) return 0; } =20 +static void cpu_post_save(void *opaque) +{ + ARMCPU *cpu =3D opaque; + pmccntr_sync(&cpu->env); +} + +static int cpu_pre_load(void *opaque) +{ + ARMCPU *cpu =3D opaque; + pmccntr_sync(&cpu->env); + return 0; +} + static int cpu_post_load(void *opaque, int version_id) { ARMCPU *cpu =3D opaque; @@ -652,6 +667,8 @@ static int cpu_post_load(void *opaque, int version_id) hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); =20 + pmccntr_sync(&cpu->env); + return 0; } =20 @@ -660,6 +677,8 @@ const VMStateDescription vmstate_arm_cpu =3D { .version_id =3D 22, .minimum_version_id =3D 22, .pre_save =3D cpu_pre_save, + .post_save =3D cpu_post_save, + .pre_load =3D cpu_pre_load, .post_load =3D cpu_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16), --=20 2.19.1