From nobody Sat May 18 03:46:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539107346036338.84617901067804; Tue, 9 Oct 2018 10:49:06 -0700 (PDT) Received: from localhost ([::1]:53135 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9w7s-0004Iz-0v for importer@patchew.org; Tue, 09 Oct 2018 13:48:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52491) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9w5c-00035u-07 for qemu-devel@nongnu.org; Tue, 09 Oct 2018 13:46:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g9w5X-0005nf-7P for qemu-devel@nongnu.org; Tue, 09 Oct 2018 13:46:35 -0400 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]:41747) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g9w5W-0005ge-UL for qemu-devel@nongnu.org; Tue, 09 Oct 2018 13:46:31 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id 9F4D8DD7; Tue, 9 Oct 2018 13:46:07 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Tue, 09 Oct 2018 13:46:07 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id E9E55E48B9; Tue, 9 Oct 2018 13:46:06 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h= from:to:cc:subject:date:message-id:in-reply-to:references; s= mesmtp; bh=KUbVlbJ92K47N4Cu8UgDmZAdkFvrmx6GWBLrerMabfw=; b=DsoXU FF/C3DnlyYgLRdgh+jMXe7YMy4Rrh4KqbPecPIi741JwUdDi4owVZoy687mfmH1M VVEs++hDIc+6y84Jitv8EYg1VW+v0M9w2vApRarmfjz/tyOUJJijmR2A/IU/0k6D ou10PAqsWUcBPCGcTgp5ZNpUFt+LtQqKxB0MBI= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-proxy:x-me-proxy:x-me-sender :x-me-sender:x-sasl-enc; s=fm1; bh=KUbVlbJ92K47N4Cu8UgDmZAdkFvrm x6GWBLrerMabfw=; b=tig5jHF6tAPVc0+phEk8CPz3sqXEUWkAxonnAiBN2rmTy WQhl14qLMySFEu0ispEv6LEzboCjrpdX8DZoxTTj4C8+kW/X3WQFc938ZmtnV6qz VJmG2vtRtY6nojzK/Wi4wi5pgqMtjVzjhZIWDinXV0rCnv5r8UNfztxL5HI/EIk+ 8eAAf1c2u5hR3oVDO6gsQfDxNRr7FMSV1xeY3mKre4yGpD/Z6MQAk2uqAjDiMzvy Zb5Y7u77bgYAzqm9EcYX6KoeWN/1XI8zv2uVZfPAHunylXeSCtU+wy1bJHd7VLao X5M6agqQXHaw8XtJAqqH1BdYh6ESTv2W82nVFlXjg== X-ME-Sender: X-ME-Proxy: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Tue, 9 Oct 2018 13:45:52 -0400 Message-Id: <20181009174557.16125-2-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181009174557.16125-1-cota@braap.org> References: <20181009174557.16125-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.24 Subject: [Qemu-devel] [PATCH v5 1/6] target/alpha: remove tlb_flush from alpha_cpu_initfn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" As far as I can tell tlb_flush does not need to be called this early. tlb_flush is eventually called after the CPU has been realized. This change paves the way to the introduction of tlb_init, which will be called from cpu_exec_realizefn. Signed-off-by: Emilio G. Cota Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/alpha/cpu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index b08078e7fc..a953897fcc 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -201,7 +201,6 @@ static void alpha_cpu_initfn(Object *obj) CPUAlphaState *env =3D &cpu->env; =20 cs->env_ptr =3D env; - tlb_flush(cs); =20 env->lock_addr =3D -1; #if defined(CONFIG_USER_ONLY) --=20 2.17.1 From nobody Sat May 18 03:46:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539107487453456.1912641299398; Tue, 9 Oct 2018 10:51:27 -0700 (PDT) Received: from localhost ([::1]:53150 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9wAI-0006Mj-DH for importer@patchew.org; Tue, 09 Oct 2018 13:51:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52498) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9w5c-00035y-22 for qemu-devel@nongnu.org; Tue, 09 Oct 2018 13:46:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g9w5X-0005nm-9K for qemu-devel@nongnu.org; Tue, 09 Oct 2018 13:46:35 -0400 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]:43247) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g9w5W-0005hF-Vz for qemu-devel@nongnu.org; Tue, 09 Oct 2018 13:46:31 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id 7CF2ADE4; Tue, 9 Oct 2018 13:46:08 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Tue, 09 Oct 2018 13:46:08 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 3F719E49C5; Tue, 9 Oct 2018 13:46:07 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h= from:to:cc:subject:date:message-id:in-reply-to:references; s= mesmtp; bh=Mu2nueOzWHBFSWPVOdHslrJvtg5d6PSCY1NuRp4eB3Y=; b=NhoHJ B1d0ljws1hYVLhUJTlTzftCe0IJyeDokssbHLtDu/6qX16Si+6zlLkchLd4mjx5J 3NbqBlo/KuH2UFEOXJj8w8OJoqaR2BmwhqfesnB/eoMZ4JGW124CS16lW2OpaLWs udVIXImgBG2uVjmYN0NU3syKaW0joYOuSIKxeg= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-proxy:x-me-proxy:x-me-sender :x-me-sender:x-sasl-enc; s=fm1; bh=Mu2nueOzWHBFSWPVOdHslrJvtg5d6 PSCY1NuRp4eB3Y=; b=Z2/INd0S/fVd9WBWfBoRLr6tFvMtOb6y2urMOjEmcPNry ktZyuSo3RfUyyUp3bdNBNmhRgpYvAxzMoacqtLoA9qJ+TQF1KfOVT4kGAspGcihf Aln3YCtsGNri1xB3xL6DP+VOejS95iaTzQpBRrJVmjQFetUh/Q0I3ZdzCPnBlFJZ nJ8rMATBOtSm7v6avKvL3MBJItxIO/fZtk95/SI79Yp780Okl1+A/CylzjQ4vRCO 2Z2bgEQm18/8TYTi/z3S9zM0S0KDeqBDYUus5MENTbBnXhXD690RhMdnfeQ8RdsW VoR9iFQttFth2iNtMT2KGgUtJ0uvZBxpFseG+69Sg== X-ME-Sender: X-ME-Proxy: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Tue, 9 Oct 2018 13:45:53 -0400 Message-Id: <20181009174557.16125-3-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181009174557.16125-1-cota@braap.org> References: <20181009174557.16125-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.24 Subject: [Qemu-devel] [PATCH v5 2/6] target/unicore32: remove tlb_flush from uc32_init_fn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Guan Xuetao , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" As far as I can tell tlb_flush does not need to be called this early. tlb_flush is eventually called after the CPU has been realized. This change paves the way to the introduction of tlb_init, which will be called from cpu_exec_realizefn. Cc: Guan Xuetao Signed-off-by: Emilio G. Cota Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- target/unicore32/cpu.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 68f978d80b..2b49d1ca40 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -116,8 +116,6 @@ static void uc32_cpu_initfn(Object *obj) env->uncached_asr =3D ASR_MODE_PRIV; env->regs[31] =3D 0x03000000; #endif - - tlb_flush(cs); } =20 static const VMStateDescription vmstate_uc32_cpu =3D { --=20 2.17.1 From nobody Sat May 18 03:46:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539107346086849.4598656146468; Tue, 9 Oct 2018 10:49:06 -0700 (PDT) Received: from localhost ([::1]:53136 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9w7u-0004JU-Tl for importer@patchew.org; Tue, 09 Oct 2018 13:48:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52494) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9w5c-00035w-1h for qemu-devel@nongnu.org; Tue, 09 Oct 2018 13:46:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g9w5X-0005o2-CQ for qemu-devel@nongnu.org; Tue, 09 Oct 2018 13:46:35 -0400 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]:33419) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g9w5W-0005gp-Vk for qemu-devel@nongnu.org; Tue, 09 Oct 2018 13:46:31 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id 4081EDE1; Tue, 9 Oct 2018 13:46:08 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Tue, 09 Oct 2018 13:46:08 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 76337E461F; Tue, 9 Oct 2018 13:46:07 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=mesmtp; bh=w2xlButVNr8XvoKsWO1Rb5GETMtFag2s9Hsug8YA1dE=; b=F1TM+ltem6PV sURV9k93/cl6aUomvH8PUF+2DU2EEGQ/u2hnuxdk6iB6TsK+jkGXWH0aMYkcpFez a+99PPle0VrImnT/4vlaiqt0sRp7ApLxojMghvFyYrgt4NFXAgv7FmQs4i/DrNKY cy/kHhDlux6T9OM4KVqPtINvo2RA67A= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=w2xlButVNr8XvoKsWO1Rb5GETMtFag2s9Hsug8YA1 dE=; b=FWgQNVHonMEKGXUZVRM3BjkwY6bB/jhF93Q3vdu14NO+BOF45Z9Qddiep jMargyKbOzEUsfUYqOAspsk2uVAtCYKmf2xJbrkrcz8hedhvCUw9yoy9n6LdnQTH XpuSngbf86ppPRlI2cdPUUqUeY7mEk2Y+3GFFTRm1f6FFrY1mujd9KdxtCCunVRi jgcRsP7q6j1wWNpUridADPRs+sj+B70ryfXvBLoNrqyqoIJ+xKdWBKzlkIalIyBi pUPdg2ZuAdK+ED5aVaOx4hYVB4sFodNi4d09HOMYPaybdVW+P7o91SeTXXNLmHcq MNkTueQHd0fwKz5F0+zmexJ++aeQw== X-ME-Sender: X-ME-Proxy: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Tue, 9 Oct 2018 13:45:54 -0400 Message-Id: <20181009174557.16125-4-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181009174557.16125-1-cota@braap.org> References: <20181009174557.16125-1-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.24 Subject: [Qemu-devel] [PATCH v5 3/6] exec: introduce tlb_init X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Paves the way for the addition of a per-TLB lock. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson --- include/exec/exec-all.h | 8 ++++++++ accel/tcg/cputlb.c | 4 ++++ exec.c | 1 + 3 files changed, 13 insertions(+) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 5f78125582..815e5b1e83 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -99,6 +99,11 @@ void cpu_address_space_init(CPUState *cpu, int asidx, =20 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* cputlb.c */ +/** + * tlb_init - initialize a CPU's TLB + * @cpu: CPU whose TLB should be initialized + */ +void tlb_init(CPUState *cpu); /** * tlb_flush_page: * @cpu: CPU whose TLB should be flushed @@ -258,6 +263,9 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_i= dx, uintptr_t retaddr); #else +static inline void tlb_init(CPUState *cpu) +{ +} static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) { } diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f4702ce91f..502eea2850 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -73,6 +73,10 @@ QEMU_BUILD_BUG_ON(sizeof(target_ulong) > sizeof(run_on_c= pu_data)); QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16); #define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1) =20 +void tlb_init(CPUState *cpu) +{ +} + /* flush_all_helper: run fn across all cpus * * If the wait flag is set then the src cpu's helper will be queued as diff --git a/exec.c b/exec.c index d0821e69aa..4fd831ef06 100644 --- a/exec.c +++ b/exec.c @@ -965,6 +965,7 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) tcg_target_initialized =3D true; cc->tcg_initialize(); } + tlb_init(cpu); =20 #ifndef CONFIG_USER_ONLY if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { --=20 2.17.1 From nobody Sat May 18 03:46:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539107346039989.1898160535458; Tue, 9 Oct 2018 10:49:06 -0700 (PDT) Received: from localhost ([::1]:53134 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9w7t-0004Ip-AW for importer@patchew.org; Tue, 09 Oct 2018 13:48:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52486) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9w5b-00035t-Qg for qemu-devel@nongnu.org; Tue, 09 Oct 2018 13:46:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g9w5W-0005nP-S1 for qemu-devel@nongnu.org; Tue, 09 Oct 2018 13:46:35 -0400 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]:51391) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g9w5V-0005hC-9I for qemu-devel@nongnu.org; Tue, 09 Oct 2018 13:46:30 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id 76719DDA; Tue, 9 Oct 2018 13:46:08 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Tue, 09 Oct 2018 13:46:08 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id ABBF3E4625; Tue, 9 Oct 2018 13:46:07 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=mesmtp; bh=nYzLrBi+6IUI1um7n2y57xEkcc9dZ27eqVYitngjqzo=; b=h5ZIPO8dXLto 4uHkww98Jm7xroHEam7XyCZW2lSt7trjj2372M778M3grEPrO1TmfacduSuJJcvY PKSf4+YZcFm7yk3HREo/JJLpP278XXyR1FxWapNaYBF7fIntDo2w70aSeNFoA2Q2 yuRnr8D4Nzh1YyYlcGc9COhQv5yn2Qo= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=nYzLrBi+6IUI1um7n2y57xEkcc9dZ27eqVYitngjq zo=; b=IT+NKpcVncfb1IPP6nQ7fb7Hk0fWh2Gx7mnzJ9R8odQbbmuWHOFblVj4u WafT1qRad7QQvsUb80Dji+ugkNnl2226d0h7FueJKKeQ9KQH92/PtkFNjtqb10YI ou3q6ivoXIah0MHT+hNM6RnqpwUYgcaQCN1JQb6F0tF9TdcuJrLjxMHLtSzoXGZK gFDRNpRrI1zr0ct85RViclcyCwHwTeXWWqGcua7ip35JSeXB1jjZBzqGM5Xoro2s gl5S4Y11YaPkfpMxnhEGXCjoZfrV0b4H4u+HUN3aGAAjub//zDI+gsUDKq3NINUZ tM4ubkTx/Hxo45Q3bBzm88ad9dv6w== X-ME-Sender: X-ME-Proxy: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Tue, 9 Oct 2018 13:45:55 -0400 Message-Id: <20181009174557.16125-5-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181009174557.16125-1-cota@braap.org> References: <20181009174557.16125-1-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.24 Subject: [Qemu-devel] [PATCH v5 4/6] cputlb: fix assert_cpu_is_self macro X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- accel/tcg/cputlb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 502eea2850..f6b388c961 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -58,9 +58,9 @@ } \ } while (0) =20 -#define assert_cpu_is_self(this_cpu) do { \ +#define assert_cpu_is_self(cpu) do { \ if (DEBUG_TLB_GATE) { \ - g_assert(!cpu->created || qemu_cpu_is_self(cpu)); \ + g_assert(!(cpu)->created || qemu_cpu_is_self(cpu)); \ } \ } while (0) =20 --=20 2.17.1 From nobody Sat May 18 03:46:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539107488964696.6090176891096; Tue, 9 Oct 2018 10:51:28 -0700 (PDT) Received: from localhost ([::1]:53151 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9wAJ-0006N4-O9 for importer@patchew.org; Tue, 09 Oct 2018 13:51:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52493) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9w5c-00035v-14 for qemu-devel@nongnu.org; Tue, 09 Oct 2018 13:46:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g9w5X-0005oc-Vj for qemu-devel@nongnu.org; Tue, 09 Oct 2018 13:46:35 -0400 Received: from wout1-smtp.messagingengine.com ([64.147.123.24]:51177) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g9w5X-0005nU-H8 for qemu-devel@nongnu.org; Tue, 09 Oct 2018 13:46:31 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id A9B14DAF; Tue, 9 Oct 2018 13:46:08 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Tue, 09 Oct 2018 13:46:08 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id E4742E49C7; Tue, 9 Oct 2018 13:46:07 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=mesmtp; bh=zeSLJRIWuk/ZjQKZuY5sB/AvlIBTJt75ISwYSiwR9HQ=; b=rcDnOzM85EHa domDi9xAUXmueGjPWOMG8jksZn/hksRUZmEbmLJ9lnmYK1W8969MctFaqah1uKx+ lilgUMIZcbPMspQzd2W+OCk5QLSDiPKy1AR/HPlqjQsulKn1bc50N96xyNHAMRCC 4PRh1hdABPmgdgeMUwL2HrmGfOolyI4= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=zeSLJRIWuk/ZjQKZuY5sB/AvlIBTJt75ISwYSiwR9 HQ=; b=eTnqS/eEjepuJOUG4v9hjEk4tPB8um3PwDfVy6oeVmVxBwlQD1h6bnOcZ gxmn4g3kra4U+l5z/RSb+QefrvEtAhydkPl62wpr+0ajuImcrYawYfPsFYYT7uMi Gq/GJ9PxuBjbMGKoDQpfoWmGxagipFS9zYhdH1/r1+dYoQjzPyk98RbzclUphojL qH7aOULkmYCYrcR5PdeFFcJ+rD+eLUmjYvliEOqOAPAmK4h3ivtfS9Zl94Rv0L5u 0KTcHbT3CmODtsYUR22BcgxMdJXrUcPMGw/+hv+GOsVWKAflU6yW2Z2eK5ub4/GO oWdjG7pN1dQp/P4Qy1NmSH3soIhCA== X-ME-Sender: X-ME-Proxy: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Tue, 9 Oct 2018 13:45:56 -0400 Message-Id: <20181009174557.16125-6-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181009174557.16125-1-cota@braap.org> References: <20181009174557.16125-1-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.24 Subject: [Qemu-devel] [PATCH v5 5/6] cputlb: serialize tlb updates with env->tlb_lock X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Currently we rely on atomic operations for cross-CPU invalidations. There are two cases that these atomics miss: cross-CPU invalidations can race with either (1) vCPU threads flushing their TLB, which happens via memset, or (2) vCPUs calling tlb_reset_dirty on their TLB, which updates .addr_write with a regular store. This results in undefined behaviour, since we're mixing regular and atomic ops on concurrent accesses. Fix it by using tlb_lock, a per-vCPU lock. All updaters of tlb_table and the corresponding victim cache now hold the lock. The readers that do not hold tlb_lock must use atomic reads when reading .addr_write, since this field can be updated by other threads; the conversion to atomic reads is done in the next patch. Note that an alternative fix would be to expand the use of atomic ops. However, in the case of TLB flushes this would have a huge performance impact, since (1) TLB flushes can happen very frequently and (2) we currently use a full memory barrier to flush each TLB entry, and a TLB has many entries. Instead, acquiring the lock is barely slower than a full memory barrier since it is uncontended, and with a single lock acquisition we can flush the entire TLB. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- include/exec/cpu-defs.h | 3 + accel/tcg/cputlb.c | 155 ++++++++++++++++++++++------------------ 2 files changed, 87 insertions(+), 71 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index a171ffc1a4..4ff62f32bf 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -24,6 +24,7 @@ #endif =20 #include "qemu/host-utils.h" +#include "qemu/thread.h" #include "qemu/queue.h" #ifdef CONFIG_TCG #include "tcg-target.h" @@ -142,6 +143,8 @@ typedef struct CPUIOTLBEntry { =20 #define CPU_COMMON_TLB \ /* The meaning of the MMU modes is defined in the target code. */ \ + /* tlb_lock serializes updates to tlb_table and tlb_v_table */ \ + QemuSpin tlb_lock; \ CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f6b388c961..c2a6190674 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -75,6 +75,9 @@ QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16); =20 void tlb_init(CPUState *cpu) { + CPUArchState *env =3D cpu->env_ptr; + + qemu_spin_init(&env->tlb_lock); } =20 /* flush_all_helper: run fn across all cpus @@ -129,8 +132,17 @@ static void tlb_flush_nocheck(CPUState *cpu) atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); tlb_debug("(count: %zu)\n", tlb_flush_count()); =20 + /* + * tlb_table/tlb_v_table updates from any thread must hold tlb_lock. + * However, updates from the owner thread (as is the case here; see the + * above assert_cpu_is_self) do not need atomic_set because all reads + * that do not hold the lock are performed by the same owner thread. + */ + qemu_spin_lock(&env->tlb_lock); memset(env->tlb_table, -1, sizeof(env->tlb_table)); memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table)); + qemu_spin_unlock(&env->tlb_lock); + cpu_tb_jmp_cache_clear(cpu); =20 env->vtlb_index =3D 0; @@ -182,6 +194,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cp= u, run_on_cpu_data data) =20 tlb_debug("start: mmu_idx:0x%04lx\n", mmu_idx_bitmask); =20 + qemu_spin_lock(&env->tlb_lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { =20 if (test_bit(mmu_idx, &mmu_idx_bitmask)) { @@ -191,6 +204,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cp= u, run_on_cpu_data data) memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[= 0])); } } + qemu_spin_unlock(&env->tlb_lock); =20 cpu_tb_jmp_cache_clear(cpu); =20 @@ -247,19 +261,24 @@ static inline bool tlb_hit_page_anyprot(CPUTLBEntry *= tlb_entry, tlb_hit_page(tlb_entry->addr_code, page); } =20 -static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong pa= ge) +/* Called with tlb_lock held */ +static inline void tlb_flush_entry_locked(CPUTLBEntry *tlb_entry, + target_ulong page) { if (tlb_hit_page_anyprot(tlb_entry, page)) { memset(tlb_entry, -1, sizeof(*tlb_entry)); } } =20 -static inline void tlb_flush_vtlb_page(CPUArchState *env, int mmu_idx, - target_ulong page) +/* Called with tlb_lock held */ +static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_i= dx, + target_ulong page) { int k; + + assert_cpu_is_self(ENV_GET_CPU(env)); for (k =3D 0; k < CPU_VTLB_SIZE; k++) { - tlb_flush_entry(&env->tlb_v_table[mmu_idx][k], page); + tlb_flush_entry_locked(&env->tlb_v_table[mmu_idx][k], page); } } =20 @@ -286,10 +305,12 @@ static void tlb_flush_page_async_work(CPUState *cpu, = run_on_cpu_data data) =20 addr &=3D TARGET_PAGE_MASK; i =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + qemu_spin_lock(&env->tlb_lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); - tlb_flush_vtlb_page(env, mmu_idx, addr); + tlb_flush_entry_locked(&env->tlb_table[mmu_idx][i], addr); + tlb_flush_vtlb_page_locked(env, mmu_idx, addr); } + qemu_spin_unlock(&env->tlb_lock); =20 tb_flush_jmp_cache(cpu, addr); } @@ -326,12 +347,14 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUSt= ate *cpu, tlb_debug("page:%d addr:"TARGET_FMT_lx" mmu_idx:0x%lx\n", page, addr, mmu_idx_bitmap); =20 + qemu_spin_lock(&env->tlb_lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { if (test_bit(mmu_idx, &mmu_idx_bitmap)) { - tlb_flush_entry(&env->tlb_table[mmu_idx][page], addr); - tlb_flush_vtlb_page(env, mmu_idx, addr); + tlb_flush_entry_locked(&env->tlb_table[mmu_idx][page], addr); + tlb_flush_vtlb_page_locked(env, mmu_idx, addr); } } + qemu_spin_unlock(&env->tlb_lock); =20 tb_flush_jmp_cache(cpu, addr); } @@ -454,72 +477,44 @@ void tlb_unprotect_code(ram_addr_t ram_addr) * most usual is detecting writes to code regions which may invalidate * generated code. * - * Because we want other vCPUs to respond to changes straight away we - * update the te->addr_write field atomically. If the TLB entry has - * been changed by the vCPU in the mean time we skip the update. + * Other vCPUs might be reading their TLBs during guest execution, so we u= pdate + * te->addr_write with atomic_set. We don't need to worry about this for + * oversized guests as MTTCG is disabled for them. * - * As this function uses atomic accesses we also need to ensure - * updates to tlb_entries follow the same access rules. We don't need - * to worry about this for oversized guests as MTTCG is disabled for - * them. + * Called with tlb_lock held. */ - -static void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start, - uintptr_t length) +static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry, + uintptr_t start, uintptr_t length) { -#if TCG_OVERSIZED_GUEST uintptr_t addr =3D tlb_entry->addr_write; =20 if ((addr & (TLB_INVALID_MASK | TLB_MMIO | TLB_NOTDIRTY)) =3D=3D 0) { addr &=3D TARGET_PAGE_MASK; addr +=3D tlb_entry->addend; if ((addr - start) < length) { +#if TCG_OVERSIZED_GUEST tlb_entry->addr_write |=3D TLB_NOTDIRTY; - } - } #else - /* paired with atomic_mb_set in tlb_set_page_with_attrs */ - uintptr_t orig_addr =3D atomic_mb_read(&tlb_entry->addr_write); - uintptr_t addr =3D orig_addr; - - if ((addr & (TLB_INVALID_MASK | TLB_MMIO | TLB_NOTDIRTY)) =3D=3D 0) { - addr &=3D TARGET_PAGE_MASK; - addr +=3D atomic_read(&tlb_entry->addend); - if ((addr - start) < length) { - uintptr_t notdirty_addr =3D orig_addr | TLB_NOTDIRTY; - atomic_cmpxchg(&tlb_entry->addr_write, orig_addr, notdirty_add= r); + atomic_set(&tlb_entry->addr_write, + tlb_entry->addr_write | TLB_NOTDIRTY); +#endif } } -#endif } =20 -/* For atomic correctness when running MTTCG we need to use the right - * primitives when copying entries */ -static inline void copy_tlb_helper(CPUTLBEntry *d, CPUTLBEntry *s, - bool atomic_set) +/* + * Called with tlb_lock held. + * Called only from the vCPU context, i.e. the TLB's owner thread. + */ +static inline void copy_tlb_helper_locked(CPUTLBEntry *d, const CPUTLBEntr= y *s) { -#if TCG_OVERSIZED_GUEST *d =3D *s; -#else - if (atomic_set) { - d->addr_read =3D s->addr_read; - d->addr_code =3D s->addr_code; - atomic_set(&d->addend, atomic_read(&s->addend)); - /* Pairs with flag setting in tlb_reset_dirty_range */ - atomic_mb_set(&d->addr_write, atomic_read(&s->addr_write)); - } else { - d->addr_read =3D s->addr_read; - d->addr_write =3D atomic_read(&s->addr_write); - d->addr_code =3D s->addr_code; - d->addend =3D atomic_read(&s->addend); - } -#endif } =20 /* This is a cross vCPU call (i.e. another vCPU resetting the flags of - * the target vCPU). As such care needs to be taken that we don't - * dangerously race with another vCPU update. The only thing actually - * updated is the target TLB entry ->addr_write flags. + * the target vCPU). + * We must take tlb_lock to avoid racing with another vCPU update. The only + * thing actually updated is the target TLB entry ->addr_write flags. */ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) { @@ -528,22 +523,26 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1= , ram_addr_t length) int mmu_idx; =20 env =3D cpu->env_ptr; + qemu_spin_lock(&env->tlb_lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { unsigned int i; =20 for (i =3D 0; i < CPU_TLB_SIZE; i++) { - tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i], - start1, length); + tlb_reset_dirty_range_locked(&env->tlb_table[mmu_idx][i], star= t1, + length); } =20 for (i =3D 0; i < CPU_VTLB_SIZE; i++) { - tlb_reset_dirty_range(&env->tlb_v_table[mmu_idx][i], - start1, length); + tlb_reset_dirty_range_locked(&env->tlb_v_table[mmu_idx][i], st= art1, + length); } } + qemu_spin_unlock(&env->tlb_lock); } =20 -static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vad= dr) +/* Called with tlb_lock held */ +static inline void tlb_set_dirty1_locked(CPUTLBEntry *tlb_entry, + target_ulong vaddr) { if (tlb_entry->addr_write =3D=3D (vaddr | TLB_NOTDIRTY)) { tlb_entry->addr_write =3D vaddr; @@ -562,16 +561,18 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) =20 vaddr &=3D TARGET_PAGE_MASK; i =3D (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + qemu_spin_lock(&env->tlb_lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr); + tlb_set_dirty1_locked(&env->tlb_table[mmu_idx][i], vaddr); } =20 for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { int k; for (k =3D 0; k < CPU_VTLB_SIZE; k++) { - tlb_set_dirty1(&env->tlb_v_table[mmu_idx][k], vaddr); + tlb_set_dirty1_locked(&env->tlb_v_table[mmu_idx][k], vaddr); } } + qemu_spin_unlock(&env->tlb_lock); } =20 /* Our TLB does not support large pages, so remember the area covered by @@ -658,9 +659,6 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, addend =3D (uintptr_t)memory_region_get_ram_ptr(section->mr) + xla= t; } =20 - /* Make sure there's no cached translation for the new page. */ - tlb_flush_vtlb_page(env, mmu_idx, vaddr_page); - code_address =3D address; iotlb =3D memory_region_section_get_iotlb(cpu, section, vaddr_page, paddr_page, xlat, prot, &addre= ss); @@ -668,6 +666,18 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulo= ng vaddr, index =3D (vaddr_page >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); te =3D &env->tlb_table[mmu_idx][index]; =20 + /* + * Hold the TLB lock for the rest of the function. We could acquire/re= lease + * the lock several times in the function, but it is faster to amortiz= e the + * acquisition cost by acquiring it just once. Note that this leads to + * a longer critical section, but this is not a concern since the TLB = lock + * is unlikely to be contended. + */ + qemu_spin_lock(&env->tlb_lock); + + /* Make sure there's no cached translation for the new page. */ + tlb_flush_vtlb_page_locked(env, mmu_idx, vaddr_page); + /* * Only evict the old entry to the victim tlb if it's for a * different page; otherwise just overwrite the stale data. @@ -677,7 +687,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, CPUTLBEntry *tv =3D &env->tlb_v_table[mmu_idx][vidx]; =20 /* Evict the old entry into the victim tlb. */ - copy_tlb_helper(tv, te, true); + copy_tlb_helper_locked(tv, te); env->iotlb_v[mmu_idx][vidx] =3D env->iotlb[mmu_idx][index]; } =20 @@ -729,9 +739,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, } } =20 - /* Pairs with flag setting in tlb_reset_dirty_range */ - copy_tlb_helper(te, &tn, true); - /* atomic_mb_set(&te->addr_write, write_address); */ + copy_tlb_helper_locked(te, &tn); + qemu_spin_unlock(&env->tlb_lock); } =20 /* Add a new TLB entry, but without specifying the memory @@ -895,6 +904,8 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mm= u_idx, size_t index, size_t elt_ofs, target_ulong page) { size_t vidx; + + assert_cpu_is_self(ENV_GET_CPU(env)); for (vidx =3D 0; vidx < CPU_VTLB_SIZE; ++vidx) { CPUTLBEntry *vtlb =3D &env->tlb_v_table[mmu_idx][vidx]; target_ulong cmp =3D *(target_ulong *)((uintptr_t)vtlb + elt_ofs); @@ -903,9 +914,11 @@ static bool victim_tlb_hit(CPUArchState *env, size_t m= mu_idx, size_t index, /* Found entry in victim tlb, swap tlb and iotlb. */ CPUTLBEntry tmptlb, *tlb =3D &env->tlb_table[mmu_idx][index]; =20 - copy_tlb_helper(&tmptlb, tlb, false); - copy_tlb_helper(tlb, vtlb, true); - copy_tlb_helper(vtlb, &tmptlb, true); + qemu_spin_lock(&env->tlb_lock); + copy_tlb_helper_locked(&tmptlb, tlb); + copy_tlb_helper_locked(tlb, vtlb); + copy_tlb_helper_locked(vtlb, &tmptlb); + qemu_spin_unlock(&env->tlb_lock); =20 CPUIOTLBEntry tmpio, *io =3D &env->iotlb[mmu_idx][index]; CPUIOTLBEntry *vio =3D &env->iotlb_v[mmu_idx][vidx]; --=20 2.17.1 From nobody Sat May 18 03:46:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539107657491702.5930723021052; Tue, 9 Oct 2018 10:54:17 -0700 (PDT) Received: from localhost ([::1]:53162 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9wCw-0008SV-3T for importer@patchew.org; Tue, 09 Oct 2018 13:54:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52499) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9w5c-00035z-1y for qemu-devel@nongnu.org; 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s= mesmtp; bh=HPWD5bUv7GWVMZ8NWNA5MQH9lXkmbPRoJrOXATw9tAw=; b=BkHJt u2mumoUkd3GKlQQTQA8D7CSbJ3TFufU4kuOYBBpbQEcV6Fsz5/hDkrSCt3hODyGP yM/kt2+Om/nqxDjJW9+JDGdlBaxgzOxM2Nth0614chyfHMy9x8BlI9/9P17UsHlh 6Yp0W2dleCB15yHXJ0N8osWpmsPQ7I1VOF8PvE= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-proxy:x-me-proxy:x-me-sender :x-me-sender:x-sasl-enc; s=fm1; bh=HPWD5bUv7GWVMZ8NWNA5MQH9lXkmb PRoJrOXATw9tAw=; b=EEs0BCs0fAwtkp6pYjN7sWv4pB1REwuRBKHO8lzYBuuJK OMlTr5IHR4cgJhz9raJvSSupzvlyZqHpNBGdoqT2V5FsLZmURH6HlqhKfceNEQC/ rlS3mbEUnmwLKdh95w8uxsaJziXtvWSOniuhTPkCxFGXPxGKTPjvl95hKxnVWo4u IQUrweTolCWm3hUKtckNIkRmCsO3oGNs+NQIcGjcsBC2HxHrIyZUqwMaXNFmPpnf Tmxd8EFhh80FOpGa3BfH7zru7W7EKsvv7Bu17SsinMrnoK5JaiXL6aABB8mpxbhh mSrx69IVT0krYHt/Ppwn0kM7BHC60OkBnU6Arplug== X-ME-Sender: X-ME-Proxy: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Tue, 9 Oct 2018 13:45:57 -0400 Message-Id: <20181009174557.16125-7-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181009174557.16125-1-cota@braap.org> References: <20181009174557.16125-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.24 Subject: [Qemu-devel] [PATCH v5 6/6] cputlb: read CPUTLBEntry.addr_write atomically X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Updates can come from other threads, so readers that do not take tlb_lock must use atomic_read to avoid undefined behaviour (UB). This and the previous commit result on average in no performance loss, as the following experiments (run on an Intel i7-6700K CPU @ 4.00GHz) show. 1. aarch64 bootup+shutdown test: - Before: Performance counter stats for 'taskset -c 0 ../img/aarch64/die.sh' (10 run= s): 7487.087786 task-clock (msec) # 0.998 CPUs utilized = ( +- 0.12% ) 31,574,905,303 cycles # 4.217 GHz = ( +- 0.12% ) 57,097,908,812 instructions # 1.81 insns per cycl= e ( +- 0.08% ) 10,255,415,367 branches # 1369.747 M/sec = ( +- 0.08% ) 173,278,962 branch-misses # 1.69% of all branche= s ( +- 0.18% ) 7.504481349 seconds time elapsed = ( +- 0.14% ) - After: Performance counter stats for 'taskset -c 0 ../img/aarch64/die.sh' (10 run= s): 7462.441328 task-clock (msec) # 0.998 CPUs utilized = ( +- 0.07% ) 31,478,476,520 cycles # 4.218 GHz = ( +- 0.07% ) 57,017,330,084 instructions # 1.81 insns per cycl= e ( +- 0.05% ) 10,251,929,667 branches # 1373.804 M/sec = ( +- 0.05% ) 173,023,787 branch-misses # 1.69% of all branche= s ( +- 0.11% ) 7.474970463 seconds time elapsed = ( +- 0.07% ) 2. SPEC06int: SPEC06int (test set) [Y axis: Speedup over master] 1.15 +-+----+------+------+------+------+------+-------+------+------+---= ---+------+------+------+----+-+ | = | 1.1 +-+.................................+++.............................= + tlb-lock-v2 (m+++x) +-+ | +++ | +++ = tlb-lock-v3 (spinl|ck) | | +++ | | +++ +++ | = | | 1.05 +-+....+++...........####.........|####.+++.|......|.....###....+++.= ..........+++....###.........+-+ | ### ++#| # |# |# ***### +++### +++#+# | = +++ | #|# ### | 1 +-+++***+#++++####+++#++#++++++++++#++#+*+*++#++++#+#+****+#++++###+= +++###++++###++++#+#++++#+#+++-+ | *+* # #++# *** # #### *** # * *++# ****+# *| * # ****|# = |# # #|# #+# # # | 0.95 +-+..*.*.#....#..#.*|*..#...#..#.*|*..#.*.*..#.*|.*.#.*++*.#.*++*+#.= ****.#....#+#....#.#..++#.#..+-+ | * * # # # *|* # # # *|* # * * # *++* # * * # * * # = * |* # ++# # # # *** # | | * * # ++# # *+* # # # *|* # * * # * * # * * # * * # = *++* # **** # ++# # * * # | 0.9 +-+..*.*.#...|#..#.*.*..#.++#..#.*|*..#.*.*..#.*..*.#.*..*.#.*..*.#.= *..*.#.*.|*.#...|#.#..*.*.#..+-+ | * * # *** # * * # |# # *+* # * * # * * # * * # * * # = * * # *++* # |# # * * # | 0.85 +-+..*.*.#..*|*..#.*.*..#.***..#.*.*..#.*.*..#.*..*.#.*..*.#.*..*.#.= *..*.#.*..*.#.****.#..*.*.#..+-+ | * * # *+* # * * # *|* # * * # * * # * * # * * # * * # = * * # * * # * |* # * * # | | * * # * * # * * # *+* # * * # * * # * * # * * # * * # = * * # * * # * |* # * * # | 0.8 +-+..*.*.#..*.*..#.*.*..#.*.*..#.*.*..#.*.*..#.*..*.#.*..*.#.*..*.#.= *..*.#.*..*.#.*++*.#..*.*.#..+-+ | * * # * * # * * # * * # * * # * * # * * # * * # * * # = * * # * * # * * # * * # | 0.75 +-+--***##--***###-***###-***###-***###-***###-****##-****##-****##-= ****##-****##-****##--***##--+-+ 400.perlben401.bzip2403.gcc429.m445.gob456.hmme45462.libqua464.h26471.omne= t473483.xalancbmkgeomean png: https://imgur.com/a/BHzpPTW Notes: - tlb-lock-v2 corresponds to an implementation with a mutex. - tlb-lock-v3 is the current patch series, i.e. with a spinlock and a single lock acquisition in tlb_set_page_with_attrs. Signed-off-by: Emilio G. Cota --- accel/tcg/softmmu_template.h | 16 ++++++++++------ include/exec/cpu_ldst.h | 2 +- include/exec/cpu_ldst_template.h | 2 +- accel/tcg/cputlb.c | 15 +++++++++------ 4 files changed, 21 insertions(+), 14 deletions(-) diff --git a/accel/tcg/softmmu_template.h b/accel/tcg/softmmu_template.h index f060a693d4..1e50263871 100644 --- a/accel/tcg/softmmu_template.h +++ b/accel/tcg/softmmu_template.h @@ -277,7 +277,8 @@ void helper_le_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, { unsigned mmu_idx =3D get_mmuidx(oi); int index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write; + target_ulong tlb_addr =3D + atomic_read(&env->tlb_table[mmu_idx][index].addr_write); unsigned a_bits =3D get_alignment_bits(get_memop(oi)); uintptr_t haddr; =20 @@ -292,7 +293,8 @@ void helper_le_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, mmu_idx, retaddr); } - tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVA= LID_MASK; + tlb_addr =3D atomic_read(&env->tlb_table[mmu_idx][index].addr_writ= e) & + ~TLB_INVALID_MASK; } =20 /* Handle an IO access. */ @@ -321,7 +323,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, cannot evict the first. */ page2 =3D (addr + DATA_SIZE) & TARGET_PAGE_MASK; index2 =3D (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - tlb_addr2 =3D env->tlb_table[mmu_idx][index2].addr_write; + tlb_addr2 =3D atomic_read(&env->tlb_table[mmu_idx][index2].addr_wr= ite); if (!tlb_hit_page(tlb_addr2, page2) && !VICTIM_TLB_HIT(addr_write, page2)) { tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE, @@ -354,7 +356,8 @@ void helper_be_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, { unsigned mmu_idx =3D get_mmuidx(oi); int index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write; + target_ulong tlb_addr =3D + atomic_read(&env->tlb_table[mmu_idx][index].addr_write); unsigned a_bits =3D get_alignment_bits(get_memop(oi)); uintptr_t haddr; =20 @@ -369,7 +372,8 @@ void helper_be_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, mmu_idx, retaddr); } - tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVA= LID_MASK; + tlb_addr =3D atomic_read(&env->tlb_table[mmu_idx][index].addr_writ= e) & + ~TLB_INVALID_MASK; } =20 /* Handle an IO access. */ @@ -398,7 +402,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, cannot evict the first. */ page2 =3D (addr + DATA_SIZE) & TARGET_PAGE_MASK; index2 =3D (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - tlb_addr2 =3D env->tlb_table[mmu_idx][index2].addr_write; + tlb_addr2 =3D atomic_read(&env->tlb_table[mmu_idx][index2].addr_wr= ite); if (!tlb_hit_page(tlb_addr2, page2) && !VICTIM_TLB_HIT(addr_write, page2)) { tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE, diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 41ed0526e2..9581587ce1 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -426,7 +426,7 @@ static inline void *tlb_vaddr_to_host(CPUArchState *env= , abi_ptr addr, tlb_addr =3D tlbentry->addr_read; break; case 1: - tlb_addr =3D tlbentry->addr_write; + tlb_addr =3D atomic_read(&tlbentry->addr_write); break; case 2: tlb_addr =3D tlbentry->addr_code; diff --git a/include/exec/cpu_ldst_template.h b/include/exec/cpu_ldst_templ= ate.h index 4db2302962..ba7a11123c 100644 --- a/include/exec/cpu_ldst_template.h +++ b/include/exec/cpu_ldst_template.h @@ -176,7 +176,7 @@ glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArc= hState *env, addr =3D ptr; page_index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx =3D CPU_MMU_INDEX; - if (unlikely(env->tlb_table[mmu_idx][page_index].addr_write !=3D + if (unlikely(atomic_read(&env->tlb_table[mmu_idx][page_index].addr_wri= te) !=3D (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) { oi =3D make_memop_idx(SHIFT, mmu_idx); glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(env, addr, v, oi, diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c2a6190674..200444142a 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -257,7 +257,7 @@ static inline bool tlb_hit_page_anyprot(CPUTLBEntry *tl= b_entry, target_ulong page) { return tlb_hit_page(tlb_entry->addr_read, page) || - tlb_hit_page(tlb_entry->addr_write, page) || + tlb_hit_page(atomic_read(&tlb_entry->addr_write), page) || tlb_hit_page(tlb_entry->addr_code, page); } =20 @@ -859,7 +859,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry = *iotlbentry, tlb_fill(cpu, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); =20 index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write; + tlb_addr =3D atomic_read(&env->tlb_table[mmu_idx][index].addr_writ= e); if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) { /* RAM access */ uintptr_t haddr =3D addr + env->tlb_table[mmu_idx][index].adde= nd; @@ -908,7 +908,9 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mm= u_idx, size_t index, assert_cpu_is_self(ENV_GET_CPU(env)); for (vidx =3D 0; vidx < CPU_VTLB_SIZE; ++vidx) { CPUTLBEntry *vtlb =3D &env->tlb_v_table[mmu_idx][vidx]; - target_ulong cmp =3D *(target_ulong *)((uintptr_t)vtlb + elt_ofs); + /* elt_ofs might correspond to .addr_write, so use atomic_read */ + target_ulong cmp =3D + atomic_read((target_ulong *)((uintptr_t)vtlb + elt_ofs)); =20 if (cmp =3D=3D page) { /* Found entry in victim tlb, swap tlb and iotlb. */ @@ -980,7 +982,8 @@ void probe_write(CPUArchState *env, target_ulong addr, = int size, int mmu_idx, uintptr_t retaddr) { int index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr =3D env->tlb_table[mmu_idx][index].addr_write; + target_ulong tlb_addr =3D + atomic_read(&env->tlb_table[mmu_idx][index].addr_write); =20 if (!tlb_hit(tlb_addr, addr)) { /* TLB entry is for a different page */ @@ -1000,7 +1003,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, size_t mmu_idx =3D get_mmuidx(oi); size_t index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); CPUTLBEntry *tlbe =3D &env->tlb_table[mmu_idx][index]; - target_ulong tlb_addr =3D tlbe->addr_write; + target_ulong tlb_addr =3D atomic_read(&tlbe->addr_write); TCGMemOp mop =3D get_memop(oi); int a_bits =3D get_alignment_bits(mop); int s_bits =3D mop & MO_SIZE; @@ -1031,7 +1034,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, tlb_fill(ENV_GET_CPU(env), addr, 1 << s_bits, MMU_DATA_STORE, mmu_idx, retaddr); } - tlb_addr =3D tlbe->addr_write & ~TLB_INVALID_MASK; + tlb_addr =3D atomic_read(&tlbe->addr_write) & ~TLB_INVALID_MASK; } =20 /* Notice an IO access or a needs-MMU-lookup access */ --=20 2.17.1