From nobody Fri Nov 7 13:05:40 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539041424373397.7725508412225; Mon, 8 Oct 2018 16:30:24 -0700 (PDT) Received: from localhost ([::1]:48743 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9eyd-0001qI-RU for importer@patchew.org; Mon, 08 Oct 2018 19:30:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33896) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9ewV-0000fp-N1 for qemu-devel@nongnu.org; Mon, 08 Oct 2018 19:28:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g9ewS-0000V8-Cq for qemu-devel@nongnu.org; Mon, 08 Oct 2018 19:28:03 -0400 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:51653) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g9ewS-0000UD-4g for qemu-devel@nongnu.org; Mon, 08 Oct 2018 19:28:00 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id D9BC621EBD; Mon, 8 Oct 2018 19:27:59 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Mon, 08 Oct 2018 19:27:59 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 8A55B102A0; Mon, 8 Oct 2018 19:27:59 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h= from:to:cc:subject:date:message-id:in-reply-to:references; s= mesmtp; bh=EiCsUJS8wNl3hDLL/xMTw8y56kbrt3sCl5/51kcnehI=; b=lYIhE 9xs0fplH4SeRTOmVo7XPe1cO3mXr5CU4UTbnxdxCQ9JbFxKB+Z+ETmcdcqYBR0+I YhAVIniztIE8rlxR2gYLssy2K4pg1Sl66zWYJ//BZhjpGKpTxeDtVaGnQ8yuelfP KTeKuRTpQVGjfg+raTbft17mhkgK2WAZ3lNY/I= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-proxy:x-me-proxy:x-me-sender :x-me-sender:x-sasl-enc; s=fm3; bh=EiCsUJS8wNl3hDLL/xMTw8y56kbrt 3sCl5/51kcnehI=; b=VZJHgPo4k3SWit8guscAI82VzlraEWGgra28lJMMIbPoe bUlFS6wfOe3iO1Yl5lb7wsjO7kTUccrBz2d4bPVkFc/IOuhASHfqH3aJCIsaTgAe z1Twdmt1OnNC2VhxiidYQ+GXlCea1/3zLktrOVidospD/KcaiT2DxNa4ZIcj+xz8 A4N1Z4//fS7trlVaQvPykMhBGovm2N1tADfjW5jKK2EpSdTjXPqmdjtmb/Y2jU52 zPwrZ2+7qq6jf2tMhdbiK1NkGqNsWKlNN1FtyvUesdIsdK9FlZ+Z3ECPLWt9P/sK 8fXM9mYy74F4mGW5V/s6rjvaTg5GNrJ9LFoPmJ+WA== X-ME-Sender: X-ME-Proxy: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Mon, 8 Oct 2018 19:27:55 -0400 Message-Id: <20181008232756.30704-5-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181008232756.30704-1-cota@braap.org> References: <20181008232756.30704-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.111.4.27 Subject: [Qemu-devel] [RFC v2 4/5] cputlb: track TLB use rate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This paves the way for implementing a dynamically-sized softmmu. Signed-off-by: Emilio G. Cota Reviewed-by: Alex Benn=C3=A9e --- include/exec/cpu-defs.h | 5 +++++ accel/tcg/cputlb.c | 17 ++++++++++++++--- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 87cd015f60..56f1887c7f 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -141,10 +141,15 @@ typedef struct CPUIOTLBEntry { MemTxAttrs attrs; } CPUIOTLBEntry; =20 +typedef struct CPUTLBDesc { + size_t n_used_entries; +} CPUTLBDesc; + #define CPU_COMMON_TLB \ /* The meaning of the MMU modes is defined in the target code. */ \ /* tlb_lock serializes updates to tlb_mask, tlb_table and tlb_v_table = */ \ QemuSpin tlb_lock; \ + CPUTLBDesc tlb_desc[NB_MMU_MODES]; \ /* tlb_mask[i] contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ \ uintptr_t tlb_mask[NB_MMU_MODES]; \ CPUTLBEntry *tlb_table[NB_MMU_MODES]; \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 4dc47e603c..11d6060eb0 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -82,6 +82,7 @@ void tlb_init(CPUState *cpu) for (i =3D 0; i < NB_MMU_MODES; i++) { size_t n_entries =3D CPU_TLB_SIZE; =20 + env->tlb_desc[i].n_used_entries =3D 0; env->tlb_mask[i] =3D (n_entries - 1) << CPU_TLB_ENTRY_BITS; env->tlb_table[i] =3D g_new(CPUTLBEntry, n_entries); env->iotlb[i] =3D g_new0(CPUIOTLBEntry, n_entries); @@ -150,6 +151,7 @@ static void tlb_flush_nocheck(CPUState *cpu) qemu_spin_lock(&env->tlb_lock); for (i =3D 0; i < NB_MMU_MODES; i++) { memset(env->tlb_table[i], -1, sizeof_tlb(env, i)); + env->tlb_desc[i].n_used_entries =3D 0; } memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table)); qemu_spin_unlock(&env->tlb_lock); @@ -213,6 +215,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cp= u, run_on_cpu_data data) =20 memset(env->tlb_table[mmu_idx], -1, sizeof_tlb(env, mmu_idx)); memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[= 0])); + env->tlb_desc[mmu_idx].n_used_entries =3D 0; } } qemu_spin_unlock(&env->tlb_lock); @@ -273,12 +276,14 @@ static inline bool tlb_hit_page_anyprot(CPUTLBEntry *= tlb_entry, } =20 /* Called with tlb_lock held */ -static inline void tlb_flush_entry_locked(CPUTLBEntry *tlb_entry, +static inline bool tlb_flush_entry_locked(CPUTLBEntry *tlb_entry, target_ulong page) { if (tlb_hit_page_anyprot(tlb_entry, page)) { memset(tlb_entry, -1, sizeof(*tlb_entry)); + return true; } + return false; } =20 /* Called with tlb_lock held */ @@ -316,7 +321,9 @@ static void tlb_flush_page_async_work(CPUState *cpu, ru= n_on_cpu_data data) addr &=3D TARGET_PAGE_MASK; qemu_spin_lock(&env->tlb_lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - tlb_flush_entry_locked(tlb_entry(env, mmu_idx, addr), addr); + if (tlb_flush_entry_locked(tlb_entry(env, mmu_idx, addr), addr)) { + env->tlb_desc[mmu_idx].n_used_entries--; + } tlb_flush_vtlb_page_locked(env, mmu_idx, addr); } qemu_spin_unlock(&env->tlb_lock); @@ -358,7 +365,9 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUStat= e *cpu, qemu_spin_lock(&env->tlb_lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { if (test_bit(mmu_idx, &mmu_idx_bitmap)) { - tlb_flush_entry_locked(tlb_entry(env, mmu_idx, addr), addr); + if (tlb_flush_entry_locked(tlb_entry(env, mmu_idx, addr), addr= )) { + env->tlb_desc[mmu_idx].n_used_entries--; + } tlb_flush_vtlb_page_locked(env, mmu_idx, addr); } } @@ -696,6 +705,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, /* Evict the old entry into the victim tlb. */ copy_tlb_helper_locked(tv, te); env->iotlb_v[mmu_idx][vidx] =3D env->iotlb[mmu_idx][index]; + env->tlb_desc[mmu_idx].n_used_entries--; } =20 /* refill the tlb */ @@ -747,6 +757,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, } =20 copy_tlb_helper_locked(te, &tn); + env->tlb_desc[mmu_idx].n_used_entries++; qemu_spin_unlock(&env->tlb_lock); } =20 --=20 2.17.1