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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id r25-v6sm20392913pgm.59.2018.10.08.14.22.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 14:22:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=t5ntcVDQxgIMgTJgAEaytF6rOREVU67yK50aRSjbmKM=; b=CeRGShbCEFg71yMZn3+1X1tFEuL5bW6OfPSPIFDELeUboeojhpXDJ3ER8aIITAPYTG 4rs12Gx2mYt2hMTBAbvsns4BDaN7XQdAC64v0mGfAAxhxqce6Dd5FtjI+CPzuC6qY+Ip tQLDT2rSRcwNFe8huA0y7td+3w52Z/Uu+0UB8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=t5ntcVDQxgIMgTJgAEaytF6rOREVU67yK50aRSjbmKM=; b=Ke/Gd1BXK6wAumIVf50wU+KP16KqnRztKtCDFktqlbSzBKUsNQF2zcXPNuSHxyDDnM s+vlASmtPLpv3ziFxfrIGj9NGJmVdM+59w/xtch/vXFYi8bG9P8M0cggaFiLfu/Ale8U zAlun9v0Q2vuwF3wpxyFlMQSCkP1jN9LMniAHvJjKse4n+r1MpuuaCex7Bd3NlVafR/m kClhzG4bpYPQ8DaPEXkekEwL2hCqfNpIE8d2NwBOY8BHfZf2epSuaekipi38Z2ZPV1aj z69y21j8oNeIo8pNr/FhJXshizoJ6jbvMS7Mp9TTgoUUk29WK8Ej5BnuECLkvCwHVZEr 14cA== X-Gm-Message-State: ABuFfojEWeF+NYqUFP4zDmeoxf/Pqa+oBxlq/MasH1gvrHw8Ph7ggcOV 3TbVfzbOlXOtEW+P3pFrd06rYHMRu+c= X-Google-Smtp-Source: ACcGV60U/9VigbC6/MgZQn96w2tMYoJt+AlJiCY9KNwboyWg3a79hZWtu+7zQCOkNCD9NnVjMftUFA== X-Received: by 2002:a17:902:3324:: with SMTP id a33-v6mr25661544plc.208.1539033729872; Mon, 08 Oct 2018 14:22:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 8 Oct 2018 14:21:56 -0700 Message-Id: <20181008212205.17752-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181008212205.17752-1-richard.henderson@linaro.org> References: <20181008212205.17752-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62d Subject: [Qemu-devel] [PATCH v3 01/10] target/arm: Fix aarch64_sve_change_el wrt EL0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" At present we assert: arm_el_is_aa64: Assertion `el >=3D 1 && el <=3D 3' failed. The comment in arm_el_is_aa64 explains why asking about EL0 without extra information is impossible. Add an extra argument to provide it from the surrounding context. Fixes: 0ab5953b00b3 Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 7 +++++-- target/arm/helper.c | 16 ++++++++++++---- target/arm/op_helper.c | 6 +++++- 3 files changed, 22 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3a2aff1192..54362ddce8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -911,10 +911,13 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f,= CPUState *cs, int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); -void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el); +void aarch64_sve_change_el(CPUARMState *env, int old_el, + int new_el, bool el0_a64); #else static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } -static inline void aarch64_sve_change_el(CPUARMState *env, int o, int n) {= } +static inline void aarch64_sve_change_el(CPUARMState *env, int o, + int n, bool a) +{ } #endif =20 target_ulong do_arm_semihosting(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index c83f7c1109..0efbb5c76c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8374,7 +8374,11 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *c= s) unsigned int new_mode =3D aarch64_pstate_mode(new_el, true); unsigned int cur_el =3D arm_current_el(env); =20 - aarch64_sve_change_el(env, cur_el, new_el); + /* + * Note that new_el can never be 0. If cur_el is 0, then + * el0_a64 is is_a64(), else el0_a64 is ignored. + */ + aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); =20 if (cur_el < new_el) { /* Entry vector offset depends on whether the implemented EL @@ -12791,9 +12795,11 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsig= ned vq) /* * Notice a change in SVE vector size when changing EL. */ -void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el) +void aarch64_sve_change_el(CPUARMState *env, int old_el, + int new_el, bool el0_a64) { int old_len, new_len; + bool old_a64, new_a64; =20 /* Nothing to do if no SVE. */ if (!arm_feature(env, ARM_FEATURE_SVE)) { @@ -12817,9 +12823,11 @@ void aarch64_sve_change_el(CPUARMState *env, int o= ld_el, int new_el) * we already have the correct register contents when encountering the * vq0->vq0 transition between EL0->EL1. */ - old_len =3D (arm_el_is_aa64(env, old_el) && !sve_exception_el(env, old= _el) + old_a64 =3D old_el ? arm_el_is_aa64(env, old_el) : el0_a64; + old_len =3D (old_a64 && !sve_exception_el(env, old_el) ? sve_zcr_len_for_el(env, old_el) : 0); - new_len =3D (arm_el_is_aa64(env, new_el) && !sve_exception_el(env, new= _el) + new_a64 =3D new_el ? arm_el_is_aa64(env, new_el) : el0_a64; + new_len =3D (new_a64 && !sve_exception_el(env, new_el) ? sve_zcr_len_for_el(env, new_el) : 0); =20 /* When changing vector length, clear inaccessible state. */ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index fb15a13e6c..d915579712 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -1101,7 +1101,11 @@ void HELPER(exception_return)(CPUARMState *env) "AArch64 EL%d PC 0x%" PRIx64 "\n", cur_el, new_el, env->pc); } - aarch64_sve_change_el(env, cur_el, new_el); + /* + * Note that cur_el can never be 0. If new_el is 0, then + * el0_a64 is return_to_aa64, else el0_a64 is ignored. + */ + aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); =20 qemu_mutex_lock_iothread(); arm_call_el_change_hook(arm_env_get_cpu(env)); --=20 2.17.1