From nobody Thu Dec 18 22:17:25 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1539008349542315.8594989313027; Mon, 8 Oct 2018 07:19:09 -0700 (PDT) Received: from localhost ([::1]:46453 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9WNF-0006uR-DK for importer@patchew.org; Mon, 08 Oct 2018 10:19:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46254) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g9W5a-0001Gj-Rb for qemu-devel@nongnu.org; Mon, 08 Oct 2018 10:00:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g9W5V-0007DJ-EP for qemu-devel@nongnu.org; Mon, 08 Oct 2018 10:00:50 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51696) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g9W5U-00073I-UM for qemu-devel@nongnu.org; Mon, 08 Oct 2018 10:00:45 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1g9W54-0003g9-70 for qemu-devel@nongnu.org; Mon, 08 Oct 2018 15:00:18 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 8 Oct 2018 14:59:41 +0100 Message-Id: <20181008140004.12612-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181008140004.12612-1-peter.maydell@linaro.org> References: <20181008140004.12612-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 10/33] target/arm: Clear unused predicate bits for LD1RQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson The 16-byte load only uses 16 predicate bits. But while reusing the other load infrastructure, we find other bits that are set and trigger an assert. To avoid this and retain the assert, zero-extend the predicate that we pass to the LD1 helper. Tested-by: Laurent Desnogues Reported-by: Laurent Desnogues Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20181005175350.30752-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-sve.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 667879564f8..4ee3bbca29d 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4765,12 +4765,33 @@ static void do_ldrq(DisasContext *s, int zt, int pg= , TCGv_i64 addr, int msz) unsigned vsz =3D vec_full_reg_size(s); TCGv_ptr t_pg; TCGv_i32 desc; + int poff; =20 /* Load the first quadword using the normal predicated load helpers. = */ desc =3D tcg_const_i32(simd_desc(16, 16, zt)); - t_pg =3D tcg_temp_new_ptr(); =20 - tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); + poff =3D pred_full_reg_offset(s, pg); + if (vsz > 16) { + /* + * Zero-extend the first 16 bits of the predicate into a temporary. + * This avoids triggering an assert making sure we don't have bits + * set within a predicate beyond VQ, but we have lowered VQ to 1 + * for this load operation. + */ + TCGv_i64 tmp =3D tcg_temp_new_i64(); +#ifdef HOST_WORDS_BIGENDIAN + poff +=3D 6; +#endif + tcg_gen_ld16u_i64(tmp, cpu_env, poff); + + poff =3D offsetof(CPUARMState, vfp.preg_tmp); + tcg_gen_st_i64(tmp, cpu_env, poff); + tcg_temp_free_i64(tmp); + } + + t_pg =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr(t_pg, cpu_env, poff); + fns[msz](cpu_env, t_pg, addr, desc); =20 tcg_temp_free_ptr(t_pg); --=20 2.19.0