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Cota" To: qemu-devel@nongnu.org Date: Sat, 6 Oct 2018 17:45:07 -0400 Message-Id: <20181006214508.5331-6-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181006214508.5331-1-cota@braap.org> References: <20181006214508.5331-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.111.4.27 Subject: [Qemu-devel] [RFC 5/6] cpu-defs: define MIN_CPU_TLB_SIZE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pranith Kumar , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Emilio G. Cota --- include/exec/cpu-defs.h | 6 +++--- accel/tcg/cputlb.c | 2 +- tcg/i386/tcg-target.inc.c | 3 ++- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index af9fe04b0b..27b9433976 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -67,7 +67,7 @@ typedef uint64_t target_ulong; #define CPU_TLB_ENTRY_BITS 5 #endif =20 -/* TCG_TARGET_TLB_DISPLACEMENT_BITS is used in CPU_TLB_BITS to ensure that +/* TCG_TARGET_TLB_DISPLACEMENT_BITS is used in MIN_CPU_TLB_BITS to ensure = that * the TLB is not unnecessarily small, but still small enough for the * TLB lookup instruction sequence used by the TCG target. * @@ -89,7 +89,7 @@ typedef uint64_t target_ulong; * 0x18 (the offset of the addend field in each TLB entry) plus the offset * of tlb_table inside env (which is non-trivial but not huge). */ -#define CPU_TLB_BITS \ +#define MIN_CPU_TLB_BITS \ MIN(8, \ TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \ (NB_MMU_MODES <=3D 1 ? 0 : \ @@ -97,7 +97,7 @@ typedef uint64_t target_ulong; NB_MMU_MODES <=3D 4 ? 2 : \ NB_MMU_MODES <=3D 8 ? 3 : 4)) =20 -#define CPU_TLB_SIZE (1 << CPU_TLB_BITS) +#define MIN_CPU_TLB_SIZE (1 << MIN_CPU_TLB_BITS) =20 typedef struct CPUTLBEntry { /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index ed19ac0e40..1ca71ecfc4 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -82,7 +82,7 @@ void tlb_init(CPUState *cpu) for (i =3D 0; i < NB_MMU_MODES; i++) { CPUTLBDesc *desc =3D &env->tlb_desc[i]; =20 - desc->size =3D CPU_TLB_SIZE; + desc->size =3D MIN_CPU_TLB_SIZE; desc->mask =3D (desc->size - 1) << CPU_TLB_ENTRY_BITS; desc->used =3D 0; env->tlb_table[i] =3D g_new(CPUTLBEntry, desc->size); diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index fce6a94e22..60d8ed5264 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1626,7 +1626,8 @@ static inline void tcg_out_tlb_load(TCGContext *s, TC= GReg addrlo, TCGReg addrhi, } if (TCG_TYPE_PTR =3D=3D TCG_TYPE_I64) { hrexw =3D P_REXW; - if (TARGET_PAGE_BITS + CPU_TLB_BITS > 32) { + /* XXX the size here is variable */ + if (TARGET_PAGE_BITS + MIN_CPU_TLB_BITS > 32) { tlbtype =3D TCG_TYPE_I64; tlbrexw =3D P_REXW; } --=20 2.17.1