From nobody Thu Nov 6 01:46:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538862462605322.17567779826095; Sat, 6 Oct 2018 14:47:42 -0700 (PDT) Received: from localhost ([::1]:40450 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g8uQH-0001D0-3t for importer@patchew.org; Sat, 06 Oct 2018 17:47:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34526) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g8uOA-0000An-Eq for qemu-devel@nongnu.org; Sat, 06 Oct 2018 17:45:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g8uO7-0007IA-Vj for qemu-devel@nongnu.org; Sat, 06 Oct 2018 17:45:30 -0400 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:56861) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g8uO7-00075R-Nl for qemu-devel@nongnu.org; Sat, 06 Oct 2018 17:45:27 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id C8D6F21F86; Sat, 6 Oct 2018 17:45:14 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Sat, 06 Oct 2018 17:45:14 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 53C0F102F0; Sat, 6 Oct 2018 17:45:14 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h= from:to:cc:subject:date:message-id:in-reply-to:references; s= mesmtp; bh=nWUhH0ZEtWPptBGY8aybQYU+lkv1B2t+T8Ik9rWB3YA=; b=RQ0Od agxCIEPPGOyW/C4+7bCnTTLvFEHNaXq+u/Ga6GaBXy2FUAL2MV1E7JFj5YzM7EWr 3nrFgOTqgRoGymNJuRjRNcQgMHyAI3yqBTXdjjCeLInNGXpBatoen/Pm5mp9MSRW Hm41wGzhzTdMu7l9vWvPzw4zjSbBc25mO5i7gQ= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-proxy:x-me-proxy:x-me-sender :x-me-sender:x-sasl-enc; s=fm3; bh=nWUhH0ZEtWPptBGY8aybQYU+lkv1B 2t+T8Ik9rWB3YA=; b=bm8n+xJMS9SldpLJ6F3hbgfv1Kb7FF172AET3S24sJ5fo nIOzogmUtD4ZRQbjL3pb/3wNe9pLrDj4HmpdduPdBFm9EeFv4Rhsw4DazBV6CVhT zkREYH3PomtQxELZvYZV6Mu0PRDSuT4QqmJnTQUtpbSjYtkB077KtOmuF7uyiS4t fx0uqBwUwVndnBz6DD+b2taSnbzlBtGkauiUIDls/kpt67Z2JpXweKRWy1zLR/CS MWFQhhXkLc/o5cCfmxzZ8f80XMsdy2bYHgdSJK+1ZKUfEVaAmX4tqj8200YzLLUo bhneKEWmJdIrGWZwwnOX+Cm/wOC2HqtIHJa92UUUQ== X-ME-Sender: X-ME-Proxy: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sat, 6 Oct 2018 17:45:03 -0400 Message-Id: <20181006214508.5331-2-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181006214508.5331-1-cota@braap.org> References: <20181006214508.5331-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.111.4.27 Subject: [Qemu-devel] [RFC 1/6] (XXX) cputlb: separate MMU allocation + run-time sizing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pranith Kumar , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" No dynamic sizing yet, but the indirection is there. XXX: - convert other TCG backends Signed-off-by: Emilio G. Cota --- accel/tcg/softmmu_template.h | 14 +++++---- include/exec/cpu-defs.h | 14 ++++++--- include/exec/cpu_ldst.h | 2 +- include/exec/cpu_ldst_template.h | 6 ++-- accel/tcg/cputlb.c | 49 +++++++++++++++++++++----------- tcg/i386/tcg-target.inc.c | 26 ++++++++--------- 6 files changed, 68 insertions(+), 43 deletions(-) diff --git a/accel/tcg/softmmu_template.h b/accel/tcg/softmmu_template.h index 1e50263871..3f5a0d4017 100644 --- a/accel/tcg/softmmu_template.h +++ b/accel/tcg/softmmu_template.h @@ -112,7 +112,7 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_u= long addr, TCGMemOpIdx oi, uintptr_t retaddr) { unsigned mmu_idx =3D get_mmuidx(oi); - int index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + int index =3D (addr >> TARGET_PAGE_BITS) & (env->tlb_desc[mmu_idx].siz= e - 1); target_ulong tlb_addr =3D env->tlb_table[mmu_idx][index].ADDR_READ; unsigned a_bits =3D get_alignment_bits(get_memop(oi)); uintptr_t haddr; @@ -180,7 +180,7 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_u= long addr, TCGMemOpIdx oi, uintptr_t retaddr) { unsigned mmu_idx =3D get_mmuidx(oi); - int index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + int index =3D (addr >> TARGET_PAGE_BITS) & (env->tlb_desc[mmu_idx].siz= e - 1); target_ulong tlb_addr =3D env->tlb_table[mmu_idx][index].ADDR_READ; unsigned a_bits =3D get_alignment_bits(get_memop(oi)); uintptr_t haddr; @@ -276,7 +276,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) { unsigned mmu_idx =3D get_mmuidx(oi); - int index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + int index =3D (addr >> TARGET_PAGE_BITS) & (env->tlb_desc[mmu_idx].siz= e - 1); target_ulong tlb_addr =3D atomic_read(&env->tlb_table[mmu_idx][index].addr_write); unsigned a_bits =3D get_alignment_bits(get_memop(oi)); @@ -322,7 +322,8 @@ void helper_le_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, is already guaranteed to be filled, and that the second page cannot evict the first. */ page2 =3D (addr + DATA_SIZE) & TARGET_PAGE_MASK; - index2 =3D (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + index2 =3D (page2 >> TARGET_PAGE_BITS) & + (env->tlb_desc[mmu_idx].size - 1); tlb_addr2 =3D atomic_read(&env->tlb_table[mmu_idx][index2].addr_wr= ite); if (!tlb_hit_page(tlb_addr2, page2) && !VICTIM_TLB_HIT(addr_write, page2)) { @@ -355,7 +356,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) { unsigned mmu_idx =3D get_mmuidx(oi); - int index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + int index =3D (addr >> TARGET_PAGE_BITS) & (env->tlb_desc[mmu_idx].siz= e - 1); target_ulong tlb_addr =3D atomic_read(&env->tlb_table[mmu_idx][index].addr_write); unsigned a_bits =3D get_alignment_bits(get_memop(oi)); @@ -401,7 +402,8 @@ void helper_be_st_name(CPUArchState *env, target_ulong = addr, DATA_TYPE val, is already guaranteed to be filled, and that the second page cannot evict the first. */ page2 =3D (addr + DATA_SIZE) & TARGET_PAGE_MASK; - index2 =3D (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + index2 =3D (page2 >> TARGET_PAGE_BITS) & + (env->tlb_desc[mmu_idx].size - 1); tlb_addr2 =3D atomic_read(&env->tlb_table[mmu_idx][index2].addr_wr= ite); if (!tlb_hit_page(tlb_addr2, page2) && !VICTIM_TLB_HIT(addr_write, page2)) { diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 4ff62f32bf..fa95a4257e 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -141,13 +141,19 @@ typedef struct CPUIOTLBEntry { MemTxAttrs attrs; } CPUIOTLBEntry; =20 -#define CPU_COMMON_TLB \ +typedef struct CPUTLBDesc { + size_t size; + size_t mask; /* (.size - 1) << CPU_TLB_ENTRY_BITS for TLB fast path */ +} CPUTLBDesc; + +#define CPU_COMMON_TLB \ /* The meaning of the MMU modes is defined in the target code. */ \ - /* tlb_lock serializes updates to tlb_table and tlb_v_table */ \ + /* tlb_lock serializes updates to tlb_desc, tlb_table and tlb_v_table = */ \ QemuSpin tlb_lock; \ - CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ + CPUTLBDesc tlb_desc[NB_MMU_MODES]; \ + CPUTLBEntry *tlb_table[NB_MMU_MODES]; \ CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ - CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ + CPUIOTLBEntry *iotlb[NB_MMU_MODES]; \ CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ size_t tlb_flush_count; \ target_ulong tlb_flush_addr; \ diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 9581587ce1..df452f5977 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -416,7 +416,7 @@ static inline void *tlb_vaddr_to_host(CPUArchState *env= , abi_ptr addr, #if defined(CONFIG_USER_ONLY) return g2h(addr); #else - int index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + int index =3D (addr >> TARGET_PAGE_BITS) & (env->tlb_desc[mmu_idx].siz= e - 1); CPUTLBEntry *tlbentry =3D &env->tlb_table[mmu_idx][index]; abi_ptr tlb_addr; uintptr_t haddr; diff --git a/include/exec/cpu_ldst_template.h b/include/exec/cpu_ldst_templ= ate.h index ba7a11123c..6ab9909f46 100644 --- a/include/exec/cpu_ldst_template.h +++ b/include/exec/cpu_ldst_template.h @@ -94,8 +94,8 @@ glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArch= State *env, #endif =20 addr =3D ptr; - page_index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx =3D CPU_MMU_INDEX; + page_index =3D (addr >> TARGET_PAGE_BITS) & (env->tlb_desc[mmu_idx].si= ze - 1); if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=3D (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) { oi =3D make_memop_idx(SHIFT, mmu_idx); @@ -132,8 +132,8 @@ glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUAr= chState *env, #endif =20 addr =3D ptr; - page_index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx =3D CPU_MMU_INDEX; + page_index =3D (addr >> TARGET_PAGE_BITS) & (env->tlb_desc[mmu_idx].si= ze - 1); if (unlikely(env->tlb_table[mmu_idx][page_index].ADDR_READ !=3D (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) { oi =3D make_memop_idx(SHIFT, mmu_idx); @@ -174,8 +174,8 @@ glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArc= hState *env, #endif =20 addr =3D ptr; - page_index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx =3D CPU_MMU_INDEX; + page_index =3D (addr >> TARGET_PAGE_BITS) & (env->tlb_desc[mmu_idx].si= ze - 1); if (unlikely(atomic_read(&env->tlb_table[mmu_idx][page_index].addr_wri= te) !=3D (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) { oi =3D make_memop_idx(SHIFT, mmu_idx); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c7608ccdf8..0b51efc374 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -76,8 +76,17 @@ QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16); void tlb_init(CPUState *cpu) { CPUArchState *env =3D cpu->env_ptr; + int i; =20 qemu_spin_init(&env->tlb_lock); + for (i =3D 0; i < NB_MMU_MODES; i++) { + CPUTLBDesc *desc =3D &env->tlb_desc[i]; + + desc->size =3D CPU_TLB_SIZE; + desc->mask =3D (desc->size - 1) << CPU_TLB_ENTRY_BITS; + env->tlb_table[i] =3D g_new(CPUTLBEntry, desc->size); + env->iotlb[i] =3D g_new0(CPUIOTLBEntry, desc->size); + } } =20 /* flush_all_helper: run fn across all cpus @@ -120,6 +129,7 @@ size_t tlb_flush_count(void) static void tlb_flush_nocheck(CPUState *cpu) { CPUArchState *env =3D cpu->env_ptr; + int i; =20 /* The QOM tests will trigger tlb_flushes without setting up TCG * so we bug out here in that case. @@ -139,7 +149,10 @@ static void tlb_flush_nocheck(CPUState *cpu) * that do not hold the lock are performed by the same owner thread. */ qemu_spin_lock(&env->tlb_lock); - memset(env->tlb_table, -1, sizeof(env->tlb_table)); + for (i =3D 0; i < NB_MMU_MODES; i++) { + memset(env->tlb_table[i], -1, + env->tlb_desc[i].size * sizeof(CPUTLBEntry)); + } memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table)); qemu_spin_unlock(&env->tlb_lock); =20 @@ -200,7 +213,8 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cp= u, run_on_cpu_data data) if (test_bit(mmu_idx, &mmu_idx_bitmask)) { tlb_debug("%d\n", mmu_idx); =20 - memset(env->tlb_table[mmu_idx], -1, sizeof(env->tlb_table[0])); + memset(env->tlb_table[mmu_idx], -1, + env->tlb_desc[mmu_idx].size * sizeof(CPUTLBEntry)); memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[= 0])); } } @@ -286,7 +300,6 @@ static void tlb_flush_page_async_work(CPUState *cpu, ru= n_on_cpu_data data) { CPUArchState *env =3D cpu->env_ptr; target_ulong addr =3D (target_ulong) data.target_ptr; - int i; int mmu_idx; =20 assert_cpu_is_self(cpu); @@ -304,9 +317,10 @@ static void tlb_flush_page_async_work(CPUState *cpu, r= un_on_cpu_data data) } =20 addr &=3D TARGET_PAGE_MASK; - i =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); qemu_spin_lock(&env->tlb_lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { + int i =3D (addr >> TARGET_PAGE_BITS) & (env->tlb_desc[mmu_idx].siz= e - 1); + tlb_flush_entry_locked(&env->tlb_table[mmu_idx][i], addr); tlb_flush_vtlb_page_locked(env, mmu_idx, addr); } @@ -339,16 +353,17 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUSt= ate *cpu, target_ulong addr_and_mmuidx =3D (target_ulong) data.target_ptr; target_ulong addr =3D addr_and_mmuidx & TARGET_PAGE_MASK; unsigned long mmu_idx_bitmap =3D addr_and_mmuidx & ALL_MMUIDX_BITS; - int page =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); int mmu_idx; =20 assert_cpu_is_self(cpu); =20 - tlb_debug("page:%d addr:"TARGET_FMT_lx" mmu_idx:0x%lx\n", - page, addr, mmu_idx_bitmap); + tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:0x%lx\n", addr, mmu_idx_bitma= p); =20 qemu_spin_lock(&env->tlb_lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { + int page; + + page =3D (addr >> TARGET_PAGE_BITS) & (env->tlb_desc[mmu_idx].size= - 1); if (test_bit(mmu_idx, &mmu_idx_bitmap)) { tlb_flush_entry_locked(&env->tlb_table[mmu_idx][page], addr); tlb_flush_vtlb_page_locked(env, mmu_idx, addr); @@ -524,7 +539,7 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, = ram_addr_t length) for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { unsigned int i; =20 - for (i =3D 0; i < CPU_TLB_SIZE; i++) { + for (i =3D 0; i < env->tlb_desc[mmu_idx].size; i++) { tlb_reset_dirty_range_locked(&env->tlb_table[mmu_idx][i], star= t1, length); } @@ -551,15 +566,15 @@ static inline void tlb_set_dirty1_locked(CPUTLBEntry = *tlb_entry, void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) { CPUArchState *env =3D cpu->env_ptr; - int i; int mmu_idx; =20 assert_cpu_is_self(cpu); =20 vaddr &=3D TARGET_PAGE_MASK; - i =3D (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); qemu_spin_lock(&env->tlb_lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { + int i =3D (vaddr >> TARGET_PAGE_BITS) & (env->tlb_desc[mmu_idx].si= ze - 1); + tlb_set_dirty1_locked(&env->tlb_table[mmu_idx][i], vaddr); } =20 @@ -660,7 +675,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, iotlb =3D memory_region_section_get_iotlb(cpu, section, vaddr_page, paddr_page, xlat, prot, &addre= ss); =20 - index =3D (vaddr_page >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + index =3D (vaddr_page >> TARGET_PAGE_BITS) & + (env->tlb_desc[mmu_idx].size - 1); te =3D &env->tlb_table[mmu_idx][index]; =20 /* @@ -788,7 +804,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEnt= ry *iotlbentry, =20 tlb_fill(cpu, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); =20 - index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + index =3D (addr >> TARGET_PAGE_BITS) & (env->tlb_desc[mmu_idx].siz= e - 1); tlb_addr =3D env->tlb_table[mmu_idx][index].addr_read; if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) { /* RAM access */ @@ -855,7 +871,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry = *iotlbentry, =20 tlb_fill(cpu, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); =20 - index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + index =3D (addr >> TARGET_PAGE_BITS) & (env->tlb_desc[mmu_idx].siz= e - 1); tlb_addr =3D atomic_read(&env->tlb_table[mmu_idx][index].addr_writ= e); if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) { /* RAM access */ @@ -943,8 +959,8 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, ta= rget_ulong addr) int mmu_idx, index; void *p; =20 - index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx =3D cpu_mmu_index(env, true); + index =3D (addr >> TARGET_PAGE_BITS) & (env->tlb_desc[mmu_idx].size - = 1); if (unlikely(!tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr))= ) { if (!VICTIM_TLB_HIT(addr_code, addr)) { tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0= ); @@ -978,7 +994,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, ta= rget_ulong addr) void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_i= dx, uintptr_t retaddr) { - int index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + int index =3D (addr >> TARGET_PAGE_BITS) & (env->tlb_desc[mmu_idx].siz= e - 1); target_ulong tlb_addr =3D atomic_read(&env->tlb_table[mmu_idx][index].addr_write); =20 @@ -998,7 +1014,8 @@ static void *atomic_mmu_lookup(CPUArchState *env, targ= et_ulong addr, NotDirtyInfo *ndi) { size_t mmu_idx =3D get_mmuidx(oi); - size_t index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + size_t index =3D (addr >> TARGET_PAGE_BITS) & + (env->tlb_desc[mmu_idx].size - 1); CPUTLBEntry *tlbe =3D &env->tlb_table[mmu_idx][index]; target_ulong tlb_addr =3D atomic_read(&tlbe->addr_write); TCGMemOp mop =3D get_memop(oi); diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 436195894b..fce6a94e22 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -330,6 +330,7 @@ static inline int tcg_target_const_match(tcg_target_lon= g val, TCGType type, #define OPC_ARITH_GvEv (0x03) /* ... plus (ARITH_FOO << 3) */ #define OPC_ANDN (0xf2 | P_EXT38) #define OPC_ADD_GvEv (OPC_ARITH_GvEv | (ARITH_ADD << 3)) +#define OPC_AND_GvEv (OPC_ARITH_GvEv | (ARITH_AND << 3)) #define OPC_BLENDPS (0x0c | P_EXT3A | P_DATA16) #define OPC_BSF (0xbc | P_EXT) #define OPC_BSR (0xbd | P_EXT) @@ -1633,6 +1634,15 @@ static inline void tcg_out_tlb_load(TCGContext *s, T= CGReg addrlo, TCGReg addrhi, } =20 tcg_out_mov(s, tlbtype, r0, addrlo); + tcg_out_shifti(s, SHIFT_SHR + tlbrexw, r0, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + + tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0, + offsetof(CPUArchState, tlb_desc[mem_index].mask)); + + tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0, + offsetof(CPUArchState, tlb_table[mem_index])); + /* If the required alignment is at least as large as the access, simply copy the address and mask. For lesser alignments, check that we do= n't cross pages for the complete access. */ @@ -1642,20 +1652,10 @@ static inline void tcg_out_tlb_load(TCGContext *s, = TCGReg addrlo, TCGReg addrhi, tcg_out_modrm_offset(s, OPC_LEA + trexw, r1, addrlo, s_mask - a_ma= sk); } tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; - - tcg_out_shifti(s, SHIFT_SHR + tlbrexw, r0, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tgen_arithi(s, ARITH_AND + trexw, r1, tlb_mask, 0); - tgen_arithi(s, ARITH_AND + tlbrexw, r0, - (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS, 0); - - tcg_out_modrm_sib_offset(s, OPC_LEA + hrexw, r0, TCG_AREG0, r0, 0, - offsetof(CPUArchState, tlb_table[mem_index][0= ]) - + which); =20 /* cmp 0(r0), r1 */ - tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, r1, r0, 0); + tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, r1, r0, which); =20 /* Prepare for both the fast path add of the tlb addend, and the slow path function argument setup. There are two cases worth note: @@ -1672,7 +1672,7 @@ static inline void tcg_out_tlb_load(TCGContext *s, TC= GReg addrlo, TCGReg addrhi, =20 if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { /* cmp 4(r0), addrhi */ - tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, r0, 4); + tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, r0, which + 4); =20 /* jne slow_path */ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); @@ -1684,7 +1684,7 @@ static inline void tcg_out_tlb_load(TCGContext *s, TC= GReg addrlo, TCGReg addrhi, =20 /* add addend(r0), r1 */ tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0, - offsetof(CPUTLBEntry, addend) - which); + offsetof(CPUTLBEntry, addend)); } =20 /* --=20 2.17.1 From nobody Thu Nov 6 01:46:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538862459675318.4184667480275; Sat, 6 Oct 2018 14:47:39 -0700 (PDT) Received: from localhost ([::1]:40449 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g8uQE-0001AB-CF for importer@patchew.org; Sat, 06 Oct 2018 17:47:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34476) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g8uO9-0000AY-09 for qemu-devel@nongnu.org; Sat, 06 Oct 2018 17:45:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g8uO8-0007IZ-3O for qemu-devel@nongnu.org; Sat, 06 Oct 2018 17:45:28 -0400 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:53205) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g8uO7-00075S-S8 for qemu-devel@nongnu.org; Sat, 06 Oct 2018 17:45:27 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id DAED221F8E; Sat, 6 Oct 2018 17:45:14 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Sat, 06 Oct 2018 17:45:14 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 894EC102EC; Sat, 6 Oct 2018 17:45:14 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h= from:to:cc:subject:date:message-id:in-reply-to:references; s= mesmtp; bh=Kks5MRe/oWUrPNG8WtoMLPgvHnBycaeNyuPSOqtMKOc=; b=xhg7V TqH30GlpDWuLFiP6xPcVg8d7bdO1a7sAZyAowt1/l9XTy8QhU5yx76ClzAyYItz/ mZU0wEwA4/YAoGgC3hLw0oF0FqLd6VL+E7SYRYmRwt0SfAlZRJZa8VdJQToCYlIh ohJJ625u+/X09a2Ie3739QKJs7ILAV63OMt8P0= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-proxy:x-me-proxy:x-me-sender :x-me-sender:x-sasl-enc; s=fm3; bh=Kks5MRe/oWUrPNG8WtoMLPgvHnByc aeNyuPSOqtMKOc=; b=pCP36mUVBgU8Q0WIb8ZU+fgXAY90MVyphTb8WNYeY0HIZ Nuhth4qJ/BrmIDdiQ/psP/ZyCuHUVMlSUkolYVEGGbsgpDFFuWpAfpnH+YpE5zjO zaLMs29Go9NIDz/4vE3uKxiMC7IRWUABnpPt3nGxC1jXlwOrGmlAC9+RdmQeyzw3 woWson2C90MXacJBQmY8YZVUSTQnH11DuRh1Gi4uWi7FkAmTB5u5bb28dX6G0K7Q BSQAUipFD1CzHbCyfTuN64V9t9hxrviSW+s2iwcCdng5kl45EAfhMHgCsgbCKJ5t blM9U8sBvwlGIavhXaPJe0Lmx1R5DSCNWp4WEq+Sw== X-ME-Sender: X-ME-Proxy: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sat, 6 Oct 2018 17:45:04 -0400 Message-Id: <20181006214508.5331-3-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181006214508.5331-1-cota@braap.org> References: <20181006214508.5331-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.111.4.27 Subject: [Qemu-devel] [RFC 2/6] cputlb: do not evict invalid entries to the vtlb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pranith Kumar , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently we evict an entry to the victim TLB when it doesn't match the current address. But it could be that there's no match because the current entry is invalid. Do not evict the entry to the vtlb in that case. This change will help us keep track of the TLB's use rate. Signed-off-by: Emilio G. Cota --- include/exec/cpu-all.h | 14 ++++++++++++++ accel/tcg/cputlb.c | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 117d2fbbca..d938dedafc 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -362,6 +362,20 @@ static inline bool tlb_hit(target_ulong tlb_addr, targ= et_ulong addr) return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); } =20 +/** + * tlb_is_valid - return true if at least one of the addresses is valid + * @te: pointer to CPUTLBEntry + * + * This is useful when we don't have a particular address to compare again= st, + * and we just want to know whether any entry holds valid data. + */ +static inline bool tlb_is_valid(const CPUTLBEntry *te) +{ + return !(te->addr_read & TLB_INVALID_MASK) || + !(te->addr_write & TLB_INVALID_MASK) || + !(te->addr_code & TLB_INVALID_MASK); +} + void dump_exec_info(FILE *f, fprintf_function cpu_fprintf); void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf); #endif /* !CONFIG_USER_ONLY */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 0b51efc374..0e2c149d6b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -695,7 +695,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, * Only evict the old entry to the victim tlb if it's for a * different page; otherwise just overwrite the stale data. */ - if (!tlb_hit_page_anyprot(te, vaddr_page)) { + if (!tlb_hit_page_anyprot(te, vaddr_page) && tlb_is_valid(te)) { unsigned vidx =3D env->vtlb_index++ % CPU_VTLB_SIZE; CPUTLBEntry *tv =3D &env->tlb_v_table[mmu_idx][vidx]; =20 --=20 2.17.1 From nobody Thu Nov 6 01:46:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538862456985932.4631015818767; Sat, 6 Oct 2018 14:47:36 -0700 (PDT) Received: from localhost ([::1]:40448 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g8uQB-00019O-9N for importer@patchew.org; Sat, 06 Oct 2018 17:47:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34473) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g8uO8-0000AX-Vj for qemu-devel@nongnu.org; Sat, 06 Oct 2018 17:45:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g8uO5-0007FD-O9 for qemu-devel@nongnu.org; Sat, 06 Oct 2018 17:45:28 -0400 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:38521) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g8uO2-00075d-0k for qemu-devel@nongnu.org; Sat, 06 Oct 2018 17:45:23 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 2FEFE21F11; Sat, 6 Oct 2018 17:45:15 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Sat, 06 Oct 2018 17:45:15 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id BCEDC102F2; Sat, 6 Oct 2018 17:45:14 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h= from:to:cc:subject:date:message-id:in-reply-to:references; s= mesmtp; bh=eM5Llfn3oUKhKDsDOUosXpHekW7oLxN0QGxyMHVJR+c=; b=R6LHD juODKvT2LYdaj6emUjsQdFSbyQmtzTlbUY6mwg0jnN9zWELB/ymu6TZZN4XprqzR V1RT8Qr5sKF0dSPbdygLmvPkRPYsXXbFR+gxNF8IACu0eDs5pcTkMSUuY07QKJzx wmiMHXsE8p7AfkOXfr+JvmAYACvnKPfJnxUYe0= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-proxy:x-me-proxy:x-me-sender :x-me-sender:x-sasl-enc; s=fm3; bh=eM5Llfn3oUKhKDsDOUosXpHekW7oL xN0QGxyMHVJR+c=; b=XdP90tw3sat44EQq519tNIRZKRT0m9HeEw+K2i8r8XOIg qCf/8Mr7aE4rHCqDcNObI2fodtRmKmIdsm5Ya1ICMb7a4JE1+7A7bG86XGOfQ9oK mO7ozvDp6tZwlvTYPXoIq7WUZp5zeDE+fuRwCvP9LUBzYStD6COgi2z/zYz0B1qj xHl6dFOvc57D3ipkN8RlQnYJ7KAPIIyycqtO2X/bOws3/hgx5+p6Ybq6+1+lRCsS LMi3TKITBaf9Ch22ykxSdP4twmA2+dpive5v2BzLUSSfw94EKfzy1n7bZDgZ4rhw 0oJT5Ow7Q6Sel2cfUWdj85/GiOdOC/jDHEv3Lq5kQ== X-ME-Sender: X-ME-Proxy: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sat, 6 Oct 2018 17:45:05 -0400 Message-Id: <20181006214508.5331-4-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181006214508.5331-1-cota@braap.org> References: <20181006214508.5331-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.111.4.27 Subject: [Qemu-devel] [RFC 3/6] cputlb: track TLB use rates X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pranith Kumar , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This paves the way for implementing a dynamically-sized softmmu. Signed-off-by: Emilio G. Cota --- include/exec/cpu-defs.h | 1 + accel/tcg/cputlb.c | 17 ++++++++++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index fa95a4257e..af9fe04b0b 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -144,6 +144,7 @@ typedef struct CPUIOTLBEntry { typedef struct CPUTLBDesc { size_t size; size_t mask; /* (.size - 1) << CPU_TLB_ENTRY_BITS for TLB fast path */ + size_t used; } CPUTLBDesc; =20 #define CPU_COMMON_TLB \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 0e2c149d6b..ed19ac0e40 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -84,6 +84,7 @@ void tlb_init(CPUState *cpu) =20 desc->size =3D CPU_TLB_SIZE; desc->mask =3D (desc->size - 1) << CPU_TLB_ENTRY_BITS; + desc->used =3D 0; env->tlb_table[i] =3D g_new(CPUTLBEntry, desc->size); env->iotlb[i] =3D g_new0(CPUIOTLBEntry, desc->size); } @@ -152,6 +153,7 @@ static void tlb_flush_nocheck(CPUState *cpu) for (i =3D 0; i < NB_MMU_MODES; i++) { memset(env->tlb_table[i], -1, env->tlb_desc[i].size * sizeof(CPUTLBEntry)); + env->tlb_desc[i].used =3D 0; } memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table)); qemu_spin_unlock(&env->tlb_lock); @@ -216,6 +218,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cp= u, run_on_cpu_data data) memset(env->tlb_table[mmu_idx], -1, env->tlb_desc[mmu_idx].size * sizeof(CPUTLBEntry)); memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[= 0])); + env->tlb_desc[mmu_idx].used =3D 0; } } qemu_spin_unlock(&env->tlb_lock); @@ -276,12 +279,14 @@ static inline bool tlb_hit_page_anyprot(CPUTLBEntry *= tlb_entry, } =20 /* Called with tlb_lock held */ -static inline void tlb_flush_entry_locked(CPUTLBEntry *tlb_entry, +static inline bool tlb_flush_entry_locked(CPUTLBEntry *tlb_entry, target_ulong page) { if (tlb_hit_page_anyprot(tlb_entry, page)) { memset(tlb_entry, -1, sizeof(*tlb_entry)); + return true; } + return false; } =20 /* Called with tlb_lock held */ @@ -321,7 +326,9 @@ static void tlb_flush_page_async_work(CPUState *cpu, ru= n_on_cpu_data data) for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { int i =3D (addr >> TARGET_PAGE_BITS) & (env->tlb_desc[mmu_idx].siz= e - 1); =20 - tlb_flush_entry_locked(&env->tlb_table[mmu_idx][i], addr); + if (tlb_flush_entry_locked(&env->tlb_table[mmu_idx][i], addr)) { + env->tlb_desc[mmu_idx].used--; + } tlb_flush_vtlb_page_locked(env, mmu_idx, addr); } qemu_spin_unlock(&env->tlb_lock); @@ -365,7 +372,9 @@ static void tlb_flush_page_by_mmuidx_async_work(CPUStat= e *cpu, =20 page =3D (addr >> TARGET_PAGE_BITS) & (env->tlb_desc[mmu_idx].size= - 1); if (test_bit(mmu_idx, &mmu_idx_bitmap)) { - tlb_flush_entry_locked(&env->tlb_table[mmu_idx][page], addr); + if (tlb_flush_entry_locked(&env->tlb_table[mmu_idx][page], add= r)) { + env->tlb_desc[mmu_idx].used--; + } tlb_flush_vtlb_page_locked(env, mmu_idx, addr); } } @@ -702,6 +711,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, /* Evict the old entry into the victim tlb. */ copy_tlb_helper_locked(tv, te); env->iotlb_v[mmu_idx][vidx] =3D env->iotlb[mmu_idx][index]; + env->tlb_desc[mmu_idx].used--; } =20 /* refill the tlb */ @@ -753,6 +763,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, } =20 copy_tlb_helper_locked(te, &tn); + env->tlb_desc[mmu_idx].used++; qemu_spin_unlock(&env->tlb_lock); } =20 --=20 2.17.1 From nobody Thu Nov 6 01:46:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538862619831400.8628812718375; Sat, 6 Oct 2018 14:50:19 -0700 (PDT) Received: from localhost ([::1]:40457 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g8uSo-000350-Kq for importer@patchew.org; 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Cota" To: qemu-devel@nongnu.org Date: Sat, 6 Oct 2018 17:45:06 -0400 Message-Id: <20181006214508.5331-5-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181006214508.5331-1-cota@braap.org> References: <20181006214508.5331-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.111.4.27 Subject: [Qemu-devel] [RFC 4/6] tcg: define TCG_TARGET_TLB_MAX_INDEX_BITS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pranith Kumar , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Pranith Kumar This paves the way for implementing a dynamically-sized softmmu. Signed-off-by: Pranith Kumar Signed-off-by: Emilio G. Cota --- tcg/aarch64/tcg-target.h | 1 + tcg/arm/tcg-target.h | 1 + tcg/i386/tcg-target.h | 2 ++ tcg/mips/tcg-target.h | 2 ++ tcg/ppc/tcg-target.h | 1 + tcg/s390/tcg-target.h | 1 + tcg/sparc/tcg-target.h | 1 + tcg/tci/tcg-target.h | 1 + 8 files changed, 10 insertions(+) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 9aea1d1771..55af43d55f 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -15,6 +15,7 @@ =20 #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 24 +#define TCG_TARGET_TLB_MAX_INDEX_BITS 32 #undef TCG_TARGET_STACK_GROWSUP =20 typedef enum { diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 94b3578c55..0cd07906b3 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -60,6 +60,7 @@ extern int arm_arch; #undef TCG_TARGET_STACK_GROWSUP #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 +#define TCG_TARGET_TLB_MAX_INDEX_BITS 8 =20 typedef enum { TCG_REG_R0 =3D 0, diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 9fdf37f23c..4e79e0a550 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -200,6 +200,8 @@ extern bool have_avx2; # define TCG_AREG0 TCG_REG_EBP #endif =20 +#define TCG_TARGET_TLB_MAX_INDEX_BITS (32 - CPU_TLB_ENTRY_BITS) + static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { } diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index a8222476f0..b791e2b4cd 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -39,6 +39,8 @@ #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 #define TCG_TARGET_NB_REGS 32 =20 +#define TCG_TARGET_TLB_MAX_INDEX_BITS (16 - CPU_TLB_ENTRY_BITS) + typedef enum { TCG_REG_ZERO =3D 0, TCG_REG_AT, diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index be52ad1d2e..e0ad7c122d 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -34,6 +34,7 @@ #define TCG_TARGET_NB_REGS 32 #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 +#define TCG_TARGET_TLB_MAX_INDEX_BITS 32 =20 typedef enum { TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 6f2b06a7d1..a1e25e13b3 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -27,6 +27,7 @@ =20 #define TCG_TARGET_INSN_UNIT_SIZE 2 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 19 +#define TCG_TARGET_TLB_MAX_INDEX_BITS 32 =20 typedef enum TCGReg { TCG_REG_R0 =3D 0, diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index d8339bf010..72ace760d5 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -29,6 +29,7 @@ =20 #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 +#define TCG_TARGET_TLB_MAX_INDEX_BITS 12 #define TCG_TARGET_NB_REGS 32 =20 typedef enum { diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 26140d78cb..3f28219afc 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -43,6 +43,7 @@ #define TCG_TARGET_INTERPRETER 1 #define TCG_TARGET_INSN_UNIT_SIZE 1 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 +#define TCG_TARGET_TLB_MAX_INDEX_BITS 32 =20 #if UINTPTR_MAX =3D=3D UINT32_MAX # define TCG_TARGET_REG_BITS 32 --=20 2.17.1 From nobody Thu Nov 6 01:46:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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Cota" To: qemu-devel@nongnu.org Date: Sat, 6 Oct 2018 17:45:07 -0400 Message-Id: <20181006214508.5331-6-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181006214508.5331-1-cota@braap.org> References: <20181006214508.5331-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.111.4.27 Subject: [Qemu-devel] [RFC 5/6] cpu-defs: define MIN_CPU_TLB_SIZE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pranith Kumar , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Emilio G. Cota --- include/exec/cpu-defs.h | 6 +++--- accel/tcg/cputlb.c | 2 +- tcg/i386/tcg-target.inc.c | 3 ++- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index af9fe04b0b..27b9433976 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -67,7 +67,7 @@ typedef uint64_t target_ulong; #define CPU_TLB_ENTRY_BITS 5 #endif =20 -/* TCG_TARGET_TLB_DISPLACEMENT_BITS is used in CPU_TLB_BITS to ensure that +/* TCG_TARGET_TLB_DISPLACEMENT_BITS is used in MIN_CPU_TLB_BITS to ensure = that * the TLB is not unnecessarily small, but still small enough for the * TLB lookup instruction sequence used by the TCG target. * @@ -89,7 +89,7 @@ typedef uint64_t target_ulong; * 0x18 (the offset of the addend field in each TLB entry) plus the offset * of tlb_table inside env (which is non-trivial but not huge). */ -#define CPU_TLB_BITS \ +#define MIN_CPU_TLB_BITS \ MIN(8, \ TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \ (NB_MMU_MODES <=3D 1 ? 0 : \ @@ -97,7 +97,7 @@ typedef uint64_t target_ulong; NB_MMU_MODES <=3D 4 ? 2 : \ NB_MMU_MODES <=3D 8 ? 3 : 4)) =20 -#define CPU_TLB_SIZE (1 << CPU_TLB_BITS) +#define MIN_CPU_TLB_SIZE (1 << MIN_CPU_TLB_BITS) =20 typedef struct CPUTLBEntry { /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index ed19ac0e40..1ca71ecfc4 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -82,7 +82,7 @@ void tlb_init(CPUState *cpu) for (i =3D 0; i < NB_MMU_MODES; i++) { CPUTLBDesc *desc =3D &env->tlb_desc[i]; =20 - desc->size =3D CPU_TLB_SIZE; + desc->size =3D MIN_CPU_TLB_SIZE; desc->mask =3D (desc->size - 1) << CPU_TLB_ENTRY_BITS; desc->used =3D 0; env->tlb_table[i] =3D g_new(CPUTLBEntry, desc->size); diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index fce6a94e22..60d8ed5264 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1626,7 +1626,8 @@ static inline void tcg_out_tlb_load(TCGContext *s, TC= GReg addrlo, TCGReg addrhi, } if (TCG_TYPE_PTR =3D=3D TCG_TYPE_I64) { hrexw =3D P_REXW; - if (TARGET_PAGE_BITS + CPU_TLB_BITS > 32) { + /* XXX the size here is variable */ + if (TARGET_PAGE_BITS + MIN_CPU_TLB_BITS > 32) { tlbtype =3D TCG_TYPE_I64; tlbrexw =3D P_REXW; } --=20 2.17.1 From nobody Thu Nov 6 01:46:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153886272021839.81483990864399; Sat, 6 Oct 2018 14:52:00 -0700 (PDT) Received: from localhost ([::1]:40470 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g8uUP-0004PS-1D for importer@patchew.org; Sat, 06 Oct 2018 17:51:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34478) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g8uO9-0000Aa-7g for qemu-devel@nongnu.org; Sat, 06 Oct 2018 17:45:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g8uO7-0007HY-Od for qemu-devel@nongnu.org; Sat, 06 Oct 2018 17:45:29 -0400 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:32909) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g8uO7-0007FH-FG for qemu-devel@nongnu.org; Sat, 06 Oct 2018 17:45:27 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 2118521FB2; Sat, 6 Oct 2018 17:45:15 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Sat, 06 Oct 2018 17:45:16 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 6B859102EC; Sat, 6 Oct 2018 17:45:15 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h= from:to:cc:subject:date:message-id:in-reply-to:references; s= mesmtp; bh=nI4UTKQAvcf5wSbPDepxLgJbirR7QeciBNXzc1sNIrw=; b=fi+gD lGdKwCmDod4TMLFfMp7lTgjmWkVuW0EEWs4Z99Gb5eNnrHoRZa6ccqod1XEUk2JW T+QzZ2l2UayoJcxsdHDP0RADmn68MdOn9TMNCTd4/zFElxkGtCSbBVcZIWVjNxr7 nN9/T4ZWaPnp8nJwV/O0TTN439icO1SyJbZEss= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-proxy:x-me-proxy:x-me-sender :x-me-sender:x-sasl-enc; s=fm3; bh=nI4UTKQAvcf5wSbPDepxLgJbirR7Q eciBNXzc1sNIrw=; b=bMDCs6BkrIMU3OV4llSf2lhWQ+jLEH4EEU5W9VRmw5xED rP7iXwKlTVmM222i0pwrX7kK/asEjJ4F+AiPxIFoxBHGI8mi4m1T/DB7knmGVGSL BNyEaFtM/o9TLCRCglxHWqgrKAGYp+Qm6nnYIuso36rQt3/7qOV/KBne8flcPuDX PmHT3oU1v8y5dOEGMC+eaWrzYXmcLgbFWGZVfho7U4n9H81OrsU9eVWgh9mA44gs xT+have5irBZT2i8eYZiFeObmd0zGnf+L5x2WH67+quefhxG9/KCkBwvllBsjBX7 +T8AxUJz/YN5drV8OlEYGg65aGNh+6jguqSTfxCtQ== X-ME-Sender: X-ME-Proxy: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sat, 6 Oct 2018 17:45:08 -0400 Message-Id: <20181006214508.5331-7-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181006214508.5331-1-cota@braap.org> References: <20181006214508.5331-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.111.4.27 Subject: [Qemu-devel] [RFC 6/6] cputlb: dynamically resize TLBs based on use rate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pranith Kumar , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Perform the resizing only on flushes, otherwise we'd have to take a perf hit by either rehashing the array or unnecessarily flushing it. We grow the array aggressively, and reduce the size more slowly. This accommodates mixed workloads, where some processes might be memory-heavy while others are not. As the following experiments show, this a net perf gain, particularly for memory-heavy workloads. Experiments are run on an Intel i7-6700K CPU @ 4.00GHz. 1. System boot + shudown, debian aarch64: - Before (tb-lock-v3): Performance counter stats for 'taskset -c 0 ../img/aarch64/die.sh' (10 run= s): 7469.363393 task-clock (msec) # 0.998 CPUs utilized = ( +- 0.07% ) 31,507,707,190 cycles # 4.218 GHz = ( +- 0.07% ) 57,101,577,452 instructions # 1.81 insns per cycl= e ( +- 0.08% ) 10,265,531,804 branches # 1374.352 M/sec = ( +- 0.07% ) 173,020,681 branch-misses # 1.69% of all branche= s ( +- 0.10% ) 7.483359063 seconds time elapsed = ( +- 0.08% ) - After: Performance counter stats for 'taskset -c 0 ../img/aarch64/die.sh' (10 run= s): 7185.036730 task-clock (msec) # 0.999 CPUs utilized = ( +- 0.11% ) 30,303,501,143 cycles # 4.218 GHz = ( +- 0.11% ) 54,198,386,487 instructions # 1.79 insns per cycl= e ( +- 0.08% ) 9,726,518,945 branches # 1353.719 M/sec = ( +- 0.08% ) 167,082,307 branch-misses # 1.72% of all branche= s ( +- 0.08% ) 7.195597842 seconds time elapsed = ( +- 0.11% ) That is, a 3.8% improvement. 2. System boot + shutdown, ubuntu 18.04 x86_64: - Before (tb-lock-v3): Performance counter stats for 'taskset -c 0 ../img/x86_64/ubuntu-die.sh -no= graphic' (2 runs): 49971.036482 task-clock (msec) # 0.999 CPUs utilized = ( +- 1.62% ) 210,766,077,140 cycles # 4.218 GHz = ( +- 1.63% ) 428,829,830,790 instructions # 2.03 insns per cycl= e ( +- 0.75% ) 77,313,384,038 branches # 1547.164 M/sec = ( +- 0.54% ) 835,610,706 branch-misses # 1.08% of all branche= s ( +- 2.97% ) 50.003855102 seconds time elapsed = ( +- 1.61% ) - After: Performance counter stats for 'taskset -c 0 ../img/x86_64/ubuntu-die.sh -n= ographic' (2 runs): 50118.124477 task-clock (msec) # 0.999 CPUs utilized = ( +- 4.30% ) 132,396 context-switches # 0.003 M/sec = ( +- 1.20% ) 0 cpu-migrations # 0.000 K/sec = ( +-100.00% ) 167,754 page-faults # 0.003 M/sec = ( +- 0.06% ) 211,414,701,601 cycles # 4.218 GHz = ( +- 4.30% ) stalled-cycles-frontend stalled-cycles-backend 431,618,818,597 instructions # 2.04 insns per cycl= e ( +- 6.40% ) 80,197,256,524 branches # 1600.165 M/sec = ( +- 8.59% ) 794,830,352 branch-misses # 0.99% of all branche= s ( +- 2.05% ) 50.177077175 seconds time elapsed = ( +- 4.23% ) No improvement (within noise range). 3. x86_64 SPEC06int: SPEC06int (test set) [ Y axis: speedup over master ] 8 +-+--+----+----+-----+----+----+----+----+----+----+-----+----+----+--+= -+ | = | | tlb-lock-v3 = | 7 +-+..................$$$...........................+indirection += -+ | $ $ +resizing = | | $ $ = | 6 +-+..................$.$..............................................+= -+ | $ $ = | | $ $ = | 5 +-+..................$.$..............................................+= -+ | $ $ = | | $ $ = | 4 +-+..................$.$..............................................+= -+ | $ $ = | | +++ $ $ = | 3 +-+........$$+.......$.$..............................................+= -+ | $$ $ $ = | | $$ $ $ $$$ = | 2 +-+........$$........$.$.................................$.$..........+= -+ | $$ $ $ $ $ +$$ = | | $$ $$+ $ $ $$$ +$$ $ $ $$$ $$ = | 1 +-+***#$***#$+**#$+**#+$**#+$**##$**##$***#$***#$+**#$+**#+$**#+$**##$+= -+ | * *#$* *#$ **#$ **# $**# $** #$** #$* *#$* *#$ **#$ **# $**# $** #$ = | | * *#$* *#$ **#$ **# $**# $** #$** #$* *#$* *#$ **#$ **# $**# $** #$ = | 0 +-+***#$***#$-**#$-**#$$**#$$**##$**##$***#$***#$-**#$-**#$$**#$$**##$+= -+ 401.bzi403.gc429445.g456.h462.libq464.h471.omne4483.xalancbgeomean png: https://imgur.com/a/b1wn3wc That is, a 1.53x average speedup over master, with a max speedup of 7.13x. Note that "indirection" (i.e. the first patch in this series) incurs no overhead, on average. Signed-off-by: Emilio G. Cota --- include/exec/cpu-defs.h | 1 + accel/tcg/cputlb.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 27b9433976..4d1d6b2b8b 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -145,6 +145,7 @@ typedef struct CPUTLBDesc { size_t size; size_t mask; /* (.size - 1) << CPU_TLB_ENTRY_BITS for TLB fast path */ size_t used; + size_t n_flushes_low_rate; } CPUTLBDesc; =20 #define CPU_COMMON_TLB \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 1ca71ecfc4..afb61e9c2b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -85,6 +85,7 @@ void tlb_init(CPUState *cpu) desc->size =3D MIN_CPU_TLB_SIZE; desc->mask =3D (desc->size - 1) << CPU_TLB_ENTRY_BITS; desc->used =3D 0; + desc->n_flushes_low_rate =3D 0; env->tlb_table[i] =3D g_new(CPUTLBEntry, desc->size); env->iotlb[i] =3D g_new0(CPUIOTLBEntry, desc->size); } @@ -122,6 +123,39 @@ size_t tlb_flush_count(void) return count; } =20 +/* Call with tlb_lock held */ +static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx) +{ + CPUTLBDesc *desc =3D &env->tlb_desc[mmu_idx]; + size_t rate =3D desc->used * 100 / desc->size; + size_t new_size =3D desc->size; + + if (rate =3D=3D 100) { + new_size =3D MIN(desc->size << 2, 1 << TCG_TARGET_TLB_MAX_INDEX_BI= TS); + } else if (rate > 70) { + new_size =3D MIN(desc->size << 1, 1 << TCG_TARGET_TLB_MAX_INDEX_BI= TS); + } else if (rate < 30) { + desc->n_flushes_low_rate++; + if (desc->n_flushes_low_rate =3D=3D 100) { + new_size =3D MAX(desc->size >> 1, 1 << MIN_CPU_TLB_BITS); + desc->n_flushes_low_rate =3D 0; + } + } + + if (new_size =3D=3D desc->size) { + return; + } + + g_free(env->tlb_table[mmu_idx]); + g_free(env->iotlb[mmu_idx]); + + desc->size =3D new_size; + desc->mask =3D (desc->size - 1) << CPU_TLB_ENTRY_BITS; + desc->n_flushes_low_rate =3D 0; + env->tlb_table[mmu_idx] =3D g_new(CPUTLBEntry, desc->size); + env->iotlb[mmu_idx] =3D g_new0(CPUIOTLBEntry, desc->size); +} + /* This is OK because CPU architectures generally permit an * implementation to drop entries from the TLB at any time, so * flushing more entries than required is only an efficiency issue, @@ -151,6 +185,7 @@ static void tlb_flush_nocheck(CPUState *cpu) */ qemu_spin_lock(&env->tlb_lock); for (i =3D 0; i < NB_MMU_MODES; i++) { + tlb_mmu_resize_locked(env, i); memset(env->tlb_table[i], -1, env->tlb_desc[i].size * sizeof(CPUTLBEntry)); env->tlb_desc[i].used =3D 0; @@ -215,6 +250,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cp= u, run_on_cpu_data data) if (test_bit(mmu_idx, &mmu_idx_bitmask)) { tlb_debug("%d\n", mmu_idx); =20 + tlb_mmu_resize_locked(env, mmu_idx); memset(env->tlb_table[mmu_idx], -1, env->tlb_desc[mmu_idx].size * sizeof(CPUTLBEntry)); memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[= 0])); --=20 2.17.1