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X-Received-From: 2607:f8b0:4864:20::242 Subject: [Qemu-devel] [PULL 8/8] softfloat: Specialize udiv_qrnnd for ppc64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ISA has a 128/64-bit division instruction, though it assumes the low 64-bits of the numerator are 0, and so requires a bit more fixup than a full 128-bit division insn. Reviewed-by: David Gibson Signed-off-by: Richard Henderson --- include/fpu/softfloat-macros.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h index eafc68932b..c86687fa5e 100644 --- a/include/fpu/softfloat-macros.h +++ b/include/fpu/softfloat-macros.h @@ -647,6 +647,22 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_= t n1, asm("dlgr %0, %1" : "+r"(n) : "r"(d)); *r =3D n >> 64; return n; +#elif defined(_ARCH_PPC64) + /* From Power ISA 3.0B, programming note for divdeu. */ + uint64_t q1, q2, Q, r1, r2, R; + asm("divdeu %0,%2,%4; divdu %1,%3,%4" + : "=3D&r"(q1), "=3Dr"(q2) + : "r"(n1), "r"(n0), "r"(d)); + r1 =3D -(q1 * d); /* low part of (n1<<64) - (q1 * d) */ + r2 =3D n0 - (q2 * d); + Q =3D q1 + q2; + R =3D r1 + r2; + if (R >=3D d || R < r2) { /* overflow implies R > d */ + Q +=3D 1; + R -=3D d; + } + *r =3D R; + return Q; #else uint64_t d0, d1, q0, q1, r1, r0, m; =20 --=20 2.17.1