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X-Received-From: 2607:f8b0:4864:20::334 Subject: [Qemu-devel] [PATCH v3 06/15] target/arm: Clear unused predicate bits for LD1RQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The 16-byte load only uses 16 predicate bits. But while reusing the other load infrastructure, we find other bits that are set and trigger an assert. To avoid this and retain the assert, zero-extend the predicate that we pass to the LD1 helper. Tested-by: Laurent Desnogues Reported-by: Laurent Desnogues Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 667879564f..4ee3bbca29 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4765,12 +4765,33 @@ static void do_ldrq(DisasContext *s, int zt, int pg= , TCGv_i64 addr, int msz) unsigned vsz =3D vec_full_reg_size(s); TCGv_ptr t_pg; TCGv_i32 desc; + int poff; =20 /* Load the first quadword using the normal predicated load helpers. = */ desc =3D tcg_const_i32(simd_desc(16, 16, zt)); - t_pg =3D tcg_temp_new_ptr(); =20 - tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); + poff =3D pred_full_reg_offset(s, pg); + if (vsz > 16) { + /* + * Zero-extend the first 16 bits of the predicate into a temporary. + * This avoids triggering an assert making sure we don't have bits + * set within a predicate beyond VQ, but we have lowered VQ to 1 + * for this load operation. + */ + TCGv_i64 tmp =3D tcg_temp_new_i64(); +#ifdef HOST_WORDS_BIGENDIAN + poff +=3D 6; +#endif + tcg_gen_ld16u_i64(tmp, cpu_env, poff); + + poff =3D offsetof(CPUARMState, vfp.preg_tmp); + tcg_gen_st_i64(tmp, cpu_env, poff); + tcg_temp_free_i64(tmp); + } + + t_pg =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr(t_pg, cpu_env, poff); + fns[msz](cpu_env, t_pg, addr, desc); =20 tcg_temp_free_ptr(t_pg); --=20 2.17.1