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X-Received-From: 2607:f8b0:4864:20::243 Subject: [Qemu-devel] [PATCH v3 03/15] target/arm: Pass in current_el to fp and sve_exception_el X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We are going to want to determine whether sve is enabled for EL other than current. Tested-by: Laurent Desnogues Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 38a9d32dc4..52fc9d1d4c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4406,12 +4406,10 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = =3D { * take care of raising that exception. * C.f. the ARM pseudocode function CheckSVEEnabled. */ -static int sve_exception_el(CPUARMState *env) +static int sve_exception_el(CPUARMState *env, int el) { #ifndef CONFIG_USER_ONLY - unsigned current_el =3D arm_current_el(env); - - if (current_el <=3D 1) { + if (el <=3D 1) { bool disabled =3D false; =20 /* The CPACR.ZEN controls traps to EL1: @@ -4422,7 +4420,7 @@ static int sve_exception_el(CPUARMState *env) if (!extract32(env->cp15.cpacr_el1, 16, 1)) { disabled =3D true; } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) { - disabled =3D current_el =3D=3D 0; + disabled =3D el =3D=3D 0; } if (disabled) { /* route_to_el2 */ @@ -4435,7 +4433,7 @@ static int sve_exception_el(CPUARMState *env) if (!extract32(env->cp15.cpacr_el1, 20, 1)) { disabled =3D true; } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) { - disabled =3D current_el =3D=3D 0; + disabled =3D el =3D=3D 0; } if (disabled) { return 0; @@ -4445,7 +4443,7 @@ static int sve_exception_el(CPUARMState *env) /* CPTR_EL2. Since TZ and TFP are positive, * they will be zero when EL2 is not present. */ - if (current_el <=3D 2 && !arm_is_secure_below_el3(env)) { + if (el <=3D 2 && !arm_is_secure_below_el3(env)) { if (env->cp15.cptr_el[2] & CPTR_TZ) { return 2; } @@ -12513,11 +12511,10 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t va= l, uint32_t bytes) /* Return the exception level to which FP-disabled exceptions should * be taken, or 0 if FP is enabled. */ -static inline int fp_exception_el(CPUARMState *env) +static int fp_exception_el(CPUARMState *env, int cur_el) { #ifndef CONFIG_USER_ONLY int fpen; - int cur_el =3D arm_current_el(env); =20 /* CPACR and the CPTR registers don't exist before v6, so FP is * always accessible @@ -12580,7 +12577,8 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, target_ulong *cs_base, uint32_t *pflags) { ARMMMUIdx mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, fals= e)); - int fp_el =3D fp_exception_el(env); + int current_el =3D arm_current_el(env); + int fp_el =3D fp_exception_el(env, current_el); uint32_t flags; =20 if (is_a64(env)) { @@ -12591,7 +12589,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, flags |=3D (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT= ); =20 if (arm_feature(env, ARM_FEATURE_SVE)) { - int sve_el =3D sve_exception_el(env); + int sve_el =3D sve_exception_el(env, current_el); uint32_t zcr_len; =20 /* If SVE is disabled, but FP is enabled, @@ -12600,7 +12598,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, if (sve_el !=3D 0 && fp_el =3D=3D 0) { zcr_len =3D 0; } else { - int current_el =3D arm_current_el(env); ARMCPU *cpu =3D arm_env_get_cpu(env); =20 zcr_len =3D cpu->sve_max_vq - 1; --=20 2.17.1