From nobody Thu Nov 6 03:24:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538738095417529.0978027039168; Fri, 5 Oct 2018 04:14:55 -0700 (PDT) Received: from localhost ([::1]:34559 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g8O4M-0004yN-2i for importer@patchew.org; Fri, 05 Oct 2018 07:14:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43234) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g8O1e-00036l-Lj for qemu-devel@nongnu.org; Fri, 05 Oct 2018 07:12:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g8O1b-0003qd-NY for qemu-devel@nongnu.org; Fri, 05 Oct 2018 07:12:06 -0400 Received: from mx1.redhat.com ([209.132.183.28]:45652) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g8O1b-0003po-Eq for qemu-devel@nongnu.org; Fri, 05 Oct 2018 07:12:03 -0400 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id C0FD33086265; Fri, 5 Oct 2018 11:12:02 +0000 (UTC) Received: from sirius.home.kraxel.org (ovpn-116-29.ams2.redhat.com [10.36.116.29]) by smtp.corp.redhat.com (Postfix) with ESMTP id 22C002E182; Fri, 5 Oct 2018 11:11:59 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id 0D2D8982BE; Fri, 5 Oct 2018 13:11:58 +0200 (CEST) From: Gerd Hoffmann To: qemu-devel@nongnu.org Date: Fri, 5 Oct 2018 13:11:55 +0200 Message-Id: <20181005111157.12801-3-kraxel@redhat.com> In-Reply-To: <20181005111157.12801-1-kraxel@redhat.com> References: <20181005111157.12801-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.49]); Fri, 05 Oct 2018 11:12:02 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 2/4] hw/display/qxl: Suppress clang-7 warning about misaligned atomic operation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Gerd Hoffmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Peter Maydell If QEMU is compiled with clang-7 it results in the warning: hw/display/qxl.c:1884:19: error: misaligned or large atomic operation may incur significant performance penalty [-Werror,-Watomic-alignment] old_pending =3D atomic_fetch_or(&d->ram->int_pending, le_events); ^ This is because the Spice headers forgot to define the QXLRam struct with the '__aligned__(4)' attribute. clang 7 and newer will thus warn that the access here to int_pending might not be 4-aligned (because the QXLRam object d->ram points at might start at a misaligned address). In fact we set up d->ram in init_qxl_ram() so it always starts at a 4K boundary, so we know the atomic access here is OK. Newer Spice versions (with Spice commit beda5ec7a6848be20c0cac2a9a8ef2a41e8069c1) will fix the bug; for older Spice versions, work around it by telling the compiler explicitly that the alignment is OK using __builtin_assume_aligned(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20180927155538.699-1-peter.maydell@linaro.org Signed-off-by: Gerd Hoffmann --- include/qemu/compiler.h | 9 +++++++++ hw/display/qxl.c | 26 +++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h index 5843812710..bf47e7bee4 100644 --- a/include/qemu/compiler.h +++ b/include/qemu/compiler.h @@ -122,6 +122,15 @@ #ifndef __has_feature #define __has_feature(x) 0 /* compatibility with non-clang compilers */ #endif + +#ifndef __has_builtin +#define __has_builtin(x) 0 /* compatibility with non-clang compilers */ +#endif + +#if __has_builtin(__builtin_assume_aligned) || QEMU_GNUC_PREREQ(4, 7) +#define HAS_ASSUME_ALIGNED +#endif + /* Implement C11 _Generic via GCC builtins. Example: * * QEMU_GENERIC(x, (float, sinf), (long double, sinl), sin) (x) diff --git a/hw/display/qxl.c b/hw/display/qxl.c index 747986478f..e628cf1286 100644 --- a/hw/display/qxl.c +++ b/hw/display/qxl.c @@ -1893,7 +1893,31 @@ static void qxl_send_events(PCIQXLDevice *d, uint32_= t events) trace_qxl_send_events_vm_stopped(d->id, events); return; } - old_pending =3D atomic_fetch_or(&d->ram->int_pending, le_events); + /* + * Older versions of Spice forgot to define the QXLRam struct + * with the '__aligned__(4)' attribute. clang 7 and newer will + * thus warn that atomic_fetch_or(&d->ram->int_pending, ...) + * might be a misaligned atomic access, and will generate an + * out-of-line call for it, which results in a link error since + * we don't currently link against libatomic. + * + * In fact we set up d->ram in init_qxl_ram() so it always starts + * at a 4K boundary, so we know that &d->ram->int_pending is + * naturally aligned for a uint32_t. Newer Spice versions + * (with Spice commit beda5ec7a6848be20c0cac2a9a8ef2a41e8069c1) + * will fix the bug directly. To deal with older versions, + * we tell the compiler to assume the address really is aligned. + * Any compiler which cares about the misalignment will have + * __builtin_assume_aligned. + */ +#ifdef HAS_ASSUME_ALIGNED +#define ALIGNED_UINT32_PTR(P) ((uint32_t *)__builtin_assume_aligned(P, 4)) +#else +#define ALIGNED_UINT32_PTR(P) ((uint32_t *)P) +#endif + + old_pending =3D atomic_fetch_or(ALIGNED_UINT32_PTR(&d->ram->int_pendin= g), + le_events); if ((old_pending & le_events) =3D=3D le_events) { return; } --=20 2.9.3