From nobody Sun May 5 03:16:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538596043934895.8714357889447; Wed, 3 Oct 2018 12:47:23 -0700 (PDT) Received: from localhost ([::1]:52672 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7n71-00072d-Jv for importer@patchew.org; Wed, 03 Oct 2018 15:47:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59409) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7n02-0001eW-Oy for qemu-devel@nongnu.org; Wed, 03 Oct 2018 15:40:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g7n00-00021A-1n for qemu-devel@nongnu.org; Wed, 03 Oct 2018 15:39:58 -0400 Received: from mail-qt1-x844.google.com ([2607:f8b0:4864:20::844]:43712) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g7mzx-0001tm-Gn for qemu-devel@nongnu.org; Wed, 03 Oct 2018 15:39:53 -0400 Received: by mail-qt1-x844.google.com with SMTP id q41-v6so7282218qtq.10 for ; Wed, 03 Oct 2018 12:39:44 -0700 (PDT) Received: from cloudburst.twiddle.net ([172.56.13.153]) by smtp.gmail.com with ESMTPSA id t16-v6sm1284946qth.68.2018.10.03.12.39.41 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Oct 2018 12:39:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=eVBZVdR2wlJYrDZOh2ss3tefv/SjOKwhbvvyOD1IcWI=; b=cVE6ro2FRF0t5fJb+vQy4CAqk+eLEnqaKUFpu9FjE0S3fdd/+WazeIoaNjrnyS6idG wIKXRvvaI/BMjWxHa0dal11BF/wLfgTbsnRW48R30t90y/GkQgh9+RsQ+eeeIr/eNGog tNn7UTSKJOpfOs8OLj7JOtlewazru2nN0L0fk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=eVBZVdR2wlJYrDZOh2ss3tefv/SjOKwhbvvyOD1IcWI=; b=ZpiiCrGOwCUgnQas0eGSbMoLwQvxbxq5Y5opWz431FGv3weczsbDZgRyatTheNpREC TKrhACGOPad3EmKJPlDE6/BZ5QFoA10Ly34wsOoXfUsZ/HcvzKVz0ncUHUGDIiZAHQT5 COchqRM3+i9fA2S+c+g6WDIyxlNHfjwgSO39ePJWOFLBPz3ed2I36aKnUStYHPSm2osx BDcK0bRDXoJyxl6InvBx5z09xLxc1LWSS8ekxUjZo+qn4npCrZRf7fz2nVFR6Wa+Hq81 S8KkA+EVAwGWwRKI5iLBwSjf/Z00RfIvbVGD9dEYFR78nC6ZoX9+99o37u/h0z8g0Zep UhIw== X-Gm-Message-State: ABuFfoiF/YiN0eRn6S9rQiX/uN9Ou9BwXIOqmPKfwZOieG3M8r2zbhWT 5aDHkIcpES8t/XxMPmdBZUtf6/7vlb/UuA== X-Google-Smtp-Source: ACcGV61c7OB9SghHSADz0/BfouL+UM8YDsjpqSf/dDMgd1LIcWCxni9UdlbnBNVgOQnoSXbnzaOhsw== X-Received: by 2002:a0c:edcd:: with SMTP id i13-v6mr2592568qvr.15.1538595583780; Wed, 03 Oct 2018 12:39:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Oct 2018 14:39:23 -0500 Message-Id: <20181003193931.18096-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181003193931.18096-1-richard.henderson@linaro.org> References: <20181003193931.18096-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::844 Subject: [Qemu-devel] [PATCH v3 1/9] tcg: Split CONFIG_ATOMIC128 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" GCC7+ will no longer advertise support for 16-byte __atomic operations if only cmpxchg is supported, as for x86_64. Fortunately, x86_64 still has support for __sync_compare_and_swap_16 and we can make use of that. AArch64 does not have, nor ever has had such support, so open-code it. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 20 ++++- include/qemu/atomic128.h | 155 ++++++++++++++++++++++++++++++++++++ tcg/tcg.h | 16 ++-- accel/tcg/cputlb.c | 3 +- accel/tcg/user-exec.c | 5 +- configure | 19 +++++ 6 files changed, 204 insertions(+), 14 deletions(-) create mode 100644 include/qemu/atomic128.h diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index d751bcba48..efde12fdb2 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -100,19 +100,24 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, targ= et_ulong addr, DATA_TYPE ret; =20 ATOMIC_TRACE_RMW; +#if DATA_SIZE =3D=3D 16 + ret =3D atomic16_cmpxchg(haddr, cmpv, newv); +#else ret =3D atomic_cmpxchg__nocheck(haddr, cmpv, newv); +#endif ATOMIC_MMU_CLEANUP; return ret; } =20 #if DATA_SIZE >=3D 16 +#if HAVE_ATOMIC128 ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr EXTRA_ARGS) { ATOMIC_MMU_DECLS; DATA_TYPE val, *haddr =3D ATOMIC_MMU_LOOKUP; =20 ATOMIC_TRACE_LD; - __atomic_load(haddr, &val, __ATOMIC_RELAXED); + val =3D atomic16_read(haddr); ATOMIC_MMU_CLEANUP; return val; } @@ -124,9 +129,10 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong a= ddr, DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP; =20 ATOMIC_TRACE_ST; - __atomic_store(haddr, &val, __ATOMIC_RELAXED); + atomic16_set(haddr, val); ATOMIC_MMU_CLEANUP; } +#endif #else ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val EXTRA_ARGS) @@ -228,19 +234,24 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, targ= et_ulong addr, DATA_TYPE ret; =20 ATOMIC_TRACE_RMW; +#if DATA_SIZE =3D=3D 16 + ret =3D atomic16_cmpxchg(haddr, BSWAP(cmpv), BSWAP(newv)); +#else ret =3D atomic_cmpxchg__nocheck(haddr, BSWAP(cmpv), BSWAP(newv)); +#endif ATOMIC_MMU_CLEANUP; return BSWAP(ret); } =20 #if DATA_SIZE >=3D 16 +#if HAVE_ATOMIC128 ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr EXTRA_ARGS) { ATOMIC_MMU_DECLS; DATA_TYPE val, *haddr =3D ATOMIC_MMU_LOOKUP; =20 ATOMIC_TRACE_LD; - __atomic_load(haddr, &val, __ATOMIC_RELAXED); + val =3D atomic16_read(haddr); ATOMIC_MMU_CLEANUP; return BSWAP(val); } @@ -253,9 +264,10 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong a= ddr, =20 ATOMIC_TRACE_ST; val =3D BSWAP(val); - __atomic_store(haddr, &val, __ATOMIC_RELAXED); + atomic16_set(haddr, val); ATOMIC_MMU_CLEANUP; } +#endif #else ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val EXTRA_ARGS) diff --git a/include/qemu/atomic128.h b/include/qemu/atomic128.h new file mode 100644 index 0000000000..fdea225132 --- /dev/null +++ b/include/qemu/atomic128.h @@ -0,0 +1,155 @@ +/* + * Simple interface for 128-bit atomic operations. + * + * Copyright (C) 2018 Linaro, Ltd. + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + * See docs/devel/atomics.txt for discussion about the guarantees each + * atomic primitive is meant to provide. + */ + +#ifndef QEMU_ATOMIC128_H +#define QEMU_ATOMIC128_H + +/* + * GCC is a house divided about supporting large atomic operations. + * + * For hosts that only have large compare-and-swap, a legalistic reading + * of the C++ standard means that one cannot implement __atomic_read on + * read-only memory, and thus all atomic operations must synchronize + * through libatomic. + * + * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D80878 + * + * This interpretation is not especially helpful for QEMU. + * For softmmu, all RAM is always read/write from the hypervisor. + * For user-only, if the guest doesn't implement such an __atomic_read + * then the host need not worry about it either. + * + * Moreover, using libatomic is not an option, because its interface is + * built for std::atomic, and requires that *all* accesses to such an + * object go through the library. In our case we do not have an object + * in the C/C++ sense, but a view of memory as seen by the guest. + * The guest may issue a large atomic operation and then access those + * pieces using word-sized accesses. From the hypervisor, we have no + * way to connect those two actions. + * + * Therefore, special case each platform. + */ + +#if defined(CONFIG_ATOMIC128) +static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) +{ + return atomic_cmpxchg__nocheck(ptr, cmp, new); +} +# define HAVE_CMPXCHG128 1 +#elif defined(CONFIG_CMPXCHG128) +static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) +{ + return __sync_val_compare_and_swap_16(ptr, cmp, new); +} +# define HAVE_CMPXCHG128 1 +#elif defined(__aarch64__) +/* Through gcc 8, aarch64 has no support for 128-bit at all. */ +static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) +{ + uint64_t cmpl =3D int128_getlo(cmp), cmph =3D int128_gethi(cmp); + uint64_t newl =3D int128_getlo(new), newh =3D int128_gethi(new); + uint64_t oldl, oldh; + uint32_t tmp; + + asm("0: ldaxp %[oldl], %[oldh], %[mem]\n\t" + "cmp %[oldl], %[cmpl]\n\t" + "ccmp %[oldh], %[cmph], #0, eq\n\t" + "b.ne 1f\n\t" + "stlxp %w[tmp], %[newl], %[newh], %[mem]\n\t" + "cbnz %w[tmp], 0b\n" + "1:" + : [mem] "+m"(*ptr), [tmp] "=3D&r"(tmp), + [oldl] "=3D&r"(oldl), [oldh] "=3Dr"(oldh) + : [cmpl] "r"(cmpl), [cmph] "r"(cmph), + [newl] "r"(newl), [newh] "r"(newh) + : "memory", "cc"); + + return int128_make128(oldl, oldh); +} +# define HAVE_CMPXCHG128 1 +#else +/* Fallback definition that must be optimized away, or error. */ +Int128 __attribute__((error("unsupported atomic"))) + atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new); +# define HAVE_CMPXCHG128 0 +#endif /* Some definition for HAVE_CMPXCHG128 */ + + +#if defined(CONFIG_ATOMIC128) +static inline Int128 atomic16_read(Int128 *ptr) +{ + return atomic_read__nocheck(ptr); +} + +static inline void atomic16_set(Int128 *ptr, Int128 val) +{ + atomic_set__nocheck(ptr, val); +} + +# define HAVE_ATOMIC128 1 +#elif !defined(CONFIG_USER_ONLY) && defined(__aarch64__) +/* We can do better than cmpxchg for AArch64. */ +static inline Int128 atomic16_read(Int128 *ptr) +{ + uint64_t l, h; + uint32_t tmp; + + /* The load must be paired with the store to guarantee not tearing. */ + asm("0: ldxp %[l], %[h], %[mem]\n\t" + "stxp %w[tmp], %[l], %[h], %[mem]\n\t" + "cbnz %w[tmp], 0b" + : [mem] "+m"(*ptr), [tmp] "=3Dr"(tmp), [l] "=3Dr"(l), [h] "=3Dr"(h= )); + + return int128_make128(l, h); +} + +static inline void atomic16_set(Int128 *ptr, Int128 val) +{ + uint64_t l =3D int128_getlo(val), h =3D int128_gethi(val); + uint64_t t1, t2; + + /* Load into temporaries to acquire the exclusive access lock. */ + asm("0: ldxp %[t1], %[t2], %[mem]\n\t" + "stxp %w[t1], %[l], %[h], %[mem]\n\t" + "cbnz %w[t1], 0b" + : [mem] "+m"(*ptr), [t1] "=3D&r"(t1), [t2] "=3D&r"(t2) + : [l] "r"(l), [h] "r"(h)); +} + +# define HAVE_ATOMIC128 1 +#elif !defined(CONFIG_USER_ONLY) && HAVE_CMPXCHG128 +static inline Int128 atomic16_read(Int128 *ptr) +{ + /* Maybe replace 0 with 0, returning the old value. */ + return atomic16_cmpxchg(ptr, 0, 0); +} + +static inline void atomic16_set(Int128 *ptr, Int128 val) +{ + Int128 old =3D *ptr, cmp; + do { + cmp =3D old; + old =3D atomic16_cmpxchg(ptr, cmp, val); + } while (old !=3D cmp); +} + +# define HAVE_ATOMIC128 1 +#else +/* Fallback definitions that must be optimized away, or error. */ +Int128 __attribute__((error("unsupported atomic"))) + atomic16_read(Int128 *ptr); +void __attribute__((error("unsupported atomic"))) + atomic16_set(Int128 *ptr, Int128 val); +# define HAVE_ATOMIC128 0 +#endif /* Some definition for HAVE_ATOMIC128 */ + +#endif /* QEMU_ATOMIC128_H */ diff --git a/tcg/tcg.h b/tcg/tcg.h index f9f12378e9..20803b8b64 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -32,6 +32,7 @@ #include "qemu/queue.h" #include "tcg-mo.h" #include "tcg-target.h" +#include "qemu/int128.h" =20 /* XXX: make safe guess about sizes */ #define MAX_OP_PER_INSTR 266 @@ -1454,11 +1455,14 @@ GEN_ATOMIC_HELPER_ALL(xchg) #undef GEN_ATOMIC_HELPER #endif /* CONFIG_SOFTMMU */ =20 -#ifdef CONFIG_ATOMIC128 -#include "qemu/int128.h" - -/* These aren't really a "proper" helpers because TCG cannot manage Int128. - However, use the same format as the others, for use by the backends. */ +/* + * These aren't really a "proper" helpers because TCG cannot manage Int128. + * However, use the same format as the others, for use by the backends. + * + * The cmpxchg functions are only defined if HAVE_CMPXCHG128; + * the ld/st functions are only defined if HAVE_ATOMIC128, + * as defined by . + */ Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr, Int128 cmpv, Int128 newv, TCGMemOpIdx oi, uintptr_t retaddr); @@ -1475,6 +1479,4 @@ void helper_atomic_sto_le_mmu(CPUArchState *env, targ= et_ulong addr, Int128 val, void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128= val, TCGMemOpIdx oi, uintptr_t retaddr); =20 -#endif /* CONFIG_ATOMIC128 */ - #endif /* TCG_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f4702ce91f..0e740f5296 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -32,6 +32,7 @@ #include "exec/log.h" #include "exec/helper-proto.h" #include "qemu/atomic.h" +#include "qemu/atomic128.h" =20 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ @@ -1101,7 +1102,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, #include "atomic_template.h" #endif =20 -#ifdef CONFIG_ATOMIC128 +#if HAVE_CMPXCHG128 || HAVE_ATOMIC128 #define DATA_SIZE 16 #include "atomic_template.h" #endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 26a3ffbba1..cd75829cf2 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -25,6 +25,7 @@ #include "exec/cpu_ldst.h" #include "translate-all.h" #include "exec/helper-proto.h" +#include "qemu/atomic128.h" =20 #undef EAX #undef ECX @@ -615,7 +616,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, targe= t_ulong addr, /* The following is only callable from other helpers, and matches up with the softmmu version. */ =20 -#ifdef CONFIG_ATOMIC128 +#if HAVE_ATOMIC128 || HAVE_CMPXCHG128 =20 #undef EXTRA_ARGS #undef ATOMIC_NAME @@ -628,4 +629,4 @@ static void *atomic_mmu_lookup(CPUArchState *env, targe= t_ulong addr, =20 #define DATA_SIZE 16 #include "atomic_template.h" -#endif /* CONFIG_ATOMIC128 */ +#endif diff --git a/configure b/configure index f3d4b799a5..f6fa341f33 100755 --- a/configure +++ b/configure @@ -5186,6 +5186,21 @@ EOF fi fi =20 +cmpxchg128=3Dno +if test "$int128" =3D yes -a "$atomic128" =3D no; then + cat > $TMPC << EOF +int main(void) +{ + unsigned __int128 x =3D 0, y =3D 0; + __sync_val_compare_and_swap_16(&x, y, x); + return 0; +} +EOF + if compile_prog "" "" ; then + cmpxchg128=3Dyes + fi +fi + ######################################### # See if 64-bit atomic operations are supported. # Note that without __atomic builtins, we can only @@ -6702,6 +6717,10 @@ if test "$atomic128" =3D "yes" ; then echo "CONFIG_ATOMIC128=3Dy" >> $config_host_mak fi =20 +if test "$cmpxchg128" =3D "yes" ; then + echo "CONFIG_CMPXCHG128=3Dy" >> $config_host_mak +fi + if test "$atomic64" =3D "yes" ; then echo "CONFIG_ATOMIC64=3Dy" >> $config_host_mak fi --=20 2.17.1 From nobody Sun May 5 03:16:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 03 Oct 2018 12:39:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Oct 2018 14:39:24 -0500 Message-Id: <20181003193931.18096-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181003193931.18096-1-richard.henderson@linaro.org> References: <20181003193931.18096-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::736 Subject: [Qemu-devel] [PATCH v3 2/9] target/i386: Convert to HAVE_CMPXCHG128 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/i386/mem_helper.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/target/i386/mem_helper.c b/target/i386/mem_helper.c index 30c26b9d9c..6cc53bcb40 100644 --- a/target/i386/mem_helper.c +++ b/target/i386/mem_helper.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "qemu/int128.h" +#include "qemu/atomic128.h" #include "tcg.h" =20 void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0) @@ -137,10 +138,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong = a0) =20 if ((a0 & 0xf) !=3D 0) { raise_exception_ra(env, EXCP0D_GPF, ra); - } else { -#ifndef CONFIG_ATOMIC128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else + } else if (HAVE_CMPXCHG128) { int eflags =3D cpu_cc_compute_all(env, CC_OP); =20 Int128 cmpv =3D int128_make128(env->regs[R_EAX], env->regs[R_EDX]); @@ -159,7 +157,8 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a= 0) eflags &=3D ~CC_Z; } CC_SRC =3D eflags; -#endif + } else { + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); } } #endif --=20 2.17.1 From nobody Sun May 5 03:16:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538596164853821.3688029807636; Wed, 3 Oct 2018 12:49:24 -0700 (PDT) Received: from localhost ([::1]:52682 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7n99-0000Ix-Ji for importer@patchew.org; Wed, 03 Oct 2018 15:49:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59404) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7n02-0001eV-J5 for qemu-devel@nongnu.org; Wed, 03 Oct 2018 15:40:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g7n00-00021K-1C for qemu-devel@nongnu.org; Wed, 03 Oct 2018 15:39:58 -0400 Received: from mail-qt1-x82f.google.com ([2607:f8b0:4864:20::82f]:45482) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g7mzx-0001vv-Hj for qemu-devel@nongnu.org; Wed, 03 Oct 2018 15:39:55 -0400 Received: by mail-qt1-x82f.google.com with SMTP id l2-v6so7264157qtr.12 for ; Wed, 03 Oct 2018 12:39:48 -0700 (PDT) Received: from cloudburst.twiddle.net ([172.56.13.153]) by smtp.gmail.com with ESMTPSA id t16-v6sm1284946qth.68.2018.10.03.12.39.46 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Oct 2018 12:39:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=QKc2lwPI6gYZ9z9pd6IUUHkpaxmzYi423q9W7Fv4D+w=; b=HQboFbgLtbXlZmjf1mDGSFIGsb5FlTO+iC6jIZVurOIn6ZnLUyqrQhVfvc0tQEMHGa /oEh/uB+UTVm6MIQF3o8LSpK32pSxa4HXV9PA12UwdJd3TUlB+YTdWvvEp7I2gzCfOle T3L55XPZFnqbmUrBsTe2jAJH5+qDuJ28HmMy4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=QKc2lwPI6gYZ9z9pd6IUUHkpaxmzYi423q9W7Fv4D+w=; b=nz+k32n5y6t9kiJ6t1+uXqcvJfud87MmUYXZ7sEfb0P64IknPRDZAqRq//1lVj7KF3 gYsYSysFDs7twjgJ2z3+bSXPzOhiidTOQxGQB4SfT+WGav+Bt7vJplZtMi+9fXCbBurw QkXdebc5OeO9Frw/5AWjixdYLz/EWNUcRoEWNU8FZJMzodmmWzIgNGAKHquX2mlPUPJJ h/W6R9V0NSg9QozBNqvGB1bMaMcvHtM0akCZIQJpuy/qHxWaZXr6evaS56xfdT4akNF2 LccGMzDNyQ4ULsXd1jEWu7Hc+uuFsZCpgT7yMfx0e8jRqoy80OHnh+8yFltuhUkn+RCT q54w== X-Gm-Message-State: ABuFfojqVNb7l9fx52qn54u5nQ/dc6Sf5oU8AlWKsboT/R9sozZ7jL0p mADW3KVvbWAjV61Z6T9o/ZW38CJ25y+BqA== X-Google-Smtp-Source: ACcGV61tcPiPlmteaCHhs+3HgVs6kZB3Hz3YLl5s4ATv6/d9uJHdIR/ZbxDjhukggeLtqvmIpAvgHg== X-Received: by 2002:ac8:2e11:: with SMTP id r17-v6mr2597907qta.12.1538595587848; Wed, 03 Oct 2018 12:39:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Oct 2018 14:39:25 -0500 Message-Id: <20181003193931.18096-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181003193931.18096-1-richard.henderson@linaro.org> References: <20181003193931.18096-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::82f Subject: [Qemu-devel] [PATCH v3 3/9] target/arm: Convert to HAVE_CMPXCHG128 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 259 +++++++++++++++++++++------------------- 1 file changed, 133 insertions(+), 126 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 7f6ad3000b..6e4e1b8a19 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -30,6 +30,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "qemu/int128.h" +#include "qemu/atomic128.h" #include "tcg.h" #include "fpu/softfloat.h" #include /* For crc32 */ @@ -509,189 +510,195 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t v= al, uint32_t bytes) return crc32c(acc, buf, bytes) ^ 0xffffffff; } =20 -/* Returns 0 on success; 1 otherwise. */ -static uint64_t do_paired_cmpxchg64_le(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi, - bool parallel, uintptr_t ra) +uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, + uint64_t new_lo, uint64_t new_hi) { - Int128 oldv, cmpv, newv; + Int128 cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high= ); + Int128 newv =3D int128_make128(new_lo, new_hi); + Int128 oldv; + uintptr_t ra =3D GETPC(); + uint64_t o0, o1; bool success; =20 - cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); - newv =3D int128_make128(new_lo, new_hi); - - if (parallel) { -#ifndef CONFIG_ATOMIC128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); - oldv =3D helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, = ra); - success =3D int128_eq(oldv, cmpv); -#endif - } else { - uint64_t o0, o1; - #ifdef CONFIG_USER_ONLY - /* ??? Enforce alignment. */ - uint64_t *haddr =3D g2h(addr); + /* ??? Enforce alignment. */ + uint64_t *haddr =3D g2h(addr); =20 - helper_retaddr =3D ra; - o0 =3D ldq_le_p(haddr + 0); - o1 =3D ldq_le_p(haddr + 1); - oldv =3D int128_make128(o0, o1); + helper_retaddr =3D ra; + o0 =3D ldq_le_p(haddr + 0); + o1 =3D ldq_le_p(haddr + 1); + oldv =3D int128_make128(o0, o1); =20 - success =3D int128_eq(oldv, cmpv); - if (success) { - stq_le_p(haddr + 0, int128_getlo(newv)); - stq_le_p(haddr + 1, int128_gethi(newv)); - } - helper_retaddr =3D 0; -#else - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi0 =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); - TCGMemOpIdx oi1 =3D make_memop_idx(MO_LEQ, mem_idx); - - o0 =3D helper_le_ldq_mmu(env, addr + 0, oi0, ra); - o1 =3D helper_le_ldq_mmu(env, addr + 8, oi1, ra); - oldv =3D int128_make128(o0, o1); - - success =3D int128_eq(oldv, cmpv); - if (success) { - helper_le_stq_mmu(env, addr + 0, int128_getlo(newv), oi1, ra); - helper_le_stq_mmu(env, addr + 8, int128_gethi(newv), oi1, ra); - } -#endif + success =3D int128_eq(oldv, cmpv); + if (success) { + stq_le_p(haddr + 0, int128_getlo(newv)); + stq_le_p(haddr + 1, int128_gethi(newv)); } + helper_retaddr =3D 0; +#else + int mem_idx =3D cpu_mmu_index(env, false); + TCGMemOpIdx oi0 =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); + TCGMemOpIdx oi1 =3D make_memop_idx(MO_LEQ, mem_idx); + + o0 =3D helper_le_ldq_mmu(env, addr + 0, oi0, ra); + o1 =3D helper_le_ldq_mmu(env, addr + 8, oi1, ra); + oldv =3D int128_make128(o0, o1); + + success =3D int128_eq(oldv, cmpv); + if (success) { + helper_le_stq_mmu(env, addr + 0, int128_getlo(newv), oi1, ra); + helper_le_stq_mmu(env, addr + 8, int128_gethi(newv), oi1, ra); + } +#endif =20 return !success; } =20 -uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t ne= w_hi) -{ - return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, false, GETPC(= )); -} - uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t a= ddr, uint64_t new_lo, uint64_t ne= w_hi) -{ - return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, true, GETPC()= ); -} - -static uint64_t do_paired_cmpxchg64_be(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi, - bool parallel, uintptr_t ra) { Int128 oldv, cmpv, newv; + uintptr_t ra =3D GETPC(); bool success; + int mem_idx; + TCGMemOpIdx oi; =20 - /* high and low need to be switched here because this is not actually a - * 128bit store but two doublewords stored consecutively - */ - cmpv =3D int128_make128(env->exclusive_high, env->exclusive_val); - newv =3D int128_make128(new_hi, new_lo); - - if (parallel) { -#ifndef CONFIG_ATOMIC128 + if (!HAVE_CMPXCHG128) { cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); - oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, = ra); - success =3D int128_eq(oldv, cmpv); -#endif - } else { - uint64_t o0, o1; - -#ifdef CONFIG_USER_ONLY - /* ??? Enforce alignment. */ - uint64_t *haddr =3D g2h(addr); - - helper_retaddr =3D ra; - o1 =3D ldq_be_p(haddr + 0); - o0 =3D ldq_be_p(haddr + 1); - oldv =3D int128_make128(o0, o1); - - success =3D int128_eq(oldv, cmpv); - if (success) { - stq_be_p(haddr + 0, int128_gethi(newv)); - stq_be_p(haddr + 1, int128_getlo(newv)); - } - helper_retaddr =3D 0; -#else - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi0 =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); - TCGMemOpIdx oi1 =3D make_memop_idx(MO_BEQ, mem_idx); - - o1 =3D helper_be_ldq_mmu(env, addr + 0, oi0, ra); - o0 =3D helper_be_ldq_mmu(env, addr + 8, oi1, ra); - oldv =3D int128_make128(o0, o1); - - success =3D int128_eq(oldv, cmpv); - if (success) { - helper_be_stq_mmu(env, addr + 0, int128_gethi(newv), oi1, ra); - helper_be_stq_mmu(env, addr + 8, int128_getlo(newv), oi1, ra); - } -#endif } =20 + mem_idx =3D cpu_mmu_index(env, false); + oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); + + cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); + newv =3D int128_make128(new_lo, new_hi); + oldv =3D helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra); + + success =3D int128_eq(oldv, cmpv); return !success; } =20 uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, uint64_t new_lo, uint64_t new_hi) { - return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, false, GETPC(= )); + /* + * High and low need to be switched here because this is not actually a + * 128bit store but two doublewords stored consecutively + */ + Int128 cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high= ); + Int128 newv =3D int128_make128(new_lo, new_hi); + Int128 oldv; + uintptr_t ra =3D GETPC(); + uint64_t o0, o1; + bool success; + +#ifdef CONFIG_USER_ONLY + /* ??? Enforce alignment. */ + uint64_t *haddr =3D g2h(addr); + + helper_retaddr =3D ra; + o1 =3D ldq_be_p(haddr + 0); + o0 =3D ldq_be_p(haddr + 1); + oldv =3D int128_make128(o0, o1); + + success =3D int128_eq(oldv, cmpv); + if (success) { + stq_be_p(haddr + 0, int128_gethi(newv)); + stq_be_p(haddr + 1, int128_getlo(newv)); + } + helper_retaddr =3D 0; +#else + int mem_idx =3D cpu_mmu_index(env, false); + TCGMemOpIdx oi0 =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); + TCGMemOpIdx oi1 =3D make_memop_idx(MO_BEQ, mem_idx); + + o1 =3D helper_be_ldq_mmu(env, addr + 0, oi0, ra); + o0 =3D helper_be_ldq_mmu(env, addr + 8, oi1, ra); + oldv =3D int128_make128(o0, o1); + + success =3D int128_eq(oldv, cmpv); + if (success) { + helper_be_stq_mmu(env, addr + 0, int128_gethi(newv), oi1, ra); + helper_be_stq_mmu(env, addr + 8, int128_getlo(newv), oi1, ra); + } +#endif + + return !success; } =20 uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t a= ddr, - uint64_t new_lo, uint64_t new_hi) + uint64_t new_lo, uint64_t ne= w_hi) { - return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true, GETPC()= ); + Int128 oldv, cmpv, newv; + uintptr_t ra =3D GETPC(); + bool success; + int mem_idx; + TCGMemOpIdx oi; + + if (!HAVE_CMPXCHG128) { + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + } + + mem_idx =3D cpu_mmu_index(env, false); + oi =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); + + /* + * High and low need to be switched here because this is not actually a + * 128bit store but two doublewords stored consecutively + */ + cmpv =3D int128_make128(env->exclusive_high, env->exclusive_val); + newv =3D int128_make128(new_hi, new_lo); + oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); + + success =3D int128_eq(oldv, cmpv); + return !success; } =20 /* Writes back the old data into Rs. */ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, uint64_t new_lo, uint64_t new_hi) { - uintptr_t ra =3D GETPC(); -#ifndef CONFIG_ATOMIC128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else Int128 oldv, cmpv, newv; + uintptr_t ra =3D GETPC(); + int mem_idx; + TCGMemOpIdx oi; + + if (!HAVE_CMPXCHG128) { + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + } + + mem_idx =3D cpu_mmu_index(env, false); + oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); =20 cmpv =3D int128_make128(env->xregs[rs], env->xregs[rs + 1]); newv =3D int128_make128(new_lo, new_hi); - - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); oldv =3D helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra); =20 env->xregs[rs] =3D int128_getlo(oldv); env->xregs[rs + 1] =3D int128_gethi(oldv); -#endif } =20 void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, uint64_t new_hi, uint64_t new_lo) { - uintptr_t ra =3D GETPC(); -#ifndef CONFIG_ATOMIC128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else Int128 oldv, cmpv, newv; + uintptr_t ra =3D GETPC(); + int mem_idx; + TCGMemOpIdx oi; + + if (!HAVE_CMPXCHG128) { + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + } + + mem_idx =3D cpu_mmu_index(env, false); + oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); =20 cmpv =3D int128_make128(env->xregs[rs + 1], env->xregs[rs]); newv =3D int128_make128(new_lo, new_hi); - - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); =20 env->xregs[rs + 1] =3D int128_getlo(oldv); env->xregs[rs] =3D int128_gethi(oldv); -#endif } =20 /* --=20 2.17.1 From nobody Sun May 5 03:16:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538595900272267.9267557821024; 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Wed, 03 Oct 2018 12:39:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Oct 2018 14:39:26 -0500 Message-Id: <20181003193931.18096-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181003193931.18096-1-richard.henderson@linaro.org> References: <20181003193931.18096-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::841 Subject: [Qemu-devel] [PATCH v3 4/9] target/arm: Check HAVE_CMPXCHG128 at translate time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper-a64.c | 16 ++++------------ target/arm/translate-a64.c | 38 ++++++++++++++++++++++---------------- 2 files changed, 26 insertions(+), 28 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 6e4e1b8a19..61799d20e1 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -563,9 +563,7 @@ uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMSta= te *env, uint64_t addr, int mem_idx; TCGMemOpIdx oi; =20 - if (!HAVE_CMPXCHG128) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } + assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); @@ -635,9 +633,7 @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMSta= te *env, uint64_t addr, int mem_idx; TCGMemOpIdx oi; =20 - if (!HAVE_CMPXCHG128) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } + assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); oi =3D make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx); @@ -663,9 +659,7 @@ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_= t rs, uint64_t addr, int mem_idx; TCGMemOpIdx oi; =20 - if (!HAVE_CMPXCHG128) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } + assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); @@ -686,9 +680,7 @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_= t rs, uint64_t addr, int mem_idx; TCGMemOpIdx oi; =20 - if (!HAVE_CMPXCHG128) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } + assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); oi =3D make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8ca3876707..77ee8d9085 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -37,6 +37,7 @@ =20 #include "trace-tcg.h" #include "translate-a64.h" +#include "qemu/atomic128.h" =20 static TCGv_i64 cpu_X[32]; static TCGv_i64 cpu_pc; @@ -2082,26 +2083,27 @@ static void gen_store_exclusive(DisasContext *s, in= t rd, int rt, int rt2, get_mem_index(s), MO_64 | MO_ALIGN | s->be_data); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); - } else if (s->be_data =3D=3D MO_LE) { - if (tb_cflags(s->base.tb) & CF_PARALLEL) { + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { + if (!HAVE_CMPXCHG128) { + gen_helper_exit_atomic(cpu_env); + s->base.is_jmp =3D DISAS_NORETURN; + } else if (s->be_data =3D=3D MO_LE) { gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env, cpu_exclusive_addr, cpu_reg(s, rt), cpu_reg(s, rt2)); } else { - gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive= _addr, - cpu_reg(s, rt), cpu_reg(s, = rt2)); - } - } else { - if (tb_cflags(s->base.tb) & CF_PARALLEL) { gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env, cpu_exclusive_addr, cpu_reg(s, rt), cpu_reg(s, rt2)); - } else { - gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive= _addr, - cpu_reg(s, rt), cpu_reg(s, = rt2)); } + } else if (s->be_data =3D=3D MO_LE) { + gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_add= r, + cpu_reg(s, rt), cpu_reg(s, rt2)= ); + } else { + gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_add= r, + cpu_reg(s, rt), cpu_reg(s, rt2)= ); } } else { tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_= val, @@ -2171,14 +2173,18 @@ static void gen_compare_and_swap_pair(DisasContext = *s, int rs, int rt, } tcg_temp_free_i64(cmp); } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { - TCGv_i32 tcg_rs =3D tcg_const_i32(rs); - - if (s->be_data =3D=3D MO_LE) { - gen_helper_casp_le_parallel(cpu_env, tcg_rs, addr, t1, t2); + if (HAVE_CMPXCHG128) { + TCGv_i32 tcg_rs =3D tcg_const_i32(rs); + if (s->be_data =3D=3D MO_LE) { + gen_helper_casp_le_parallel(cpu_env, tcg_rs, addr, t1, t2); + } else { + gen_helper_casp_be_parallel(cpu_env, tcg_rs, addr, t1, t2); + } + tcg_temp_free_i32(tcg_rs); } else { - gen_helper_casp_be_parallel(cpu_env, tcg_rs, addr, t1, t2); + gen_helper_exit_atomic(cpu_env); + s->base.is_jmp =3D DISAS_NORETURN; } - tcg_temp_free_i32(tcg_rs); } else { TCGv_i64 d1 =3D tcg_temp_new_i64(); TCGv_i64 d2 =3D tcg_temp_new_i64(); --=20 2.17.1 From nobody Sun May 5 03:16:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538596056543860.036432155825; Wed, 3 Oct 2018 12:47:36 -0700 (PDT) Received: from localhost ([::1]:52673 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7n7P-0007JV-6H for importer@patchew.org; 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Wed, 03 Oct 2018 12:39:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Oct 2018 14:39:27 -0500 Message-Id: <20181003193931.18096-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181003193931.18096-1-richard.henderson@linaro.org> References: <20181003193931.18096-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::72a Subject: [Qemu-devel] [PATCH v3 5/9] target/ppc: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/ppc/helper.h | 2 +- target/ppc/mem_helper.c | 33 ++++++++++-- target/ppc/translate.c | 115 +++++++++++++++++++++------------------- 3 files changed, 88 insertions(+), 62 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index ef64248bc4..7a1481fd0b 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -800,7 +800,7 @@ DEF_HELPER_4(dscliq, void, env, fprp, fprp, i32) DEF_HELPER_1(tbegin, void, env) DEF_HELPER_FLAGS_1(fixup_thrm, TCG_CALL_NO_RWG, void, env) =20 -#if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128) +#ifdef TARGET_PPC64 DEF_HELPER_FLAGS_3(lq_le_parallel, TCG_CALL_NO_WG, i64, env, tl, i32) DEF_HELPER_FLAGS_3(lq_be_parallel, TCG_CALL_NO_WG, i64, env, tl, i32) DEF_HELPER_FLAGS_5(stq_le_parallel, TCG_CALL_NO_WG, diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 8f0d86d104..a1485fad9b 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -25,6 +25,7 @@ #include "exec/cpu_ldst.h" #include "tcg.h" #include "internal.h" +#include "qemu/atomic128.h" =20 //#define DEBUG_OP =20 @@ -215,11 +216,15 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ul= ong addr, uint32_t reg, return i; } =20 -#if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128) +#ifdef TARGET_PPC64 uint64_t helper_lq_le_parallel(CPUPPCState *env, target_ulong addr, uint32_t opidx) { - Int128 ret =3D helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC()); + Int128 ret; + + /* We will have raised EXCP_ATOMIC from the translator. */ + assert(HAVE_ATOMIC128); + ret =3D helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC()); env->retxh =3D int128_gethi(ret); return int128_getlo(ret); } @@ -227,7 +232,11 @@ uint64_t helper_lq_le_parallel(CPUPPCState *env, targe= t_ulong addr, uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr, uint32_t opidx) { - Int128 ret =3D helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC()); + Int128 ret; + + /* We will have raised EXCP_ATOMIC from the translator. */ + assert(HAVE_ATOMIC128); + ret =3D helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC()); env->retxh =3D int128_gethi(ret); return int128_getlo(ret); } @@ -235,14 +244,22 @@ uint64_t helper_lq_be_parallel(CPUPPCState *env, targ= et_ulong addr, void helper_stq_le_parallel(CPUPPCState *env, target_ulong addr, uint64_t lo, uint64_t hi, uint32_t opidx) { - Int128 val =3D int128_make128(lo, hi); + Int128 val; + + /* We will have raised EXCP_ATOMIC from the translator. */ + assert(HAVE_ATOMIC128); + val =3D int128_make128(lo, hi); helper_atomic_sto_le_mmu(env, addr, val, opidx, GETPC()); } =20 void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr, uint64_t lo, uint64_t hi, uint32_t opidx) { - Int128 val =3D int128_make128(lo, hi); + Int128 val; + + /* We will have raised EXCP_ATOMIC from the translator. */ + assert(HAVE_ATOMIC128); + val =3D int128_make128(lo, hi); helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC()); } =20 @@ -252,6 +269,9 @@ uint32_t helper_stqcx_le_parallel(CPUPPCState *env, tar= get_ulong addr, { bool success =3D false; =20 + /* We will have raised EXCP_ATOMIC from the translator. */ + assert(HAVE_CMPXCHG128); + if (likely(addr =3D=3D env->reserve_addr)) { Int128 oldv, cmpv, newv; =20 @@ -271,6 +291,9 @@ uint32_t helper_stqcx_be_parallel(CPUPPCState *env, tar= get_ulong addr, { bool success =3D false; =20 + /* We will have raised EXCP_ATOMIC from the translator. */ + assert(HAVE_CMPXCHG128); + if (likely(addr =3D=3D env->reserve_addr)) { Int128 oldv, cmpv, newv; =20 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 881743571b..4e59dd5f42 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -33,6 +33,7 @@ #include "trace-tcg.h" #include "exec/translator.h" #include "exec/log.h" +#include "qemu/atomic128.h" =20 =20 #define CPU_SINGLE_STEP 0x1 @@ -2654,22 +2655,22 @@ static void gen_lq(DisasContext *ctx) hi =3D cpu_gpr[rd]; =20 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { -#ifdef CONFIG_ATOMIC128 - TCGv_i32 oi =3D tcg_temp_new_i32(); - if (ctx->le_mode) { - tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); - gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); + if (HAVE_ATOMIC128) { + TCGv_i32 oi =3D tcg_temp_new_i32(); + if (ctx->le_mode) { + tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); + gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); + } else { + tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); + gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); + } + tcg_temp_free_i32(oi); + tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); } else { - tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); - gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; } - tcg_temp_free_i32(oi); - tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); -#else - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; -#endif } else if (ctx->le_mode) { tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); gen_addr_add(ctx, EA, EA, 8); @@ -2805,21 +2806,21 @@ static void gen_std(DisasContext *ctx) hi =3D cpu_gpr[rs]; =20 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { -#ifdef CONFIG_ATOMIC128 - TCGv_i32 oi =3D tcg_temp_new_i32(); - if (ctx->le_mode) { - tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); - gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); + if (HAVE_ATOMIC128) { + TCGv_i32 oi =3D tcg_temp_new_i32(); + if (ctx->le_mode) { + tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_i= dx)); + gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); + } else { + tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_i= dx)); + gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); + } + tcg_temp_free_i32(oi); } else { - tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); - gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; } - tcg_temp_free_i32(oi); -#else - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; -#endif } else if (ctx->le_mode) { tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); gen_addr_add(ctx, EA, EA, 8); @@ -3404,26 +3405,26 @@ static void gen_lqarx(DisasContext *ctx) hi =3D cpu_gpr[rd]; =20 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { -#ifdef CONFIG_ATOMIC128 - TCGv_i32 oi =3D tcg_temp_new_i32(); - if (ctx->le_mode) { - tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, - ctx->mem_idx)); - gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); + if (HAVE_ATOMIC128) { + TCGv_i32 oi =3D tcg_temp_new_i32(); + if (ctx->le_mode) { + tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, + ctx->mem_idx)); + gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); + } else { + tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, + ctx->mem_idx)); + gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); + } + tcg_temp_free_i32(oi); + tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); } else { - tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, - ctx->mem_idx)); - gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; + tcg_temp_free(EA); + return; } - tcg_temp_free_i32(oi); - tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); -#else - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - tcg_temp_free(EA); - return; -#endif } else if (ctx->le_mode) { tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); tcg_gen_mov_tl(cpu_reserve, EA); @@ -3461,20 +3462,22 @@ static void gen_stqcx_(DisasContext *ctx) hi =3D cpu_gpr[rs]; =20 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - TCGv_i32 oi =3D tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); -#ifdef CONFIG_ATOMIC128 - if (ctx->le_mode) { - gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, = oi); + if (HAVE_CMPXCHG128) { + TCGv_i32 oi =3D tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); + if (ctx->le_mode) { + gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, + EA, lo, hi, oi); + } else { + gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, + EA, lo, hi, oi); + } + tcg_temp_free_i32(oi); } else { - gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, EA, lo, hi, = oi); + /* Restart with exclusive lock. */ + gen_helper_exit_atomic(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; } -#else - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; -#endif tcg_temp_free(EA); - tcg_temp_free_i32(oi); } else { TCGLabel *lab_fail =3D gen_new_label(); TCGLabel *lab_over =3D gen_new_label(); --=20 2.17.1 From nobody Sun May 5 03:16:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538595753354687.8755701624906; Wed, 3 Oct 2018 12:42:33 -0700 (PDT) Received: from localhost ([::1]:52650 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7n2W-0002zT-3Q for importer@patchew.org; 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Wed, 03 Oct 2018 12:39:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Oct 2018 14:39:28 -0500 Message-Id: <20181003193931.18096-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181003193931.18096-1-richard.henderson@linaro.org> References: <20181003193931.18096-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::842 Subject: [Qemu-devel] [PATCH v3 6/9] target/s390x: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: qemu-s390x@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand --- target/s390x/mem_helper.c | 92 +++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 51 deletions(-) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index bacae4f503..e106f61b4e 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -25,6 +25,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "qemu/int128.h" +#include "qemu/atomic128.h" =20 #if !defined(CONFIG_USER_ONLY) #include "hw/s390x/storage-keys.h" @@ -1389,7 +1390,7 @@ static void do_cdsg(CPUS390XState *env, uint64_t addr, bool fail; =20 if (parallel) { -#ifndef CONFIG_ATOMIC128 +#if !HAVE_CMPXCHG128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else int mem_idx =3D cpu_mmu_index(env, false); @@ -1435,9 +1436,7 @@ void HELPER(cdsg_parallel)(CPUS390XState *env, uint64= _t addr, static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2, bool parallel) { -#if !defined(CONFIG_USER_ONLY) || defined(CONFIG_ATOMIC128) uint32_t mem_idx =3D cpu_mmu_index(env, false); -#endif uintptr_t ra =3D GETPC(); uint32_t fc =3D extract32(env->regs[0], 0, 8); uint32_t sc =3D extract32(env->regs[0], 8, 8); @@ -1465,18 +1464,20 @@ static uint32_t do_csst(CPUS390XState *env, uint32_= t r3, uint64_t a1, probe_write(env, a2, 0, mem_idx, ra); #endif =20 - /* Note that the compare-and-swap is atomic, and the store is atomic, = but - the complete operation is not. Therefore we do not need to assert = serial - context in order to implement this. That said, restart early if we= can't - support either operation that is supposed to be atomic. */ + /* + * Note that the compare-and-swap is atomic, and the store is atomic, + * but the complete operation is not. Therefore we do not need to + * assert serial context in order to implement this. That said, + * restart early if we can't support either operation that is supposed + * to be atomic. + */ if (parallel) { - int mask =3D 0; -#if !defined(CONFIG_ATOMIC64) - mask =3D -8; -#elif !defined(CONFIG_ATOMIC128) - mask =3D -16; + uint32_t max =3D 2; +#ifdef CONFIG_ATOMIC64 + max =3D 3; #endif - if (((4 << fc) | (1 << sc)) & mask) { + if ((HAVE_CMPXCHG128 ? 0 : fc + 2 > max) || + (HAVE_ATOMIC128 ? 0 : sc > max)) { cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); } } @@ -1546,16 +1547,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t= r3, uint64_t a1, Int128 cv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); Int128 ov; =20 - if (parallel) { -#ifdef CONFIG_ATOMIC128 - TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, me= m_idx); - ov =3D helper_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, = ra); - cc =3D !int128_eq(ov, cv); -#else - /* Note that we asserted !parallel above. */ - g_assert_not_reached(); -#endif - } else { + if (!parallel) { uint64_t oh =3D cpu_ldq_data_ra(env, a1 + 0, ra); uint64_t ol =3D cpu_ldq_data_ra(env, a1 + 8, ra); =20 @@ -1567,6 +1559,13 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t= r3, uint64_t a1, =20 cpu_stq_data_ra(env, a1 + 0, int128_gethi(nv), ra); cpu_stq_data_ra(env, a1 + 8, int128_getlo(nv), ra); + } else if (HAVE_CMPXCHG128) { + TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, me= m_idx); + ov =3D helper_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, = ra); + cc =3D !int128_eq(ov, cv); + } else { + /* Note that we asserted !parallel above. */ + g_assert_not_reached(); } =20 env->regs[r3 + 0] =3D int128_gethi(ov); @@ -1596,18 +1595,16 @@ static uint32_t do_csst(CPUS390XState *env, uint32_= t r3, uint64_t a1, cpu_stq_data_ra(env, a2, svh, ra); break; case 4: - if (parallel) { -#ifdef CONFIG_ATOMIC128 + if (!parallel) { + cpu_stq_data_ra(env, a2 + 0, svh, ra); + cpu_stq_data_ra(env, a2 + 8, svl, ra); + } else if (HAVE_ATOMIC128) { TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, me= m_idx); Int128 sv =3D int128_make128(svl, svh); helper_atomic_sto_be_mmu(env, a2, sv, oi, ra); -#else + } else { /* Note that we asserted !parallel above. */ g_assert_not_reached(); -#endif - } else { - cpu_stq_data_ra(env, a2 + 0, svh, ra); - cpu_stq_data_ra(env, a2 + 8, svl, ra); } break; default: @@ -2105,21 +2102,18 @@ static uint64_t do_lpq(CPUS390XState *env, uint64_t= addr, bool parallel) uintptr_t ra =3D GETPC(); uint64_t hi, lo; =20 - if (parallel) { -#ifndef CONFIG_ATOMIC128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else + if (!parallel) { + check_alignment(env, addr, 16, ra); + hi =3D cpu_ldq_data_ra(env, addr + 0, ra); + lo =3D cpu_ldq_data_ra(env, addr + 8, ra); + } else if (HAVE_ATOMIC128) { int mem_idx =3D cpu_mmu_index(env, false); TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); Int128 v =3D helper_atomic_ldo_be_mmu(env, addr, oi, ra); hi =3D int128_gethi(v); lo =3D int128_getlo(v); -#endif } else { - check_alignment(env, addr, 16, ra); - - hi =3D cpu_ldq_data_ra(env, addr + 0, ra); - lo =3D cpu_ldq_data_ra(env, addr + 8, ra); + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); } =20 env->retxl =3D lo; @@ -2142,21 +2136,17 @@ static void do_stpq(CPUS390XState *env, uint64_t ad= dr, { uintptr_t ra =3D GETPC(); =20 - if (parallel) { -#ifndef CONFIG_ATOMIC128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); - - Int128 v =3D int128_make128(low, high); - helper_atomic_sto_be_mmu(env, addr, v, oi, ra); -#endif - } else { + if (!parallel) { check_alignment(env, addr, 16, ra); - cpu_stq_data_ra(env, addr + 0, high, ra); cpu_stq_data_ra(env, addr + 8, low, ra); + } else if (HAVE_ATOMIC128) { + int mem_idx =3D cpu_mmu_index(env, false); + TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + Int128 v =3D int128_make128(low, high); + helper_atomic_sto_be_mmu(env, addr, v, oi, ra); + } else { + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); } } =20 --=20 2.17.1 From nobody Sun May 5 03:16:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:4864:20::72a Subject: [Qemu-devel] [PATCH v3 7/9] target/s390x: Split do_cdsg, do_lpq, do_stpq X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: qemu-s390x@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand --- target/s390x/mem_helper.c | 128 ++++++++++++++++++-------------------- 1 file changed, 61 insertions(+), 67 deletions(-) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index e106f61b4e..b5858d2fa2 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1380,57 +1380,58 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t = r1, uint32_t r2, return cc; } =20 -static void do_cdsg(CPUS390XState *env, uint64_t addr, - uint32_t r1, uint32_t r3, bool parallel) +void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, + uint32_t r1, uint32_t r3) { uintptr_t ra =3D GETPC(); Int128 cmpv =3D int128_make128(env->regs[r1 + 1], env->regs[r1]); Int128 newv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); Int128 oldv; + uint64_t oldh, oldl; bool fail; =20 - if (parallel) { -#if !HAVE_CMPXCHG128 - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); -#else - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); - oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, = ra); - fail =3D !int128_eq(oldv, cmpv); -#endif - } else { - uint64_t oldh, oldl; + check_alignment(env, addr, 16, ra); =20 - check_alignment(env, addr, 16, ra); + oldh =3D cpu_ldq_data_ra(env, addr + 0, ra); + oldl =3D cpu_ldq_data_ra(env, addr + 8, ra); =20 - oldh =3D cpu_ldq_data_ra(env, addr + 0, ra); - oldl =3D cpu_ldq_data_ra(env, addr + 8, ra); - - oldv =3D int128_make128(oldl, oldh); - fail =3D !int128_eq(oldv, cmpv); - if (fail) { - newv =3D oldv; - } - - cpu_stq_data_ra(env, addr + 0, int128_gethi(newv), ra); - cpu_stq_data_ra(env, addr + 8, int128_getlo(newv), ra); + oldv =3D int128_make128(oldl, oldh); + fail =3D !int128_eq(oldv, cmpv); + if (fail) { + newv =3D oldv; } =20 + cpu_stq_data_ra(env, addr + 0, int128_gethi(newv), ra); + cpu_stq_data_ra(env, addr + 8, int128_getlo(newv), ra); + env->cc_op =3D fail; env->regs[r1] =3D int128_gethi(oldv); env->regs[r1 + 1] =3D int128_getlo(oldv); } =20 -void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, - uint32_t r1, uint32_t r3) -{ - do_cdsg(env, addr, r1, r3, false); -} - void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr, uint32_t r1, uint32_t r3) { - do_cdsg(env, addr, r1, r3, true); + uintptr_t ra =3D GETPC(); + Int128 cmpv =3D int128_make128(env->regs[r1 + 1], env->regs[r1]); + Int128 newv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); + int mem_idx; + TCGMemOpIdx oi; + Int128 oldv; + bool fail; + + if (!HAVE_CMPXCHG128) { + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + } + + mem_idx =3D cpu_mmu_index(env, false); + oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); + fail =3D !int128_eq(oldv, cmpv); + + env->cc_op =3D fail; + env->regs[r1] =3D int128_gethi(oldv); + env->regs[r1 + 1] =3D int128_getlo(oldv); } =20 static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, @@ -2097,16 +2098,25 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t a= ddr) #endif =20 /* load pair from quadword */ -static uint64_t do_lpq(CPUS390XState *env, uint64_t addr, bool parallel) +uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t addr) { uintptr_t ra =3D GETPC(); uint64_t hi, lo; =20 - if (!parallel) { - check_alignment(env, addr, 16, ra); - hi =3D cpu_ldq_data_ra(env, addr + 0, ra); - lo =3D cpu_ldq_data_ra(env, addr + 8, ra); - } else if (HAVE_ATOMIC128) { + check_alignment(env, addr, 16, ra); + hi =3D cpu_ldq_data_ra(env, addr + 0, ra); + lo =3D cpu_ldq_data_ra(env, addr + 8, ra); + + env->retxl =3D lo; + return hi; +} + +uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uint64_t addr) +{ + uintptr_t ra =3D GETPC(); + uint64_t hi, lo; + + if (HAVE_ATOMIC128) { int mem_idx =3D cpu_mmu_index(env, false); TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); Int128 v =3D helper_atomic_ldo_be_mmu(env, addr, oi, ra); @@ -2120,27 +2130,23 @@ static uint64_t do_lpq(CPUS390XState *env, uint64_t= addr, bool parallel) return hi; } =20 -uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t addr) -{ - return do_lpq(env, addr, false); -} - -uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uint64_t addr) -{ - return do_lpq(env, addr, true); -} - /* store pair to quadword */ -static void do_stpq(CPUS390XState *env, uint64_t addr, - uint64_t low, uint64_t high, bool parallel) +void HELPER(stpq)(CPUS390XState *env, uint64_t addr, + uint64_t low, uint64_t high) { uintptr_t ra =3D GETPC(); =20 - if (!parallel) { - check_alignment(env, addr, 16, ra); - cpu_stq_data_ra(env, addr + 0, high, ra); - cpu_stq_data_ra(env, addr + 8, low, ra); - } else if (HAVE_ATOMIC128) { + check_alignment(env, addr, 16, ra); + cpu_stq_data_ra(env, addr + 0, high, ra); + cpu_stq_data_ra(env, addr + 8, low, ra); +} + +void HELPER(stpq_parallel)(CPUS390XState *env, uint64_t addr, + uint64_t low, uint64_t high) +{ + uintptr_t ra =3D GETPC(); + + if (HAVE_ATOMIC128) { int mem_idx =3D cpu_mmu_index(env, false); TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); Int128 v =3D int128_make128(low, high); @@ -2150,18 +2156,6 @@ static void do_stpq(CPUS390XState *env, uint64_t add= r, } } =20 -void HELPER(stpq)(CPUS390XState *env, uint64_t addr, - uint64_t low, uint64_t high) -{ - do_stpq(env, addr, low, high, false); -} - -void HELPER(stpq_parallel)(CPUS390XState *env, uint64_t addr, - uint64_t low, uint64_t high) -{ - do_stpq(env, addr, low, high, true); -} - /* Execute instruction. This instruction executes an insn modified with the contents of r1. It does not change the executed instruction in mem= ory; it does not change the program counter. --=20 2.17.1 From nobody Sun May 5 03:16:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538595818127266.3292520892296; Wed, 3 Oct 2018 12:43:38 -0700 (PDT) Received: from localhost ([::1]:52651 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7n3Y-0004Zi-Ue for importer@patchew.org; Wed, 03 Oct 2018 15:43:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59475) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7n05-0001gD-00 for qemu-devel@nongnu.org; Wed, 03 Oct 2018 15:40:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g7n03-00025y-A0 for qemu-devel@nongnu.org; Wed, 03 Oct 2018 15:40:00 -0400 Received: from mail-qt1-x831.google.com ([2607:f8b0:4864:20::831]:33366) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g7n02-00024f-Tk for qemu-devel@nongnu.org; Wed, 03 Oct 2018 15:39:59 -0400 Received: by mail-qt1-x831.google.com with SMTP id q40-v6so7323292qte.0 for ; Wed, 03 Oct 2018 12:39:58 -0700 (PDT) Received: from cloudburst.twiddle.net ([172.56.13.153]) by smtp.gmail.com with ESMTPSA id t16-v6sm1284946qth.68.2018.10.03.12.39.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Oct 2018 12:39:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JAldEmKZ57baz29qTLPDVIF0nqXzK08T0l7+NIorDqg=; b=S9UFJdeuPrGGeDfeyqfgLFum6sPoaLYgW0dB+xcPxZCIGbixhXB6MU+MjEsIHFePlo yF4Hc+yZQtfnpNEQeRfKvu+iWcBMoMXhKECFyyryUfonzyiFNIkbSbt/PoL8Fzb1ukmu Saxnvy4J12DLdO+xI0t9aBvZQXsSjs5yKlBok= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JAldEmKZ57baz29qTLPDVIF0nqXzK08T0l7+NIorDqg=; b=AT5/SElCU22sDATikwxZzFHo0RuMyCKazwGS/9SQZQpFUpF4dD9U6ztTZzdQZhB6Vz iONiNK8H82LsCiuOZm0ltsXS4J5XTVBC0qtgPU0fME24ugNISqpV0Wd4lqHReuZreTop U1OQcL10AwaLipXQJ76VyxqaNatnHjNGK2FzI5FxNY/qG6elyaVnZjXpM/OoIxQRS8W2 tIci8+aHk0xHlqN6AkT/+m97vyUWAsVPuJ3RO9v23Q3/pT8g+ELMI478LXvGoEO0RMn0 Oa1gy8JgOzmaWgUTxAdZ0HyaI6EQe/tsBBLmdLY9aE0fjyZWtPJ8F4rl0QIWhLL7u6aO a7/g== X-Gm-Message-State: ABuFfojXe92a4qdbLhwXGHEU+jAHEP1D5SGVbypuXiU6pN7KdAgIjPzt rWMczU3Pg5VdyQhvrdKvlyACErctOS0Bng== X-Google-Smtp-Source: ACcGV61Mc1PU+1kD/Rt9Dmz0K+Xvok9CPFpu0LVUbfsLXh8zgq5F/MvveMydvY3AJEvEsVgWrd5kFw== X-Received: by 2002:ac8:5293:: with SMTP id s19-v6mr2617731qtn.336.1538595597826; Wed, 03 Oct 2018 12:39:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Oct 2018 14:39:30 -0500 Message-Id: <20181003193931.18096-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181003193931.18096-1-richard.henderson@linaro.org> References: <20181003193931.18096-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::831 Subject: [Qemu-devel] [PATCH v3 8/9] target/s390x: Skip wout, cout helpers if op helper does not return X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When op raises an exception, it may not have initialized the output temps that would be written back by wout or cout. Cc: qemu-s390x@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand --- target/s390x/translate.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 7363aabf3a..7fad3ad8e9 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -6164,11 +6164,13 @@ static DisasJumpType translate_one(CPUS390XState *e= nv, DisasContext *s) if (insn->help_op) { ret =3D insn->help_op(s, &o); } - if (insn->help_wout) { - insn->help_wout(s, &f, &o); - } - if (insn->help_cout) { - insn->help_cout(s, &o); + if (ret !=3D DISAS_NORETURN) { + if (insn->help_wout) { + insn->help_wout(s, &f, &o); + } + if (insn->help_cout) { + insn->help_cout(s, &o); + } } =20 /* Free any temporaries created by the helpers. */ --=20 2.17.1 From nobody Sun May 5 03:16:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538596277762197.17519983155682; Wed, 3 Oct 2018 12:51:17 -0700 (PDT) Received: from localhost ([::1]:52698 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7nAy-000271-I7 for importer@patchew.org; Wed, 03 Oct 2018 15:51:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59533) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7n08-0001gT-DS for qemu-devel@nongnu.org; Wed, 03 Oct 2018 15:40:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g7n05-00028I-Ha for qemu-devel@nongnu.org; Wed, 03 Oct 2018 15:40:04 -0400 Received: from mail-qt1-x834.google.com ([2607:f8b0:4864:20::834]:45488) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g7n05-000273-3o for qemu-devel@nongnu.org; Wed, 03 Oct 2018 15:40:01 -0400 Received: by mail-qt1-x834.google.com with SMTP id l2-v6so7264780qtr.12 for ; Wed, 03 Oct 2018 12:40:00 -0700 (PDT) Received: from cloudburst.twiddle.net ([172.56.13.153]) by smtp.gmail.com with ESMTPSA id t16-v6sm1284946qth.68.2018.10.03.12.39.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 Oct 2018 12:39:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=g7N3N+A91Q9wKX2V+YBrSR0niQNnDAXh8g6joZORqms=; b=RX7khVBzRJsI+sTkn3vZPwx706CpQ5btzh5UYeiIdWrUM8E+8SW2OZc7lj0oiIYHZl QwJDheE6M5CALk/213B9XAKEvOqNmoGVY7B5CXxYnsDnfOWqbm9k60mNwBnG4Ztt+dY+ 11+lRBmVVaqsJilrKf6OjTOovuuK25B26DmLc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=g7N3N+A91Q9wKX2V+YBrSR0niQNnDAXh8g6joZORqms=; b=WPkFj4vEQhf0p/L5BfMfn21gZUgMg2DeII0Nc5bXVaJdgwgZwRrO1dF020BMpE1bXU edcc2hmpda3FwD1fG3iKvV7zjtjZq108IY/RA53mSwgE/ZVGiWXBL2o3E4yDH/mVe+H6 BVG4JFuNoW4H8RGlC2EX17wkjGodKBLdSdSd47vGaa8EsurbjVnXkYg8+bMiHzYK1xIA i3AEOewjoaYIo82LoYLd/5uzcX8dVP+9gZKI4t7EKV+AzVIpKFwV10OPZpBThEhF5eCf HR0v3Wcgz1o7VG4NdUZseegh4VLJXzgcxtZY5hCiBL4LXx/ozFKzitUvgvoDXZ8pxA58 8r4A== X-Gm-Message-State: ABuFfoi5bcWJvvbqt9Y3eTKPNPcgbC/9KrdcfDFR5cb5ia/w7qcSJd/w ZnA/jpvk2nPViSKteCxhyN3GgILY6x9ywg== X-Google-Smtp-Source: ACcGV63ry4wzo/JFjJuFWzy2pkdwl1pbXq9miLEciIUefdMjk/1F2BzB0Tuk29JdqdMiYENG5Vyp6w== X-Received: by 2002:ac8:1793:: with SMTP id o19-v6mr2592068qtj.98.1538595599906; Wed, 03 Oct 2018 12:39:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Oct 2018 14:39:31 -0500 Message-Id: <20181003193931.18096-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181003193931.18096-1-richard.henderson@linaro.org> References: <20181003193931.18096-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::834 Subject: [Qemu-devel] [PATCH v3 9/9] target/s390x: Check HAVE_ATOMIC128 and HAVE_CMPXCHG128 at translate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Cc: qemu-s390x@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand --- target/s390x/mem_helper.c | 40 +++++++++++++++++++-------------------- target/s390x/translate.c | 25 +++++++++++++++++------- 2 files changed, 38 insertions(+), 27 deletions(-) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index b5858d2fa2..490c43e6e6 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1420,9 +1420,7 @@ void HELPER(cdsg_parallel)(CPUS390XState *env, uint64= _t addr, Int128 oldv; bool fail; =20 - if (!HAVE_CMPXCHG128) { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } + assert(HAVE_CMPXCHG128); =20 mem_idx =3D cpu_mmu_index(env, false); oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); @@ -2115,16 +2113,17 @@ uint64_t HELPER(lpq_parallel)(CPUS390XState *env, u= int64_t addr) { uintptr_t ra =3D GETPC(); uint64_t hi, lo; + int mem_idx; + TCGMemOpIdx oi; + Int128 v; =20 - if (HAVE_ATOMIC128) { - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); - Int128 v =3D helper_atomic_ldo_be_mmu(env, addr, oi, ra); - hi =3D int128_gethi(v); - lo =3D int128_getlo(v); - } else { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } + assert(HAVE_ATOMIC128); + + mem_idx =3D cpu_mmu_index(env, false); + oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + v =3D helper_atomic_ldo_be_mmu(env, addr, oi, ra); + hi =3D int128_gethi(v); + lo =3D int128_getlo(v); =20 env->retxl =3D lo; return hi; @@ -2145,15 +2144,16 @@ void HELPER(stpq_parallel)(CPUS390XState *env, uint= 64_t addr, uint64_t low, uint64_t high) { uintptr_t ra =3D GETPC(); + int mem_idx; + TCGMemOpIdx oi; + Int128 v; =20 - if (HAVE_ATOMIC128) { - int mem_idx =3D cpu_mmu_index(env, false); - TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); - Int128 v =3D int128_make128(low, high); - helper_atomic_sto_be_mmu(env, addr, v, oi, ra); - } else { - cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); - } + assert(HAVE_ATOMIC128); + + mem_idx =3D cpu_mmu_index(env, false); + oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); + v =3D int128_make128(low, high); + helper_atomic_sto_be_mmu(env, addr, v, oi, ra); } =20 /* Execute instruction. This instruction executes an insn modified with diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 7fad3ad8e9..57fe74e4a0 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -44,6 +44,7 @@ #include "trace-tcg.h" #include "exec/translator.h" #include "exec/log.h" +#include "qemu/atomic128.h" =20 =20 /* Information that (most) every instruction needs to manipulate. */ @@ -2032,6 +2033,7 @@ static DisasJumpType op_cdsg(DisasContext *s, DisasOp= s *o) int r3 =3D get_field(s->fields, r3); int d2 =3D get_field(s->fields, d2); int b2 =3D get_field(s->fields, b2); + DisasJumpType ret =3D DISAS_NEXT; TCGv_i64 addr; TCGv_i32 t_r1, t_r3; =20 @@ -2039,17 +2041,20 @@ static DisasJumpType op_cdsg(DisasContext *s, Disas= Ops *o) addr =3D get_address(s, 0, b2, d2); t_r1 =3D tcg_const_i32(r1); t_r3 =3D tcg_const_i32(r3); - if (tb_cflags(s->base.tb) & CF_PARALLEL) { + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_helper_cdsg(cpu_env, addr, t_r1, t_r3); + } else if (HAVE_CMPXCHG128) { gen_helper_cdsg_parallel(cpu_env, addr, t_r1, t_r3); } else { - gen_helper_cdsg(cpu_env, addr, t_r1, t_r3); + gen_helper_exit_atomic(cpu_env); + ret =3D DISAS_NORETURN; } tcg_temp_free_i64(addr); tcg_temp_free_i32(t_r1); tcg_temp_free_i32(t_r3); =20 set_cc_static(s); - return DISAS_NEXT; + return ret; } =20 static DisasJumpType op_csst(DisasContext *s, DisasOps *o) @@ -3036,10 +3041,13 @@ static DisasJumpType op_lpd(DisasContext *s, DisasO= ps *o) =20 static DisasJumpType op_lpq(DisasContext *s, DisasOps *o) { - if (tb_cflags(s->base.tb) & CF_PARALLEL) { + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_helper_lpq(o->out, cpu_env, o->in2); + } else if (HAVE_ATOMIC128) { gen_helper_lpq_parallel(o->out, cpu_env, o->in2); } else { - gen_helper_lpq(o->out, cpu_env, o->in2); + gen_helper_exit_atomic(cpu_env); + return DISAS_NORETURN; } return_low128(o->out2); return DISAS_NEXT; @@ -4462,10 +4470,13 @@ static DisasJumpType op_stmh(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_stpq(DisasContext *s, DisasOps *o) { - if (tb_cflags(s->base.tb) & CF_PARALLEL) { + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_helper_stpq(cpu_env, o->in2, o->out2, o->out); + } else if (HAVE_ATOMIC128) { gen_helper_stpq_parallel(cpu_env, o->in2, o->out2, o->out); } else { - gen_helper_stpq(cpu_env, o->in2, o->out2, o->out); + gen_helper_exit_atomic(cpu_env); + return DISAS_NORETURN; } return DISAS_NEXT; } --=20 2.17.1