From nobody Tue Feb 10 02:00:41 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538498307376945.961725069673; Tue, 2 Oct 2018 09:38:27 -0700 (PDT) Received: from localhost ([::1]:44716 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7Ngf-00080F-7q for importer@patchew.org; Tue, 02 Oct 2018 12:38:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34810) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g7Neb-0006dc-Ri for qemu-devel@nongnu.org; Tue, 02 Oct 2018 12:36:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g7Neb-00055r-1B for qemu-devel@nongnu.org; Tue, 02 Oct 2018 12:36:09 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:51558) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g7NeY-00051B-EI; Tue, 02 Oct 2018 12:36:06 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1g7NeW-0007Hc-JH; Tue, 02 Oct 2018 17:36:04 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 2 Oct 2018 17:35:48 +0100 Message-Id: <20181002163556.10279-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20181002163556.10279-1-peter.maydell@linaro.org> References: <20181002163556.10279-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 05/13] target/arm: Add some comments in Thumb decode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add some comments to the Thumb decoder indicating what bits of the instruction have been decoded at various points in the code. This is not an exhaustive set of comments; we're gradually adding comments as we work with particular bits of the code. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- Specifically, I figured these out as I was going through looking for the insns which write SP. These comments turn out not to be relevant to those instructions, but I don't want to throw them away. --- target/arm/translate.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 25a8fe672f5..fcb33b8a503 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10623,6 +10623,10 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) tmp2 =3D load_reg(s, rm); if ((insn & 0x70) !=3D 0) goto illegal_op; + /* + * 0b1111_1010_0xxx_xxxx_1111_xxxx_0000_xxxx: + * - MOV, MOVS (register-shifted register), flagsetting + */ op =3D (insn >> 21) & 3; logic_cc =3D (insn & (1 << 20)) !=3D 0; gen_arm_shift_reg(tmp, op, tmp2, logic_cc); @@ -11674,7 +11678,11 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) rd =3D insn & 7; op =3D (insn >> 11) & 3; if (op =3D=3D 3) { - /* add/subtract */ + /* + * 0b0001_1xxx_xxxx_xxxx + * - Add, subtract (three low registers) + * - Add, subtract (two low registers and immediate) + */ rn =3D (insn >> 3) & 7; tmp =3D load_reg(s, rn); if (insn & (1 << 10)) { @@ -11711,7 +11719,10 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) } break; case 2: case 3: - /* arithmetic large immediate */ + /* + * 0b001x_xxxx_xxxx_xxxx + * - Add, subtract, compare, move (one low register and immediate) + */ op =3D (insn >> 11) & 3; rd =3D (insn >> 8) & 0x7; if (op =3D=3D 0) { /* mov */ @@ -11848,7 +11859,10 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) break; } =20 - /* data processing register */ + /* + * 0b0100_00xx_xxxx_xxxx + * - Data-processing (two low registers) + */ rd =3D insn & 7; rm =3D (insn >> 3) & 7; op =3D (insn >> 6) & 0xf; --=20 2.19.0