From nobody Sun Feb 8 19:17:05 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538344283273571.185062003343; Sun, 30 Sep 2018 14:51:23 -0700 (PDT) Received: from localhost ([::1]:57780 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g6jcS-0007uL-3p for importer@patchew.org; Sun, 30 Sep 2018 17:51:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44748) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g6jaX-0006lZ-Il for qemu-devel@nongnu.org; Sun, 30 Sep 2018 17:49:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g6jZC-0007iS-2z for qemu-devel@nongnu.org; Sun, 30 Sep 2018 17:47:54 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:40581) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g6jZB-0007iD-SF for qemu-devel@nongnu.org; Sun, 30 Sep 2018 17:47:54 -0400 Received: by mail-wr1-x429.google.com with SMTP id y8-v6so11676589wrh.7 for ; Sun, 30 Sep 2018 14:47:53 -0700 (PDT) Received: from x1.local ([80.31.72.241]) by smtp.gmail.com with ESMTPSA id w5-v6sm6492838wmf.31.2018.09.30.14.47.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 30 Sep 2018 14:47:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JjAmqROZhCRNep1HJyK8QW2ml2MVqT06YHMDZAZoPLA=; b=pQQ9TgQGTbpbnlhTnNDH+auI1Tfe8Vewrqa1O0incLjzVlIIj2WS+BXUQrf3gT0j0q Qtl1ZAz2RKOB0xZKThyv4A6w5OTw4vHY9cTr9F+YROOaaDIOW5kdw7MwlfdeNq7U2h/6 jbNJLm9SA09G5ctceAVRqwmpjMMtEyiHVup+gKg0mQXKZJA0FQsajcem4tgMWRDdojUp U/u4rPA389/imM3FwlLDuEY69Th54uE/nsdgMToQC2rgqmwHe5iRokleQNFGau5keNSj wd6R06OFEwdN6pBokTLRVjQnPHlWkBXwEMhgKDV8FH8deszAsd0Ia3BhA//01ZL7/EHg nh4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=JjAmqROZhCRNep1HJyK8QW2ml2MVqT06YHMDZAZoPLA=; b=hXeSt/oAT4Ll89ARDGeC9JuMtgb7YEKvlHckgrxihL6V2CXHQbj6T07Xl3wU1Enk5p S1Hpwr6SCobebsWhjHM6zgyyUijPkXai7cvTtfFYUCCnadivLrNsNQQu1LLL84P7/yVc 8fVCBDJlMlZlbjFn7ArMdJfnouIThqzdXyU5yg238U9F0LO97IlZD1BCbmkad0Rv1v8I kyt9IMf9QjhCBU/di2pi2tNkmCEmgYuuOf2Cr98SNNhOosKjC4D6aPpKOBTsVvP6uCOv Mu7wawKfhmi1yoN4B+dfjWtqqVjhLjW6N0qPQNW34rgEpYmcGAf33vgSWcQ65TAEK7WE /u1w== X-Gm-Message-State: ABuFfohyFhz5sVosatAFBhrW6e6alxD+ND1qvGoSZxLhjR75iWN4eOiW /bQsbD3CsUfRAlO8cRxbGf4= X-Google-Smtp-Source: ACcGV62j83Y2kvKw4DMeUQpx8+8eAyXgubGGw38x9+A2IeOR1geHrYPbWzFru9QfPalsU0DU1qgfjw== X-Received: by 2002:adf:b243:: with SMTP id y3-v6mr4975317wra.90.1538344072845; Sun, 30 Sep 2018 14:47:52 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Aurelien Jarno , Aleksandar Markovic Date: Sun, 30 Sep 2018 23:47:43 +0200 Message-Id: <20180930214744.27580-4-f4bug@amsat.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180930214744.27580-1-f4bug@amsat.org> References: <20180930214744.27580-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::429 Subject: [Qemu-devel] [PATCH v3 3/4] target/mips: Clean the 'insn_flags' namespace X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Let space available for the ASE_DSPR3 entry. Suggested-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Aleksandar Markovic --- target/mips/mips-defs.h | 85 ++++++++++++++++++++++++----------------- 1 file changed, 51 insertions(+), 34 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index c0c5a98ef1..f9e99f866f 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -22,40 +22,57 @@ #endif #endif =20 -/* Masks used to mark instructions to indicate which ISA level they - were introduced in. */ -#define ISA_MIPS1 0x00000001 -#define ISA_MIPS2 0x00000002 -#define ISA_MIPS3 0x00000004 -#define ISA_MIPS4 0x00000008 -#define ISA_MIPS5 0x00000010 -#define ISA_MIPS32 0x00000020 -#define ISA_MIPS32R2 0x00000040 -#define ISA_MIPS64 0x00000080 -#define ISA_MIPS64R2 0x00000100 -#define ISA_MIPS32R3 0x00000200 -#define ISA_MIPS64R3 0x00000400 -#define ISA_MIPS32R5 0x00000800 -#define ISA_MIPS64R5 0x00001000 -#define ISA_MIPS32R6 0x00002000 -#define ISA_MIPS64R6 0x00004000 -#define ISA_NANOMIPS32 0x00008000 - -/* MIPS ASEs. */ -#define ASE_MIPS16 0x00010000 -#define ASE_MIPS3D 0x00020000 -#define ASE_MDMX 0x00040000 -#define ASE_DSP 0x00080000 -#define ASE_DSPR2 0x00100000 -#define ASE_MT 0x00200000 -#define ASE_SMARTMIPS 0x00400000 -#define ASE_MICROMIPS 0x00800000 -#define ASE_MSA 0x01000000 - -/* Chip specific instructions. */ -#define INSN_LOONGSON2E 0x20000000 -#define INSN_LOONGSON2F 0x40000000 -#define INSN_VR54XX 0x80000000 +/* +* insn_flags: mask used to mark instructions to indicate which ISA +* level they were introduced in. +*/ + +/* + * bits 0-31 MIPS base instruction sets + */ +#define ISA_MIPS1 0x0000000000000001 +#define ISA_MIPS2 0x0000000000000002 +#define ISA_MIPS3 0x0000000000000004 +#define ISA_MIPS4 0x0000000000000008 +#define ISA_MIPS5 0x0000000000000010 +#define ISA_MIPS32 0x0000000000000020 +#define ISA_MIPS32R2 0x0000000000000040 +#define ISA_MIPS64 0x0000000000000080 +#define ISA_MIPS64R2 0x0000000000000100 +#define ISA_MIPS32R3 0x0000000000000200 +#define ISA_MIPS64R3 0x0000000000000400 +#define ISA_MIPS32R5 0x0000000000000800 +#define ISA_MIPS64R5 0x0000000000001000 +#define ISA_MIPS32R6 0x0000000000002000 +#define ISA_MIPS64R6 0x0000000000004000 +#define ISA_NANOMIPS32 0x0000000000008000 + +/* + * bits 32-47 MIPS ASEs + */ +#define ASE_MIPS16 0x0000000100000000ULL +#define ASE_MIPS3D 0x0000000200000000ULL +#define ASE_MDMX 0x0000000400000000ULL +#define ASE_DSP 0x0000000800000000ULL +#define ASE_DSPR2 0x0000001000000000ULL +#define ASE_MT 0x0000004000000000ULL +#define ASE_SMARTMIPS 0x0000008000000000ULL +#define ASE_MICROMIPS 0x0000010000000000ULL +#define ASE_MSA 0x0000020000000000ULL + +/* + * bits 48-55 vendor-specific base instruction sets + */ +#define INSN_LOONGSON2E 0x0001000000000000ULL +#define INSN_LOONGSON2F 0x0002000000000000ULL +#define INSN_VR54XX 0x0004000000000000ULL + +/* + * bits 56-63 vendor-specific ASEs + * + * Example: Igenic ASE_MXU and ASE MXU2 + */ + =20 /* MIPS CPU defines. */ #define CPU_MIPS1 (ISA_MIPS1) --=20 2.19.0