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X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH v3 1/4] target/mips: Increase the 'supported instructions' flags holder size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Currently this holder is limited to at most 32 flags on a 32-bit architecture, which lets an unique bit available for another 'chip specific instructions' flag. Relax this limit using a 64-bit integer. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Aleksandar Markovic --- target/mips/cpu.h | 2 +- target/mips/internal.h | 2 +- target/mips/translate.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 28af4d191c..f2a5031fd2 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -614,7 +614,7 @@ struct CPUMIPSState { int CCRes; /* Cycle count resolution/divisor */ uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ - int insn_flags; /* Supported instruction set */ + uint64_t insn_flags; /* Supported instruction set */ =20 /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; diff --git a/target/mips/internal.h b/target/mips/internal.h index e41051f8e6..bfe83ee613 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -59,7 +59,7 @@ struct mips_def_t { int32_t CP0_PageGrain_rw_bitmask; int32_t CP0_PageGrain; target_ulong CP0_EBaseWG_rw_bitmask; - int insn_flags; + uint64_t insn_flags; enum mips_mmu_types mmu_type; }; =20 diff --git a/target/mips/translate.c b/target/mips/translate.c index ab16cdb911..b19d91bc1f 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1447,7 +1447,7 @@ typedef struct DisasContext { target_ulong saved_pc; target_ulong page_start; uint32_t opcode; - int insn_flags; + uint64_t insn_flags; int32_t CP0_Config1; int32_t CP0_Config3; int32_t CP0_Config5; @@ -1870,7 +1870,7 @@ static inline void check_dspr2(DisasContext *ctx) =20 /* This code generates a "reserved instruction" exception if the CPU does not support the instruction set corresponding to flags. */ -static inline void check_insn(DisasContext *ctx, int flags) +static inline void check_insn(DisasContext *ctx, uint64_t flags) { if (unlikely(!(ctx->insn_flags & flags))) { generate_exception_end(ctx, EXCP_RI); @@ -1880,7 +1880,7 @@ static inline void check_insn(DisasContext *ctx, int = flags) /* This code generates a "reserved instruction" exception if the CPU has corresponding flag set which indicates that the instruction has been removed. */ -static inline void check_insn_opc_removed(DisasContext *ctx, int flags) +static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flag= s) { if (unlikely(ctx->insn_flags & flags)) { generate_exception_end(ctx, EXCP_RI); --=20 2.19.0 From nobody Wed Nov 5 22:17:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538344286269664.9678043751762; Sun, 30 Sep 2018 14:51:26 -0700 (PDT) Received: from localhost ([::1]:57781 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g6jcT-0007xP-NL for importer@patchew.org; Sun, 30 Sep 2018 17:51:17 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44748) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g6jaY-0006lZ-ER for qemu-devel@nongnu.org; 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Sun, 30 Sep 2018 14:47:51 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Aurelien Jarno , Aleksandar Markovic Date: Sun, 30 Sep 2018 23:47:42 +0200 Message-Id: <20180930214744.27580-3-f4bug@amsat.org> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20180930214744.27580-1-f4bug@amsat.org> References: <20180930214744.27580-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42f Subject: [Qemu-devel] [PATCH v3 2/4] target/mips: Remove definitions that are only used once X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 There is no gain in adding cpu definition which is used only once. Use the chip specific flags directly in place. This also clears the 'MIPS CPU defines' namespace. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/mips-defs.h | 4 ---- target/mips/translate_init.inc.c | 6 +++--- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index c8e99791ad..c0c5a98ef1 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -62,10 +62,6 @@ #define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) -#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) -#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) -#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F) - #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) =20 /* MIPS Technologies "Release 1" */ diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.= inc.c index b3320b9dc7..96b7876ce2 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -527,7 +527,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 40, .PABITS =3D 32, - .insn_flags =3D CPU_VR54XX, + .insn_flags =3D CPU_MIPS4 | INSN_VR54XX, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -737,7 +737,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 40, .PABITS =3D 40, - .insn_flags =3D CPU_LOONGSON2E, + .insn_flags =3D CPU_MIPS3 | INSN_LOONGSON2E, .mmu_type =3D MMU_TYPE_R4000, }, { @@ -757,7 +757,7 @@ const mips_def_t mips_defs[] =3D .CP1_fcr31_rw_bitmask =3D 0xFF83FFFF, .SEGBITS =3D 40, .PABITS =3D 40, - .insn_flags =3D CPU_LOONGSON2F, + .insn_flags =3D CPU_MIPS3 | INSN_LOONGSON2F, .mmu_type =3D MMU_TYPE_R4000, }, { --=20 2.19.0 From nobody Wed Nov 5 22:17:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:4864:20::429 Subject: [Qemu-devel] [PATCH v3 3/4] target/mips: Clean the 'insn_flags' namespace X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Let space available for the ASE_DSPR3 entry. Suggested-by: Aleksandar Markovic Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Aleksandar Markovic --- target/mips/mips-defs.h | 85 ++++++++++++++++++++++++----------------- 1 file changed, 51 insertions(+), 34 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index c0c5a98ef1..f9e99f866f 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -22,40 +22,57 @@ #endif #endif =20 -/* Masks used to mark instructions to indicate which ISA level they - were introduced in. */ -#define ISA_MIPS1 0x00000001 -#define ISA_MIPS2 0x00000002 -#define ISA_MIPS3 0x00000004 -#define ISA_MIPS4 0x00000008 -#define ISA_MIPS5 0x00000010 -#define ISA_MIPS32 0x00000020 -#define ISA_MIPS32R2 0x00000040 -#define ISA_MIPS64 0x00000080 -#define ISA_MIPS64R2 0x00000100 -#define ISA_MIPS32R3 0x00000200 -#define ISA_MIPS64R3 0x00000400 -#define ISA_MIPS32R5 0x00000800 -#define ISA_MIPS64R5 0x00001000 -#define ISA_MIPS32R6 0x00002000 -#define ISA_MIPS64R6 0x00004000 -#define ISA_NANOMIPS32 0x00008000 - -/* MIPS ASEs. */ -#define ASE_MIPS16 0x00010000 -#define ASE_MIPS3D 0x00020000 -#define ASE_MDMX 0x00040000 -#define ASE_DSP 0x00080000 -#define ASE_DSPR2 0x00100000 -#define ASE_MT 0x00200000 -#define ASE_SMARTMIPS 0x00400000 -#define ASE_MICROMIPS 0x00800000 -#define ASE_MSA 0x01000000 - -/* Chip specific instructions. */ -#define INSN_LOONGSON2E 0x20000000 -#define INSN_LOONGSON2F 0x40000000 -#define INSN_VR54XX 0x80000000 +/* +* insn_flags: mask used to mark instructions to indicate which ISA +* level they were introduced in. +*/ + +/* + * bits 0-31 MIPS base instruction sets + */ +#define ISA_MIPS1 0x0000000000000001 +#define ISA_MIPS2 0x0000000000000002 +#define ISA_MIPS3 0x0000000000000004 +#define ISA_MIPS4 0x0000000000000008 +#define ISA_MIPS5 0x0000000000000010 +#define ISA_MIPS32 0x0000000000000020 +#define ISA_MIPS32R2 0x0000000000000040 +#define ISA_MIPS64 0x0000000000000080 +#define ISA_MIPS64R2 0x0000000000000100 +#define ISA_MIPS32R3 0x0000000000000200 +#define ISA_MIPS64R3 0x0000000000000400 +#define ISA_MIPS32R5 0x0000000000000800 +#define ISA_MIPS64R5 0x0000000000001000 +#define ISA_MIPS32R6 0x0000000000002000 +#define ISA_MIPS64R6 0x0000000000004000 +#define ISA_NANOMIPS32 0x0000000000008000 + +/* + * bits 32-47 MIPS ASEs + */ +#define ASE_MIPS16 0x0000000100000000ULL +#define ASE_MIPS3D 0x0000000200000000ULL +#define ASE_MDMX 0x0000000400000000ULL +#define ASE_DSP 0x0000000800000000ULL +#define ASE_DSPR2 0x0000001000000000ULL +#define ASE_MT 0x0000004000000000ULL +#define ASE_SMARTMIPS 0x0000008000000000ULL +#define ASE_MICROMIPS 0x0000010000000000ULL +#define ASE_MSA 0x0000020000000000ULL + +/* + * bits 48-55 vendor-specific base instruction sets + */ +#define INSN_LOONGSON2E 0x0001000000000000ULL +#define INSN_LOONGSON2F 0x0002000000000000ULL +#define INSN_VR54XX 0x0004000000000000ULL + +/* + * bits 56-63 vendor-specific ASEs + * + * Example: Igenic ASE_MXU and ASE MXU2 + */ + =20 /* MIPS CPU defines. */ #define CPU_MIPS1 (ISA_MIPS1) --=20 2.19.0 From nobody Wed Nov 5 22:17:04 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH v3 4/4] MAINTAINERS: Voluntary to review hobbyist MIPS contributions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index ce7c351afa..2708745bf7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -188,6 +188,7 @@ F: disas/microblaze.c MIPS M: Aurelien Jarno M: Aleksandar Markovic +R: Philippe Mathieu-Daud=C3=A9 S: Maintained F: target/mips/ F: hw/mips/ @@ -1948,6 +1949,7 @@ F: disas/i386.c =20 MIPS target M: Aurelien Jarno +R: Philippe Mathieu-Daud=C3=A9 S: Maintained F: tcg/mips/ F: disas/mips.c --=20 2.19.0