From nobody Thu Nov 6 08:30:59 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538083785038716.7835792193366; Thu, 27 Sep 2018 14:29:45 -0700 (PDT) Received: from localhost ([::1]:39478 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g5dqp-0004PC-RO for importer@patchew.org; Thu, 27 Sep 2018 17:29:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53627) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g5doI-0002I3-Lz for qemu-devel@nongnu.org; Thu, 27 Sep 2018 17:26:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g5dmR-0000Mh-7w for qemu-devel@nongnu.org; Thu, 27 Sep 2018 17:25:06 -0400 Received: from mx1.redhat.com ([209.132.183.28]:58424) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g5dmQ-0000AY-7P for qemu-devel@nongnu.org; Thu, 27 Sep 2018 17:25:02 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id AFA34308A95D; Thu, 27 Sep 2018 21:24:53 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-187.rdu2.redhat.com [10.10.120.187]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2AA6D5D6A9; Thu, 27 Sep 2018 21:24:51 +0000 (UTC) From: Laszlo Ersek To: qemu devel list Date: Thu, 27 Sep 2018 23:24:37 +0200 Message-Id: <20180927212438.32024-4-lersek@redhat.com> In-Reply-To: <20180927212438.32024-1-lersek@redhat.com> References: <20180927212438.32024-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.41]); Thu, 27 Sep 2018 21:24:53 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 3/4] hw/pci-host/x86: extract get_pci_hole64_start_value() helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Igor Mammedov , Alex Williamson , Gerd Hoffmann , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Expose the calculated "hole64 start" GPAs as plain uint64_t values, extracting the internals of the current property getters. This patch doesn't change behavior. Cc: "Michael S. Tsirkin" Cc: Alex Williamson Cc: Gerd Hoffmann Cc: Igor Mammedov Cc: Marcel Apfelbaum Signed-off-by: Laszlo Ersek Reviewed-by: Marcel Apfelbaum --- Notes: v2: - no changes; pick up Marcel's R-b hw/pci-host/piix.c | 15 +++++++++++---- hw/pci-host/q35.c | 15 +++++++++++---- 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index 0e608347c1f0..0df91e002076 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -249,9 +249,7 @@ static void i440fx_pcihost_get_pci_hole_end(Object *obj= , Visitor *v, * the 64bit PCI hole will start after "over 4G RAM" and the * reserved space for memory hotplug if any. */ -static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v, - const char *name, - void *opaque, Error **errp) +static uint64_t i440fx_pcihost_get_pci_hole64_start_value(Object *obj) { PCIHostState *h =3D PCI_HOST_BRIDGE(obj); I440FXState *s =3D I440FX_PCI_HOST_BRIDGE(obj); @@ -263,7 +261,16 @@ static void i440fx_pcihost_get_pci_hole64_start(Object= *obj, Visitor *v, if (!value && s->pci_hole64_fix) { value =3D pc_pci_hole64_start(); } - visit_type_uint64(v, name, &value, errp); + return value; +} + +static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v, + const char *name, + void *opaque, Error **errp) +{ + uint64_t hole64_start =3D i440fx_pcihost_get_pci_hole64_start_value(ob= j); + + visit_type_uint64(v, name, &hole64_start, errp); } =20 /* diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 02f95765880a..8acf942b5e65 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -109,9 +109,7 @@ static void q35_host_get_pci_hole_end(Object *obj, Visi= tor *v, * the 64bit PCI hole will start after "over 4G RAM" and the * reserved space for memory hotplug if any. */ -static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, - const char *name, void *opaque, - Error **errp) +static uint64_t q35_host_get_pci_hole64_start_value(Object *obj) { PCIHostState *h =3D PCI_HOST_BRIDGE(obj); Q35PCIHost *s =3D Q35_HOST_DEVICE(obj); @@ -123,7 +121,16 @@ static void q35_host_get_pci_hole64_start(Object *obj,= Visitor *v, if (!value && s->pci_hole64_fix) { value =3D pc_pci_hole64_start(); } - visit_type_uint64(v, name, &value, errp); + return value; +} + +static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + uint64_t hole64_start =3D q35_host_get_pci_hole64_start_value(obj); + + visit_type_uint64(v, name, &hole64_start, errp); } =20 /* --=20 2.14.1.3.gb7cf6e02401b