From nobody Thu Nov 6 08:30:59 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15380839850551006.5011489400798; Thu, 27 Sep 2018 14:33:05 -0700 (PDT) Received: from localhost ([::1]:39525 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g5duB-0006dc-Ng for importer@patchew.org; Thu, 27 Sep 2018 17:33:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53588) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g5doF-0002Hp-C2 for qemu-devel@nongnu.org; Thu, 27 Sep 2018 17:26:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g5dmR-0000Mn-7v for qemu-devel@nongnu.org; Thu, 27 Sep 2018 17:25:07 -0400 Received: from mx1.redhat.com ([209.132.183.28]:42014) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g5dmQ-00008K-60 for qemu-devel@nongnu.org; Thu, 27 Sep 2018 17:25:02 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id CCF3A3086249; Thu, 27 Sep 2018 21:24:51 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-187.rdu2.redhat.com [10.10.120.187]) by smtp.corp.redhat.com (Postfix) with ESMTP id 442AB5D772; Thu, 27 Sep 2018 21:24:50 +0000 (UTC) From: Laszlo Ersek To: qemu devel list Date: Thu, 27 Sep 2018 23:24:36 +0200 Message-Id: <20180927212438.32024-3-lersek@redhat.com> In-Reply-To: <20180927212438.32024-1-lersek@redhat.com> References: <20180927212438.32024-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.49]); Thu, 27 Sep 2018 21:24:51 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 2/4] tests/bios-tables-test: add 64-bit PCI MMIO aperture round-up test on Q35 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Igor Mammedov , Alex Williamson , Gerd Hoffmann , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In commit 9fa99d2519cb ("hw/pci-host: Fix x86 Host Bridges 64bit PCI hole", 2017-11-16), we meant to expose such a 64-bit PCI MMIO aperture in the ACPI DSDT that would be at least as large as the new "pci-hole64-size" property (2GB on i440fx, 32GB on q35). The goal was to offer "enough" 64-bit MMIO aperture to the guest OS for hotplug purposes. Currently the aperture is extended relative to a possibly incorrect base. This may result in an aperture size that is smaller than the intent of commit 9fa99d2519cb. We're going to fix the error in a later patch in this series; now we just add a test case that reproduces and captures the problem. In the fix, the test data will be updated as well. In the test case being added: - use 128 MB initial RAM size, - ask for one DIMM hotplug slot, - ask for 2 GB maximum RAM size, - use a pci-testdev with a 64-bit BAR of 2 GB size. Consequences: (1) In pc_memory_init() [hw/i386/pc.c], the DIMM hotplug area size is initially set to 2048-128 =3D 1920 MB. (Maximum RAM size minus initial RAM size.) (2) The DIMM area base is set to 4096 MB (because the initial RAM is only 128 MB -- there is no initial "high RAM"). (3) Due to commit 085f8e88ba73 ("pc: count in 1Gb hugepage alignment when sizing hotplug-memory container", 2014-11-24), we add 1 GB for the one DIMM hotplug slot that was specified. This sets the DIMM area size to 1920+1024 =3D 2944 MB. (4) The reserved-memory-end address (exclusive) is set to 4096 + 2944 =3D 7040 MB (DIMM area base plus DIMM area size). (5) The reserved-memory-end address is rounded up to GB alignment, yielding 7 GB (7168 MB). (6) Given the 2 GB BAR size of pci-testdev, SeaBIOS allocates said 64-bit BAR in 64-bit address space. (7) Because reserved-memory-end is at 7 GB, it is unaligned for the 2 GB BAR. Therefore SeaBIOS allocates the BAR at 8 GB. QEMU then (correctly) assigns the root bridge aperture base this BAR address, to be exposed in \_SB.PCI0._CRS. (8) The intent of commit 9fa99d2519cb dictates that QEMU extend the aperture size to 32 GB, implying a 40 GB end address. However, QEMU performs the extension relative to reserved-memory-end (7 GB), not relative to the bridge aperture base that was correctly deduced from SeaBIOS's BAR programming (8 GB). Therefore we see 39 GB as the aperture end address in \_SB.PCI0._CRS: > QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, = ReadWrite, > 0x0000000000000000, // Granularity > 0x0000000200000000, // Range Minimum > 0x00000009BFFFFFFF, // Range Maximum > 0x0000000000000000, // Translation Offset > 0x00000007C0000000, // Length > ,, , AddressRangeMemory, TypeStatic) Cc: "Michael S. Tsirkin" Cc: Alex Williamson Cc: Gerd Hoffmann Cc: Igor Mammedov Cc: Marcel Apfelbaum Signed-off-by: Laszlo Ersek Reviewed-by: Marcel Apfelbaum --- Notes: v2: - new patch - rely on Gerd's "[PATCH] pci-testdev: add optional memory bar" at tests/bios-tables-test.c | 16 ++++++++++++++++ tests/acpi-test-data/q35/DSDT.mmio64 | Bin 0 -> 8947 bytes tests/acpi-test-data/q35/SRAT.mmio64 | Bin 0 -> 224 bytes 3 files changed, 16 insertions(+) create mode 100644 tests/acpi-test-data/q35/DSDT.mmio64 create mode 100644 tests/acpi-test-data/q35/SRAT.mmio64 diff --git a/tests/bios-tables-test.c b/tests/bios-tables-test.c index 4e24930c4bf9..9dd88f9d868a 100644 --- a/tests/bios-tables-test.c +++ b/tests/bios-tables-test.c @@ -708,6 +708,21 @@ static void test_acpi_q35_tcg_bridge(void) free_test_data(&data); } =20 +static void test_acpi_q35_tcg_mmio64(void) +{ + test_data data =3D { + .machine =3D MACHINE_Q35, + .variant =3D ".mmio64", + .required_struct_types =3D base_required_struct_types, + .required_struct_types_len =3D ARRAY_SIZE(base_required_struct_typ= es) + }; + + test_acpi_one("-m 128M,slots=3D1,maxmem=3D2G " + "-device pci-testdev,membar=3D2G", + &data); + free_test_data(&data); +} + static void test_acpi_piix4_tcg_cphp(void) { test_data data; @@ -875,6 +890,7 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/piix4/bridge", test_acpi_piix4_tcg_bridge); qtest_add_func("acpi/q35", test_acpi_q35_tcg); qtest_add_func("acpi/q35/bridge", test_acpi_q35_tcg_bridge); + qtest_add_func("acpi/q35/mmio64", test_acpi_q35_tcg_mmio64); qtest_add_func("acpi/piix4/ipmi", test_acpi_piix4_tcg_ipmi); qtest_add_func("acpi/q35/ipmi", test_acpi_q35_tcg_ipmi); qtest_add_func("acpi/piix4/cpuhp", test_acpi_piix4_tcg_cphp); diff --git a/tests/acpi-test-data/q35/DSDT.mmio64 b/tests/acpi-test-data/q3= 5/DSDT.mmio64 new file mode 100644 index 0000000000000000000000000000000000000000..498c535f2a85a058b76a0a5ebc6= 7c3d5236c3265 GIT binary patch literal 8947 zcmb7KTW=3Df38J*=3D#t05&VrL`MZVVG^`JALxMpBmN0_Yk)rWwXZ=3DDKSe#?%#J*>q<~lta*>+ieaS7CVjK@3WqZ(Q z`i083+_ndvY^Ci%#qThCaJA`MZfj<+-Sske-(;Tu>gs4KJKQZUai<^rd;NzC=3DdXPA z>g~$?7ytE#yKnLg0BiWR@x30=3DNBDloFN7oK^WmQL0nx>=3D)zQ-DLvdL4Idminspnon zc2TO;@taOy%dyt%M!VKiW3@0sj1BYAX!inEVC>r;^DNW9<50ZxN^Q$8wLAWxQDFc1Uv|vKd;v4j=3D@yH8{-aq; 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