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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id l26-v6sm5395884pfg.161.2018.09.27.14.13.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 27 Sep 2018 14:13:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5ZsYiXvYqPMOwtzKs1izA74eJT68haQXBetiywP0i7Y=; b=PEWMavTQg1jOBST4glbATo04ZyauBQWRiYttsBU3JcFht+HeT9CdZMXdziWffo/SVu zNusUY1I0WeZ6pSefwhOCTqtbuVaeZR75mp5v0z7JfotDVj6l65akjIzRRFWCq1xsLjT Datb4qlc4MO1DbBdYTjMX8M7kfVddAzdIS86w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5ZsYiXvYqPMOwtzKs1izA74eJT68haQXBetiywP0i7Y=; b=p5fKm5BB1lLl2cI0iuTa+kL/dLes7qdWMeammZ5lHeLdY0vHxh3L+Jw7FmSoNtc2+g zzs1DEHi9x1Ez39+nhug0KImV83P9kq8PROZOrKWXDEEPeKEYRqBlT6WmgywBQLUYMvf Nb8v9s5cMI/iKIzrnRTqh0/eTG5KdkltxeJ3KWluyDguxSG1AQgWw3NN8RyI48830zaF nKrHTOhg2V6g83r0C5/E5YpOkapdGh+zN2JgshA4KkzNMzGUUdahwUvoCnjgku1QEQhg wGE5FU+vY6yyrDbDM1k3C1276+wpVNigQMEd/aZPl/+Q0q4CdW4T1BxcuOImMN4MjbiG sDRg== X-Gm-Message-State: ABuFfohs0DRiS+O4xoRA/u9AF074KDUgUbnoxYq3NkRnc7I4Yw6hcRA2 LI9sX/V5KBJxj/kInCWYZyqgkXQBJ+c= X-Google-Smtp-Source: ACcGV609oLR+LVN4wUVXbwP9zoTKbJZ9qGJ8NUM9FnEsPB5jjWWuDfSfZLM8LwH/QOooZGFw0h8TbQ== X-Received: by 2002:a63:cc4f:: with SMTP id q15-v6mr11901900pgi.217.1538082815589; Thu, 27 Sep 2018 14:13:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2018 14:13:20 -0700 Message-Id: <20180927211322.16118-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180927211322.16118-1-richard.henderson@linaro.org> References: <20180927211322.16118-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v2 7/9] target/arm: Convert t32ee from feature bit to isar3 test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 6 +++++- linux-user/elfload.c | 2 +- target/arm/cpu.c | 4 ---- target/arm/helper.c | 2 +- target/arm/machine.c | 3 +-- 5 files changed, 8 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c9996d2534..da841f8538 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1529,7 +1529,6 @@ enum arm_features { ARM_FEATURE_NEON, ARM_FEATURE_M, /* Microcontroller profile. */ ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ - ARM_FEATURE_THUMB2EE, ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ ARM_FEATURE_V4T, @@ -3123,6 +3122,11 @@ static inline bool aa32_feature_jazelle(ARMCPU *cpu) return FIELD_EX32(cpu->id_isar1, ID_ISAR1, JAZELLE) !=3D 0; } =20 +static inline bool aa32_feature_t32ee(ARMCPU *cpu) +{ + return FIELD_EX32(cpu->id_isar3, ID_ISAR3, T32EE) !=3D 0; +} + static inline bool aa32_feature_aes(ARMCPU *cpu) { return FIELD_EX32(cpu->id_isar5, ID_ISAR5, AES) !=3D 0; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 1ddb1fd102..01707ebb91 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -466,7 +466,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); - GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); + GET_FEATURE_ID(t32ee, ARM_HWCAP_ARM_THUMBEE); GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 41a1b27c61..abb1b6fe5c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1436,7 +1436,6 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr =3D 0x410fc080; @@ -1505,7 +1504,6 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); /* Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different @@ -1568,7 +1566,6 @@ static void cortex_a7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); @@ -1614,7 +1611,6 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); diff --git a/target/arm/helper.c b/target/arm/helper.c index 64b1564594..5af89f6d9d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5328,7 +5328,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_cp_reginfo); } - if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { + if (aa32_feature_t32ee(cpu)) { define_arm_cp_regs(cpu, t2ee_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { diff --git a/target/arm/machine.c b/target/arm/machine.c index ff4ec22bf7..d44e891533 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -301,9 +301,8 @@ static const VMStateDescription vmstate_m =3D { static bool thumb2ee_needed(void *opaque) { ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; =20 - return arm_feature(env, ARM_FEATURE_THUMB2EE); + return aa32_feature_t32ee(cpu); } =20 static const VMStateDescription vmstate_thumb2ee =3D { --=20 2.17.1