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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id l26-v6sm5395884pfg.161.2018.09.27.14.13.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 27 Sep 2018 14:13:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LP/+3WaKDve0fwiHpOFR2zYbrl7dNIkNEgKhsrE+Ecc=; b=aRQCZ7QrF44YYcYW9tMbkBU3s8wG/sUMk12XjWZOlMDdfijCr5a2SCTMVO/wkmUY6r +S5C3G5B0YXRhhz8YCmt+XASGFDS2y4t1q7JmRGa7SSCeeN2GtIU6Rp5ZyoG3BeLvfcF W/Vrwz76PoM9RQa0IxqZLcC7JI/Z6ThSBvVlg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LP/+3WaKDve0fwiHpOFR2zYbrl7dNIkNEgKhsrE+Ecc=; b=qzgtqSQkrkIfxTylcGSEAnDJbE/PLOjST2cHncLPdTU3H1ak+Os+fptyDQfFWD03Uh ybsnVmReEe8sXZp6RfyimVS/TTKyS/h2UdrjHLCsAk6awU4yFDUpaO46lWwItNdSNNoD r6+539UYtK8+jK/NPqYIQVKBhG7C1zniVrfyoyzXnVvcqBdrEQd80XQ6mjbUZoOaWro2 JI5+M57gntq3m/dEvVLyXqlreZJWWh3SHE8TeWJbA4hPsnb1kSat8740H3vy5VJyuMmv fFrkqCT96BYMWQcxG6yWJ5KVIFqetEF9W7bzzH7l3enfGFdzHipXqKE6TmRs3uWPvSFs IKaA== X-Gm-Message-State: ABuFfogflMdhjwSyPiAGs0SnwlesV8UtfFHi4dZxcqUYEJ9Z3v1ibVMj QwCAgAQiR8F6xNiYeXs9TrZrrQ8XTN4= X-Google-Smtp-Source: ACcGV60dIN58nzhmhV311Ftgv8sDx8OLz7ZlZTiGk9y/0fdzTD7tZxjerYwsZIkI53U7VO8WPAA1xw== X-Received: by 2002:a17:902:6b47:: with SMTP id g7-v6mr13144432plt.128.1538082806916; Thu, 27 Sep 2018 14:13:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2018 14:13:14 -0700 Message-Id: <20180927211322.16118-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180927211322.16118-1-richard.henderson@linaro.org> References: <20180927211322.16118-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42c Subject: [Qemu-devel] [PATCH v2 1/9] target/arm: Define fields of ISAR registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 80 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 65c0fa0a65..e1b9270b8c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1428,6 +1428,86 @@ FIELD(V7M_CSSELR, LEVEL, 1, 3) */ FIELD(V7M_CSSELR, INDEX, 0, 4) =20 +/* + * System register ID fields. + */ +FIELD(ID_ISAR0, SWAP, 0, 4) +FIELD(ID_ISAR0, BITCOUNT, 4, 4) +FIELD(ID_ISAR0, BITFIELD, 8, 4) +FIELD(ID_ISAR0, CMPBRANCH, 12, 4) +FIELD(ID_ISAR0, COPROC, 16, 4) +FIELD(ID_ISAR0, DEBUG, 20, 4) +FIELD(ID_ISAR0, DIVIDE, 24, 4) + +FIELD(ID_ISAR1, ENDIAN, 0, 4) +FIELD(ID_ISAR1, EXCEPT, 4, 4) +FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) +FIELD(ID_ISAR1, EXTEND, 12, 4) +FIELD(ID_ISAR1, IFTHEN, 16, 4) +FIELD(ID_ISAR1, IMMEDIATE, 20, 4) +FIELD(ID_ISAR1, INTERWORK, 24, 4) +FIELD(ID_ISAR1, JAZELLE, 28, 4) + +FIELD(ID_ISAR2, LOADSTORE, 0, 4) +FIELD(ID_ISAR2, MEMHINT, 4, 4) +FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) +FIELD(ID_ISAR2, MULT, 12, 4) +FIELD(ID_ISAR2, MULTS, 16, 4) +FIELD(ID_ISAR2, MULTU, 20, 4) +FIELD(ID_ISAR2, PSR_AR, 24, 4) +FIELD(ID_ISAR2, REVERSAL, 28, 4) + +FIELD(ID_ISAR3, SATURATE, 0, 4) +FIELD(ID_ISAR3, SIMD, 4, 4) +FIELD(ID_ISAR3, SVC, 8, 4) +FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) +FIELD(ID_ISAR3, TABBRANCH, 16, 4) +FIELD(ID_ISAR3, T32COPY, 20, 4) +FIELD(ID_ISAR3, TRUENOP, 24, 4) +FIELD(ID_ISAR3, T32EE, 28, 4) + +FIELD(ID_ISAR4, UNPRIV, 0, 4) +FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) +FIELD(ID_ISAR4, WRITEBACK, 8, 4) +FIELD(ID_ISAR4, SMC, 12, 4) +FIELD(ID_ISAR4, BARRIER, 16, 4) +FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) +FIELD(ID_ISAR4, PSR_M, 24, 4) +FIELD(ID_ISAR4, SWP_FRAC, 28, 4) + +FIELD(ID_ISAR5, SEVL, 0, 4) +FIELD(ID_ISAR5, AES, 4, 4) +FIELD(ID_ISAR5, SHA1, 8, 4) +FIELD(ID_ISAR5, SHA2, 12, 4) +FIELD(ID_ISAR5, CRC32, 16, 4) +FIELD(ID_ISAR5, RDM, 24, 4) +FIELD(ID_ISAR5, VCMA, 28, 4) + +FIELD(ID_ISAR6, JSCVT, 0, 4) +FIELD(ID_ISAR6, DP, 4, 4) +FIELD(ID_ISAR6, FHM, 8, 4) + +FIELD(ID_AA64ISAR0, AES, 4, 4) +FIELD(ID_AA64ISAR0, SHA1, 8, 4) +FIELD(ID_AA64ISAR0, SHA2, 12, 4) +FIELD(ID_AA64ISAR0, CRC32, 16, 4) +FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) +FIELD(ID_AA64ISAR0, RDM, 28, 4) +FIELD(ID_AA64ISAR0, SHA3, 32, 4) +FIELD(ID_AA64ISAR0, SM3, 36, 4) +FIELD(ID_AA64ISAR0, SM4, 40, 4) +FIELD(ID_AA64ISAR0, DP, 44, 4) +FIELD(ID_AA64ISAR0, FHM, 48, 4) + +FIELD(ID_AA64ISAR1, DPB, 0, 4) +FIELD(ID_AA64ISAR1, APA, 4, 4) +FIELD(ID_AA64ISAR1, API, 8, 4) +FIELD(ID_AA64ISAR1, JSCVT, 12, 4) +FIELD(ID_AA64ISAR1, FCMA, 16, 4) +FIELD(ID_AA64ISAR1, LRCPC, 20, 4) +FIELD(ID_AA64ISAR1, GPA, 24, 4) +FIELD(ID_AA64ISAR1, GPI, 28, 4) + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=3D R_V7M_CSSELR_INDE= X_MASK); =20 /* If adding a feature bit which corresponds to a Linux ELF --=20 2.17.1 From nobody Wed Nov 5 21:43:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538084025575737.1352229515215; Thu, 27 Sep 2018 14:33:45 -0700 (PDT) Received: from localhost ([::1]:39528 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g5dup-0007bt-GS for importer@patchew.org; Thu, 27 Sep 2018 17:33:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54149) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g5dpJ-0003xe-7v for qemu-devel@nongnu.org; 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id l26-v6sm5395884pfg.161.2018.09.27.14.13.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 27 Sep 2018 14:13:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0A2lNxWuQlhf1DsU/V+xrEFaPRw8w2RxVv1sDcdz2gc=; b=OFVA3vQaD5HydmMwmMm1fAYwkXkzvdDVe5Z5+UHKG0MGU7BNwJtkdPHd11GbNDf/Tj uZ7dvvJAiy/muUtmAXANimEZo7scA/fuOjKXEtIOSg4QPe2GY67XenaUbUS2+K7qVh/L KN5G21q7F9QHhiyCDCCsO6BAbMgSIcmGXUhsI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0A2lNxWuQlhf1DsU/V+xrEFaPRw8w2RxVv1sDcdz2gc=; b=JCrGOXs2TLHXrk2XMXK5dR5bDWbgaQrLz5327kgAZXn1NTVS5vtRJS3PUt6MEGidNP R12mod+Fx9KbLhjrA8Xc6WnhGBFMOSydT9RwszHP4GA9YHEdeiMS/3XUp7sAOGAddJU7 EBPRiWNNjkgwsCn1jZJN3MZBVb2WKkqDhw9JI7xen9e5U79Qbjft4t5eoyjXoWD0Ji42 CP6f14a14h3vNx/cbDaegdEU91ZYpTerBJzcnmigalC1RjCWx2kpAlnVjRu2S1iRZS4r +uLvJXKvG5Wk2ewj+ihpzkKDbBthEHIiVdfmHlFD1zhrTDeWtCQSJrtl3Uvg79ihse2k dx7w== X-Gm-Message-State: ABuFfoggIQ9y9r13apSZLUr/Q0959KUTofgfuuBetLWgRIxpXha7alwS Lc53YKcj+gCbCNdfN/6lxsxPqEqTi8A= X-Google-Smtp-Source: ACcGV62oX+fSDXwpJbMdUryxoljaluAbJaQMdvj7dKDfPtvBn0KUzBas9MqsKXJLh/Qajp1v+am/Ww== X-Received: by 2002:a62:18a:: with SMTP id 132-v6mr13454482pfb.207.1538082808367; Thu, 27 Sep 2018 14:13:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2018 14:13:15 -0700 Message-Id: <20180927211322.16118-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180927211322.16118-1-richard.henderson@linaro.org> References: <20180927211322.16118-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v2 2/9] target/arm: Convert v8 extensions from feature bits to isar tests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Most of the v8 extensions are self-contained within the ISAR registers and are not implied by other feature bits, which makes them the easiest to convert. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 123 +++++++++++++++++++++++++++++++++---- target/arm/translate-a64.h | 20 ++++++ target/arm/translate.h | 16 +++++ linux-user/elfload.c | 46 ++++++++------ target/arm/cpu.c | 18 +++--- target/arm/cpu64.c | 41 +++++++------ target/arm/translate-a64.c | 100 +++++++++++++++--------------- target/arm/translate.c | 35 +++++------ 8 files changed, 272 insertions(+), 127 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e1b9270b8c..1e3c4650ce 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1550,30 +1550,18 @@ enum arm_features { ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ ARM_FEATURE_V8, ARM_FEATURE_AARCH64, /* supports 64 bit mode */ - ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */ ARM_FEATURE_CBAR, /* has cp15 CBAR */ ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */ ARM_FEATURE_EL2, /* has EL2 Virtualization support */ ARM_FEATURE_EL3, /* has EL3 Secure monitor support */ - ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */ - ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensio= ns */ - ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions= */ ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ ARM_FEATURE_PMU, /* has PMU support */ ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ ARM_FEATURE_SVE, /* has Scalable Vector Extension */ - ARM_FEATURE_V8_SHA512, /* implements SHA512 part of v8 Crypto Extensio= ns */ - ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ - ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */ - ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ - ARM_FEATURE_V8_ATOMICS, /* ARMv8.1-Atomics feature */ - ARM_FEATURE_V8_RDM, /* implements v8.1 simd round multiply */ - ARM_FEATURE_V8_DOTPROD, /* implements v8.2 simd dot product */ ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ - ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */ ARM_FEATURE_M_MAIN, /* M profile Main Extension */ }; =20 @@ -3120,4 +3108,115 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *= env, unsigned regno) /* Shared between translate-sve.c and sve_helper.c. */ extern const uint64_t pred_esz_masks[4]; =20 +/* + * 32-bit feature tests via id registers. + */ +static inline bool aa32_feature_aes(ARMCPU *cpu) +{ + return FIELD_EX32(cpu->id_isar5, ID_ISAR5, AES) !=3D 0; +} + +static inline bool aa32_feature_pmull(ARMCPU *cpu) +{ + return FIELD_EX32(cpu->id_isar5, ID_ISAR5, AES) > 1; +} + +static inline bool aa32_feature_sha1(ARMCPU *cpu) +{ + return FIELD_EX32(cpu->id_isar5, ID_ISAR5, SHA1) !=3D 0; +} + +static inline bool aa32_feature_sha2(ARMCPU *cpu) +{ + return FIELD_EX32(cpu->id_isar5, ID_ISAR5, SHA2) !=3D 0; +} + +static inline bool aa32_feature_crc32(ARMCPU *cpu) +{ + return FIELD_EX32(cpu->id_isar5, ID_ISAR5, CRC32) !=3D 0; +} + +static inline bool aa32_feature_rdm(ARMCPU *cpu) +{ + return FIELD_EX32(cpu->id_isar5, ID_ISAR5, RDM) !=3D 0; +} + +static inline bool aa32_feature_vcma(ARMCPU *cpu) +{ + return FIELD_EX32(cpu->id_isar5, ID_ISAR5, VCMA) !=3D 0; +} + +static inline bool aa32_feature_dp(ARMCPU *cpu) +{ + return FIELD_EX32(cpu->id_isar6, ID_ISAR6, DP) !=3D 0; +} + +/* + * 64-bit feature tests via id registers. + */ +static inline bool aa64_feature_aes(ARMCPU *cpu) +{ + return FIELD_EX64(cpu->id_aa64isar0, ID_AA64ISAR0, AES) !=3D 0; +} + +static inline bool aa64_feature_pmull(ARMCPU *cpu) +{ + return FIELD_EX64(cpu->id_aa64isar0, ID_AA64ISAR0, AES) > 1; +} + +static inline bool aa64_feature_sha1(ARMCPU *cpu) +{ + return FIELD_EX64(cpu->id_aa64isar0, ID_AA64ISAR0, SHA1) !=3D 0; +} + +static inline bool aa64_feature_sha256(ARMCPU *cpu) +{ + return FIELD_EX64(cpu->id_aa64isar0, ID_AA64ISAR0, SHA2) !=3D 0; +} + +static inline bool aa64_feature_sha512(ARMCPU *cpu) +{ + return FIELD_EX64(cpu->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; +} + +static inline bool aa64_feature_crc32(ARMCPU *cpu) +{ + return FIELD_EX64(cpu->id_aa64isar0, ID_AA64ISAR0, CRC32) !=3D 0; +} + +static inline bool aa64_feature_atomics(ARMCPU *cpu) +{ + return FIELD_EX64(cpu->id_aa64isar0, ID_AA64ISAR0, ATOMIC) !=3D 0; +} + +static inline bool aa64_feature_rdm(ARMCPU *cpu) +{ + return FIELD_EX64(cpu->id_aa64isar0, ID_AA64ISAR0, RDM) !=3D 0; +} + +static inline bool aa64_feature_sha3(ARMCPU *cpu) +{ + return FIELD_EX64(cpu->id_aa64isar0, ID_AA64ISAR0, SHA3) !=3D 0; +} + +static inline bool aa64_feature_sm3(ARMCPU *cpu) +{ + return FIELD_EX64(cpu->id_aa64isar0, ID_AA64ISAR0, SM3) !=3D 0; +} + +static inline bool aa64_feature_sm4(ARMCPU *cpu) +{ + return FIELD_EX64(cpu->id_aa64isar0, ID_AA64ISAR0, SM4) !=3D 0; +} + +static inline bool aa64_feature_dp(ARMCPU *cpu) +{ + return FIELD_EX64(cpu->id_aa64isar0, ID_AA64ISAR0, DP) !=3D 0; +} + +static inline bool aa64_feature_fcma(ARMCPU *cpu) +{ + return FIELD_EX64(cpu->id_aa64isar1, ID_AA64ISAR1, FCMA) !=3D 0; +} + #endif diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 63d958cf50..b4ef9eb024 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -123,4 +123,24 @@ typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t,= int64_t, typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); =20 +#define FORWARD_FEATURE(NAME) \ + static inline bool aa64_dc_feature_##NAME(DisasContext *dc) \ + { return aa64_feature_##NAME(dc->cpu); } + +FORWARD_FEATURE(aes) +FORWARD_FEATURE(pmull) +FORWARD_FEATURE(sha1) +FORWARD_FEATURE(sha256) +FORWARD_FEATURE(sha512) +FORWARD_FEATURE(crc32) +FORWARD_FEATURE(atomics) +FORWARD_FEATURE(rdm) +FORWARD_FEATURE(sha3) +FORWARD_FEATURE(sm3) +FORWARD_FEATURE(sm4) +FORWARD_FEATURE(dp) +FORWARD_FEATURE(fcma) + +#undef FORWARD_FEATURE + #endif /* TARGET_ARM_TRANSLATE_A64_H */ diff --git a/target/arm/translate.h b/target/arm/translate.h index 45f04244be..baacfd7e6b 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -7,6 +7,7 @@ /* internal defines */ typedef struct DisasContext { DisasContextBase base; + ARMCPU *cpu; /* for access to the id_* registers */ =20 target_ulong pc; target_ulong page_start; @@ -189,4 +190,19 @@ static inline TCGv_i32 get_ahp_flag(void) return ret; } =20 +#define FORWARD_FEATURE(NAME) \ + static inline bool aa32_dc_feature_##NAME(DisasContext *dc) \ + { return aa32_feature_##NAME(dc->cpu); } + +FORWARD_FEATURE(aes) +FORWARD_FEATURE(pmull) +FORWARD_FEATURE(sha1) +FORWARD_FEATURE(sha2) +FORWARD_FEATURE(crc32) +FORWARD_FEATURE(rdm) +FORWARD_FEATURE(vcma) +FORWARD_FEATURE(dp) + +#undef FORWARD_FEATURE + #endif /* TARGET_ARM_TRANSLATE_H */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index e97c4cde49..408bf67206 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -458,6 +458,10 @@ static uint32_t get_elf_hwcap(void) /* probe for the extra features */ #define GET_FEATURE(feat, hwcap) \ do { if (arm_feature(&cpu->env, feat)) { hwcaps |=3D hwcap; } } while = (0) + +#define GET_FEATURE_ID(feat, hwcap) \ + do { if (aa32_feature_##feat(cpu)) { hwcaps |=3D hwcap; } } while (0) + /* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */ GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); @@ -485,15 +489,16 @@ static uint32_t get_elf_hwcap2(void) ARMCPU *cpu =3D ARM_CPU(thread_cpu); uint32_t hwcaps =3D 0; =20 - GET_FEATURE(ARM_FEATURE_V8_AES, ARM_HWCAP2_ARM_AES); - GET_FEATURE(ARM_FEATURE_V8_PMULL, ARM_HWCAP2_ARM_PMULL); - GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP2_ARM_SHA1); - GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP2_ARM_SHA2); - GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP2_ARM_CRC32); + GET_FEATURE_ID(aes, ARM_HWCAP2_ARM_AES); + GET_FEATURE_ID(pmull, ARM_HWCAP2_ARM_PMULL); + GET_FEATURE_ID(sha1, ARM_HWCAP2_ARM_SHA1); + GET_FEATURE_ID(sha2, ARM_HWCAP2_ARM_SHA2); + GET_FEATURE_ID(crc32, ARM_HWCAP2_ARM_CRC32); return hwcaps; } =20 #undef GET_FEATURE +#undef GET_FEATURE_ID =20 #else /* 64 bit ARM definitions */ @@ -570,23 +575,28 @@ static uint32_t get_elf_hwcap(void) /* probe for the extra features */ #define GET_FEATURE(feat, hwcap) \ do { if (arm_feature(&cpu->env, feat)) { hwcaps |=3D hwcap; } } while = (0) - GET_FEATURE(ARM_FEATURE_V8_AES, ARM_HWCAP_A64_AES); - GET_FEATURE(ARM_FEATURE_V8_PMULL, ARM_HWCAP_A64_PMULL); - GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1); - GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2); - GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32); - GET_FEATURE(ARM_FEATURE_V8_SHA3, ARM_HWCAP_A64_SHA3); - GET_FEATURE(ARM_FEATURE_V8_SM3, ARM_HWCAP_A64_SM3); - GET_FEATURE(ARM_FEATURE_V8_SM4, ARM_HWCAP_A64_SM4); - GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512); +#define GET_FEATURE_ID(feat, hwcap) \ + do { if (aa64_feature_##feat(cpu)) { hwcaps |=3D hwcap; } } while (0) + + GET_FEATURE_ID(aes, ARM_HWCAP_A64_AES); + GET_FEATURE_ID(pmull, ARM_HWCAP_A64_PMULL); + GET_FEATURE_ID(sha1, ARM_HWCAP_A64_SHA1); + GET_FEATURE_ID(sha256, ARM_HWCAP_A64_SHA2); + GET_FEATURE_ID(sha512, ARM_HWCAP_A64_SHA512); + GET_FEATURE_ID(crc32, ARM_HWCAP_A64_CRC32); + GET_FEATURE_ID(sha3, ARM_HWCAP_A64_SHA3); + GET_FEATURE_ID(sm3, ARM_HWCAP_A64_SM3); + GET_FEATURE_ID(sm4, ARM_HWCAP_A64_SM4); GET_FEATURE(ARM_FEATURE_V8_FP16, ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP); - GET_FEATURE(ARM_FEATURE_V8_ATOMICS, ARM_HWCAP_A64_ATOMICS); - GET_FEATURE(ARM_FEATURE_V8_RDM, ARM_HWCAP_A64_ASIMDRDM); - GET_FEATURE(ARM_FEATURE_V8_DOTPROD, ARM_HWCAP_A64_ASIMDDP); - GET_FEATURE(ARM_FEATURE_V8_FCMA, ARM_HWCAP_A64_FCMA); + GET_FEATURE_ID(atomics, ARM_HWCAP_A64_ATOMICS); + GET_FEATURE_ID(rdm, ARM_HWCAP_A64_ASIMDRDM); + GET_FEATURE_ID(dp, ARM_HWCAP_A64_ASIMDDP); + GET_FEATURE_ID(fcma, ARM_HWCAP_A64_FCMA); GET_FEATURE(ARM_FEATURE_SVE, ARM_HWCAP_A64_SVE); + #undef GET_FEATURE +#undef GET_FEATURE_ID =20 return hwcaps; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b5e61cc177..17c9c43f41 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1827,17 +1827,17 @@ static void arm_max_initfn(Object *obj) cortex_a15_initfn(obj); #ifdef CONFIG_USER_ONLY /* We don't set these in system emulation mode for the moment, - * since we don't correctly set the ID registers to advertise them, + * since we don't correctly set (all of) the ID registers to + * advertise them. */ set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_V8_AES); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); - set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); - set_feature(&cpu->env, ARM_FEATURE_CRC); - set_feature(&cpu->env, ARM_FEATURE_V8_RDM); - set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD); - set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); + FIELD_DP32(cpu->id_isar5, ID_ISAR5, AES, 2); /* AES + PMULL */ + FIELD_DP32(cpu->id_isar5, ID_ISAR5, SHA1, 1); + FIELD_DP32(cpu->id_isar5, ID_ISAR5, SHA2, 1); + FIELD_DP32(cpu->id_isar5, ID_ISAR5, CRC32, 1); + FIELD_DP32(cpu->id_isar5, ID_ISAR5, RDM, 1); + FIELD_DP32(cpu->id_isar5, ID_ISAR5, VCMA, 1); + FIELD_DP32(cpu->id_isar6, ID_ISAR6, DP, 1); #endif } } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 800bff780e..f9830b67f3 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -109,11 +109,6 @@ static void aarch64_a57_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_AARCH64); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_V8_AES); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); - set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); - set_feature(&cpu->env, ARM_FEATURE_CRC); set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); @@ -170,11 +165,6 @@ static void aarch64_a53_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_AARCH64); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_V8_AES); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); - set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); - set_feature(&cpu->env, ARM_FEATURE_CRC); set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); @@ -254,6 +244,29 @@ static void aarch64_max_initfn(Object *obj) kvm_arm_set_cpu_features_from_host(cpu); } else { aarch64_a57_initfn(obj); + + FIELD_DP64(cpu->id_aa64isar0, ID_AA64ISAR0, AES, 2); /* AES + PMUL= L */ + FIELD_DP64(cpu->id_aa64isar0, ID_AA64ISAR0, SHA1, 1); + FIELD_DP64(cpu->id_aa64isar0, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ + FIELD_DP64(cpu->id_aa64isar0, ID_AA64ISAR0, CRC32, 1); + FIELD_DP64(cpu->id_aa64isar0, ID_AA64ISAR0, ATOMIC, 2); + FIELD_DP64(cpu->id_aa64isar0, ID_AA64ISAR0, RDM, 1); + FIELD_DP64(cpu->id_aa64isar0, ID_AA64ISAR0, SHA3, 1); + FIELD_DP64(cpu->id_aa64isar0, ID_AA64ISAR0, SM3, 1); + FIELD_DP64(cpu->id_aa64isar0, ID_AA64ISAR0, SM4, 1); + FIELD_DP64(cpu->id_aa64isar0, ID_AA64ISAR0, DP, 1); + + FIELD_DP64(cpu->id_aa64isar1, ID_AA64ISAR1, FCMA, 1); + + /* Replicate the same data to the 32-bit id registers. */ + FIELD_DP32(cpu->id_isar5, ID_ISAR5, AES, 2); /* AES + PMULL */ + FIELD_DP32(cpu->id_isar5, ID_ISAR5, SHA1, 1); + FIELD_DP32(cpu->id_isar5, ID_ISAR5, SHA2, 1); + FIELD_DP32(cpu->id_isar5, ID_ISAR5, CRC32, 1); + FIELD_DP32(cpu->id_isar5, ID_ISAR5, RDM, 1); + FIELD_DP32(cpu->id_isar5, ID_ISAR5, VCMA, 1); + FIELD_DP32(cpu->id_isar6, ID_ISAR6, DP, 1); + #ifdef CONFIG_USER_ONLY /* We don't set these in system emulation mode for the moment, * since we don't correctly set the ID registers to advertise them, @@ -261,15 +274,7 @@ static void aarch64_max_initfn(Object *obj) * whereas the architecture requires them to be present in both if * present in either. */ - set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); - set_feature(&cpu->env, ARM_FEATURE_V8_SM3); - set_feature(&cpu->env, ARM_FEATURE_V8_SM4); - set_feature(&cpu->env, ARM_FEATURE_V8_ATOMICS); - set_feature(&cpu->env, ARM_FEATURE_V8_RDM); - set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD); set_feature(&cpu->env, ARM_FEATURE_V8_FP16); - set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); set_feature(&cpu->env, ARM_FEATURE_SVE); /* For usermode -cpu max we can use a larger and more efficient DCZ * blocksize since we don't have to follow what the hardware does. diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8ca3876707..40575485aa 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2318,7 +2318,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) } if (rt2 =3D=3D 31 && ((rt | rs) & 1) =3D=3D 0 - && arm_dc_feature(s, ARM_FEATURE_V8_ATOMICS)) { + && aa64_dc_feature_atomics(s)) { /* CASP / CASPL */ gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); return; @@ -2340,7 +2340,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) } if (rt2 =3D=3D 31 && ((rt | rs) & 1) =3D=3D 0 - && arm_dc_feature(s, ARM_FEATURE_V8_ATOMICS)) { + && aa64_dc_feature_atomics(s)) { /* CASPA / CASPAL */ gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); return; @@ -2351,7 +2351,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) case 0xb: /* CASL */ case 0xe: /* CASA */ case 0xf: /* CASAL */ - if (rt2 =3D=3D 31 && arm_dc_feature(s, ARM_FEATURE_V8_ATOMICS)) { + if (rt2 =3D=3D 31 && aa64_dc_feature_atomics(s)) { gen_compare_and_swap(s, rs, rt, rn, size); return; } @@ -2890,11 +2890,10 @@ static void disas_ldst_atomic(DisasContext *s, uint= 32_t insn, int rs =3D extract32(insn, 16, 5); int rn =3D extract32(insn, 5, 5); int o3_opc =3D extract32(insn, 12, 4); - int feature =3D ARM_FEATURE_V8_ATOMICS; TCGv_i64 tcg_rn, tcg_rs; AtomicThreeOpFn *fn; =20 - if (is_vector) { + if (is_vector || !aa64_dc_feature_atomics(s)) { unallocated_encoding(s); return; } @@ -2930,10 +2929,6 @@ static void disas_ldst_atomic(DisasContext *s, uint3= 2_t insn, unallocated_encoding(s); return; } - if (!arm_dc_feature(s, feature)) { - unallocated_encoding(s); - return; - } =20 if (rn =3D=3D 31) { gen_check_sp_alignment(s); @@ -4564,7 +4559,7 @@ static void handle_crc32(DisasContext *s, TCGv_i64 tcg_acc, tcg_val; TCGv_i32 tcg_bytes; =20 - if (!arm_dc_feature(s, ARM_FEATURE_CRC) + if (!aa64_dc_feature_crc32(s) || (sf =3D=3D 1 && sz !=3D 3) || (sf =3D=3D 0 && sz =3D=3D 3)) { unallocated_encoding(s); @@ -8608,7 +8603,7 @@ static void disas_simd_scalar_three_reg_same_extra(Di= sasContext *s, bool u =3D extract32(insn, 29, 1); TCGv_i32 ele1, ele2, ele3; TCGv_i64 res; - int feature; + bool feature; =20 switch (u * 16 + opcode) { case 0x10: /* SQRDMLAH (vector) */ @@ -8617,13 +8612,13 @@ static void disas_simd_scalar_three_reg_same_extra(= DisasContext *s, unallocated_encoding(s); return; } - feature =3D ARM_FEATURE_V8_RDM; + feature =3D aa64_dc_feature_rdm(s); break; default: unallocated_encoding(s); return; } - if (!arm_dc_feature(s, feature)) { + if (!feature) { unallocated_encoding(s); return; } @@ -10352,7 +10347,7 @@ static void disas_simd_three_reg_diff(DisasContext = *s, uint32_t insn) return; } if (size =3D=3D 3) { - if (!arm_dc_feature(s, ARM_FEATURE_V8_PMULL)) { + if (!aa64_dc_feature_pmull(s)) { unallocated_encoding(s); return; } @@ -11404,7 +11399,8 @@ static void disas_simd_three_reg_same_extra(DisasCo= ntext *s, uint32_t insn) int size =3D extract32(insn, 22, 2); bool u =3D extract32(insn, 29, 1); bool is_q =3D extract32(insn, 30, 1); - int feature, rot; + bool feature; + int rot; =20 switch (u * 16 + opcode) { case 0x10: /* SQRDMLAH (vector) */ @@ -11413,7 +11409,7 @@ static void disas_simd_three_reg_same_extra(DisasCo= ntext *s, uint32_t insn) unallocated_encoding(s); return; } - feature =3D ARM_FEATURE_V8_RDM; + feature =3D aa64_dc_feature_rdm(s); break; case 0x02: /* SDOT (vector) */ case 0x12: /* UDOT (vector) */ @@ -11421,7 +11417,7 @@ static void disas_simd_three_reg_same_extra(DisasCo= ntext *s, uint32_t insn) unallocated_encoding(s); return; } - feature =3D ARM_FEATURE_V8_DOTPROD; + feature =3D aa64_dc_feature_dp(s); break; case 0x18: /* FCMLA, #0 */ case 0x19: /* FCMLA, #90 */ @@ -11435,13 +11431,13 @@ static void disas_simd_three_reg_same_extra(Disas= Context *s, uint32_t insn) unallocated_encoding(s); return; } - feature =3D ARM_FEATURE_V8_FCMA; + feature =3D aa64_dc_feature_fcma(s); break; default: unallocated_encoding(s); return; } - if (!arm_dc_feature(s, feature)) { + if (!feature) { unallocated_encoding(s); return; } @@ -12655,14 +12651,14 @@ static void disas_simd_indexed(DisasContext *s, u= int32_t insn) break; case 0x1d: /* SQRDMLAH */ case 0x1f: /* SQRDMLSH */ - if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { + if (!aa64_dc_feature_rdm(s)) { unallocated_encoding(s); return; } break; case 0x0e: /* SDOT */ case 0x1e: /* UDOT */ - if (size !=3D MO_32 || !arm_dc_feature(s, ARM_FEATURE_V8_DOTPROD))= { + if (size !=3D MO_32 || !aa64_dc_feature_dp(s)) { unallocated_encoding(s); return; } @@ -12671,7 +12667,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) case 0x13: /* FCMLA #90 */ case 0x15: /* FCMLA #180 */ case 0x17: /* FCMLA #270 */ - if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) { + if (!aa64_dc_feature_fcma(s)) { unallocated_encoding(s); return; } @@ -13198,8 +13194,7 @@ static void disas_crypto_aes(DisasContext *s, uint3= 2_t insn) TCGv_i32 tcg_decrypt; CryptoThreeOpIntFn *genfn; =20 - if (!arm_dc_feature(s, ARM_FEATURE_V8_AES) - || size !=3D 0) { + if (!aa64_dc_feature_aes(s) || size !=3D 0) { unallocated_encoding(s); return; } @@ -13256,7 +13251,7 @@ static void disas_crypto_three_reg_sha(DisasContext= *s, uint32_t insn) int rd =3D extract32(insn, 0, 5); CryptoThreeOpFn *genfn; TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; - int feature =3D ARM_FEATURE_V8_SHA256; + bool feature; =20 if (size !=3D 0) { unallocated_encoding(s); @@ -13269,23 +13264,26 @@ static void disas_crypto_three_reg_sha(DisasConte= xt *s, uint32_t insn) case 2: /* SHA1M */ case 3: /* SHA1SU0 */ genfn =3D NULL; - feature =3D ARM_FEATURE_V8_SHA1; + feature =3D aa64_dc_feature_sha1(s); break; case 4: /* SHA256H */ genfn =3D gen_helper_crypto_sha256h; + feature =3D aa64_dc_feature_sha256(s); break; case 5: /* SHA256H2 */ genfn =3D gen_helper_crypto_sha256h2; + feature =3D aa64_dc_feature_sha256(s); break; case 6: /* SHA256SU1 */ genfn =3D gen_helper_crypto_sha256su1; + feature =3D aa64_dc_feature_sha256(s); break; default: unallocated_encoding(s); return; } =20 - if (!arm_dc_feature(s, feature)) { + if (!feature) { unallocated_encoding(s); return; } @@ -13326,7 +13324,7 @@ static void disas_crypto_two_reg_sha(DisasContext *= s, uint32_t insn) int rn =3D extract32(insn, 5, 5); int rd =3D extract32(insn, 0, 5); CryptoTwoOpFn *genfn; - int feature; + bool feature; TCGv_ptr tcg_rd_ptr, tcg_rn_ptr; =20 if (size !=3D 0) { @@ -13336,15 +13334,15 @@ static void disas_crypto_two_reg_sha(DisasContext= *s, uint32_t insn) =20 switch (opcode) { case 0: /* SHA1H */ - feature =3D ARM_FEATURE_V8_SHA1; + feature =3D aa64_dc_feature_sha1(s); genfn =3D gen_helper_crypto_sha1h; break; case 1: /* SHA1SU1 */ - feature =3D ARM_FEATURE_V8_SHA1; + feature =3D aa64_dc_feature_sha1(s); genfn =3D gen_helper_crypto_sha1su1; break; case 2: /* SHA256SU0 */ - feature =3D ARM_FEATURE_V8_SHA256; + feature =3D aa64_dc_feature_sha256(s); genfn =3D gen_helper_crypto_sha256su0; break; default: @@ -13352,7 +13350,7 @@ static void disas_crypto_two_reg_sha(DisasContext *= s, uint32_t insn) return; } =20 - if (!arm_dc_feature(s, feature)) { + if (!feature) { unallocated_encoding(s); return; } @@ -13383,40 +13381,40 @@ static void disas_crypto_three_reg_sha512(DisasCo= ntext *s, uint32_t insn) int rm =3D extract32(insn, 16, 5); int rn =3D extract32(insn, 5, 5); int rd =3D extract32(insn, 0, 5); - int feature; + bool feature; CryptoThreeOpFn *genfn; =20 if (o =3D=3D 0) { switch (opcode) { case 0: /* SHA512H */ - feature =3D ARM_FEATURE_V8_SHA512; + feature =3D aa64_dc_feature_sha512(s); genfn =3D gen_helper_crypto_sha512h; break; case 1: /* SHA512H2 */ - feature =3D ARM_FEATURE_V8_SHA512; + feature =3D aa64_dc_feature_sha512(s); genfn =3D gen_helper_crypto_sha512h2; break; case 2: /* SHA512SU1 */ - feature =3D ARM_FEATURE_V8_SHA512; + feature =3D aa64_dc_feature_sha512(s); genfn =3D gen_helper_crypto_sha512su1; break; case 3: /* RAX1 */ - feature =3D ARM_FEATURE_V8_SHA3; + feature =3D aa64_dc_feature_sha3(s); genfn =3D NULL; break; } } else { switch (opcode) { case 0: /* SM3PARTW1 */ - feature =3D ARM_FEATURE_V8_SM3; + feature =3D aa64_dc_feature_sm3(s); genfn =3D gen_helper_crypto_sm3partw1; break; case 1: /* SM3PARTW2 */ - feature =3D ARM_FEATURE_V8_SM3; + feature =3D aa64_dc_feature_sm3(s); genfn =3D gen_helper_crypto_sm3partw2; break; case 2: /* SM4EKEY */ - feature =3D ARM_FEATURE_V8_SM4; + feature =3D aa64_dc_feature_sm4(s); genfn =3D gen_helper_crypto_sm4ekey; break; default: @@ -13425,7 +13423,7 @@ static void disas_crypto_three_reg_sha512(DisasCont= ext *s, uint32_t insn) } } =20 - if (!arm_dc_feature(s, feature)) { + if (!feature) { unallocated_encoding(s); return; } @@ -13484,16 +13482,16 @@ static void disas_crypto_two_reg_sha512(DisasCont= ext *s, uint32_t insn) int rn =3D extract32(insn, 5, 5); int rd =3D extract32(insn, 0, 5); TCGv_ptr tcg_rd_ptr, tcg_rn_ptr; - int feature; + bool feature; CryptoTwoOpFn *genfn; =20 switch (opcode) { case 0: /* SHA512SU0 */ - feature =3D ARM_FEATURE_V8_SHA512; + feature =3D aa64_dc_feature_sha512(s); genfn =3D gen_helper_crypto_sha512su0; break; case 1: /* SM4E */ - feature =3D ARM_FEATURE_V8_SM4; + feature =3D aa64_dc_feature_sm4(s); genfn =3D gen_helper_crypto_sm4e; break; default: @@ -13501,7 +13499,7 @@ static void disas_crypto_two_reg_sha512(DisasContex= t *s, uint32_t insn) return; } =20 - if (!arm_dc_feature(s, feature)) { + if (!feature) { unallocated_encoding(s); return; } @@ -13532,22 +13530,22 @@ static void disas_crypto_four_reg(DisasContext *s= , uint32_t insn) int ra =3D extract32(insn, 10, 5); int rn =3D extract32(insn, 5, 5); int rd =3D extract32(insn, 0, 5); - int feature; + bool feature; =20 switch (op0) { case 0: /* EOR3 */ case 1: /* BCAX */ - feature =3D ARM_FEATURE_V8_SHA3; + feature =3D aa64_dc_feature_sha3(s); break; case 2: /* SM3SS1 */ - feature =3D ARM_FEATURE_V8_SM3; + feature =3D aa64_dc_feature_sm3(s); break; default: unallocated_encoding(s); return; } =20 - if (!arm_dc_feature(s, feature)) { + if (!feature) { unallocated_encoding(s); return; } @@ -13634,7 +13632,7 @@ static void disas_crypto_xar(DisasContext *s, uint3= 2_t insn) TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; int pass; =20 - if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA3)) { + if (!aa64_dc_feature_sha3(s)) { unallocated_encoding(s); return; } @@ -13680,7 +13678,7 @@ static void disas_crypto_three_reg_imm2(DisasContex= t *s, uint32_t insn) TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; TCGv_i32 tcg_imm2, tcg_opcode; =20 - if (!arm_dc_feature(s, ARM_FEATURE_V8_SM3)) { + if (!aa64_dc_feature_sm3(s)) { unallocated_encoding(s); return; } diff --git a/target/arm/translate.c b/target/arm/translate.c index c6a5d2ac44..06d61b1e0d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5660,7 +5660,7 @@ static const uint8_t neon_2rm_sizes[] =3D { static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn, int q, int rd, int rn, int rm) { - if (arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { + if (aa32_dc_feature_rdm(s)) { int opr_sz =3D (1 + q) * 8; tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), vfp_reg_offset(1, rn), @@ -5734,7 +5734,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) return 1; } if (!u) { /* SHA-1 */ - if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA1)) { + if (!aa32_dc_feature_sha1(s)) { return 1; } ptr1 =3D vfp_reg_ptr(true, rd); @@ -5744,7 +5744,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) gen_helper_crypto_sha1_3reg(ptr1, ptr2, ptr3, tmp4); tcg_temp_free_i32(tmp4); } else { /* SHA-256 */ - if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA256) || size =3D= =3D 3) { + if (!aa32_dc_feature_sha2(s) || size =3D=3D 3) { return 1; } ptr1 =3D vfp_reg_ptr(true, rd); @@ -6739,7 +6739,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) if (op =3D=3D 14 && size =3D=3D 2) { TCGv_i64 tcg_rn, tcg_rm, tcg_rd; =20 - if (!arm_dc_feature(s, ARM_FEATURE_V8_PMULL)) { + if (!aa32_dc_feature_pmull(s)) { return 1; } tcg_rn =3D tcg_temp_new_i64(); @@ -7056,7 +7056,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) { NeonGenThreeOpEnvFn *fn; =20 - if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { + if (!aa32_dc_feature_rdm(s)) { return 1; } if (u && ((rd | rn) & 1)) { @@ -7330,8 +7330,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) break; } case NEON_2RM_AESE: case NEON_2RM_AESMC: - if (!arm_dc_feature(s, ARM_FEATURE_V8_AES) - || ((rm | rd) & 1)) { + if (!aa32_dc_feature_aes(s) || ((rm | rd) & 1)) { return 1; } ptr1 =3D vfp_reg_ptr(true, rd); @@ -7352,8 +7351,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) tcg_temp_free_i32(tmp3); break; case NEON_2RM_SHA1H: - if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA1) - || ((rm | rd) & 1)) { + if (!aa32_dc_feature_sha1(s) || ((rm | rd) & 1)) { return 1; } ptr1 =3D vfp_reg_ptr(true, rd); @@ -7370,10 +7368,10 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) } /* bit 6 (q): set -> SHA256SU0, cleared -> SHA1SU1 */ if (q) { - if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA256)) { + if (!aa32_dc_feature_sha2(s)) { return 1; } - } else if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA1)) { + } else if (!aa32_dc_feature_sha1(s)) { return 1; } ptr1 =3D vfp_reg_ptr(true, rd); @@ -7784,7 +7782,7 @@ static int disas_neon_insn_3same_ext(DisasContext *s,= uint32_t insn) /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */ int size =3D extract32(insn, 20, 1); data =3D extract32(insn, 23, 2); /* rot */ - if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) + if (!aa32_dc_feature_vcma(s) || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { return 1; } @@ -7793,7 +7791,7 @@ static int disas_neon_insn_3same_ext(DisasContext *s,= uint32_t insn) /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */ int size =3D extract32(insn, 20, 1); data =3D extract32(insn, 24, 1); /* rot */ - if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA) + if (!aa32_dc_feature_vcma(s) || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { return 1; } @@ -7801,7 +7799,7 @@ static int disas_neon_insn_3same_ext(DisasContext *s,= uint32_t insn) } else if ((insn & 0xfeb00f00) =3D=3D 0xfc200d00) { /* V[US]DOT -- 1111 1100 0.10 .... .... 1101 .Q.U .... */ bool u =3D extract32(insn, 4, 1); - if (!arm_dc_feature(s, ARM_FEATURE_V8_DOTPROD)) { + if (!aa32_dc_feature_dp(s)) { return 1; } fn_gvec =3D u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b; @@ -7863,7 +7861,7 @@ static int disas_neon_insn_2reg_scalar_ext(DisasConte= xt *s, uint32_t insn) int size =3D extract32(insn, 23, 1); int index; =20 - if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) { + if (!aa32_dc_feature_vcma(s)) { return 1; } if (size =3D=3D 0) { @@ -7884,7 +7882,7 @@ static int disas_neon_insn_2reg_scalar_ext(DisasConte= xt *s, uint32_t insn) } else if ((insn & 0xffb00f00) =3D=3D 0xfe200d00) { /* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */ int u =3D extract32(insn, 4, 1); - if (!arm_dc_feature(s, ARM_FEATURE_V8_DOTPROD)) { + if (!aa32_dc_feature_dp(s)) { return 1; } fn_gvec =3D u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_= idx_b; @@ -8860,8 +8858,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) * op1 =3D=3D 3 is UNPREDICTABLE but handle as UNDEFINED. * Bits 8, 10 and 11 should be zero. */ - if (!arm_dc_feature(s, ARM_FEATURE_CRC) || op1 =3D=3D 0x3 || - (c & 0xd) !=3D 0) { + if (!aa32_dc_feature_crc32(s) || op1 =3D=3D 0x3 || (c & 0xd) != =3D 0) { goto illegal_op; } =20 @@ -10706,7 +10703,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) case 0x28: case 0x29: case 0x2a: - if (!arm_dc_feature(s, ARM_FEATURE_CRC)) { + if (!aa32_dc_feature_crc32(s)) { goto illegal_op; } break; --=20 2.17.1 From nobody Wed Nov 5 21:43:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538084511989208.92838012844788; Thu, 27 Sep 2018 14:41:51 -0700 (PDT) Received: from localhost ([::1]:39613 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g5e2g-0005eG-SK for importer@patchew.org; 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id l26-v6sm5395884pfg.161.2018.09.27.14.13.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 27 Sep 2018 14:13:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nb6Ix+T3s3HjmuCnzagE3Rkqdyl2ZuiE59tuUo4Bqes=; b=g+L0AKPxC3y+l2wnN+BnoyreMUX3b5qt3nuv+MdMlJFVVTAFerElCDUJdF+SQ7R3kn RvNa7t0T/jcP+mtmH8Dyo/xT5MfhfSgxgxyHTEckjmY0BkCqXJLMjh/RQe0GDFh6bwGw 03zPqzpKTaelQEj8Sw4wp4YPQteiie0lePFOc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nb6Ix+T3s3HjmuCnzagE3Rkqdyl2ZuiE59tuUo4Bqes=; b=iAcbjAGj+ShVVVYsT2AcosxlkcqAAWUKStbxmkFBKqNRg15AWYu5Mdi74VZdQFs4fY mWhX5OZpDWivILjgeGeqNclaluKwN3u7F2mmVJ8byEtGJr8atc07K80fcGzU8y+uhpME JjT6Wjg0a2Inhv8JVpKGOh7BP2OaZO2Ty2IFJHC1+/3nz2dtmTttzTc3Ag8yc2yVVNZR y0b/HsgmhyTv6oruAtZiRLJMh6YevnzCLi0ikPmy1XynDYbV6ft0vx1HjUbNaxrUV9J2 2Or8iUy0YMou1E22OO5yB4Qp1amtEwIdxpTZojS9RR2W3tpWcft07IjBD6dBbLm7hzny jJtw== X-Gm-Message-State: ABuFfogUUOZ6W+drmPTLXjfXOnWpebGxLldUeT5Rk4coF06oqZUu7tFX vJ7vIiim2J0lEF8eSs6SGEUU4Yua79s= X-Google-Smtp-Source: ACcGV62GOixA7O/9r2vqa9x48Tf5EnQeyzwycj/yrBV54Y6BZ87SaUjgmQ8Ec2GbILNPnioSM+p5rg== X-Received: by 2002:a17:902:263:: with SMTP id 90-v6mr12843159plc.190.1538082809664; Thu, 27 Sep 2018 14:13:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2018 14:13:16 -0700 Message-Id: <20180927211322.16118-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180927211322.16118-1-richard.henderson@linaro.org> References: <20180927211322.16118-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v2 3/9] target/arm: Align cortex-r5 id_isar0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The missing nibble made it more difficult to read. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 17c9c43f41..03bf28f533 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1397,7 +1397,7 @@ static void cortex_r5_initfn(Object *obj) cpu->id_mmfr1 =3D 0x00000000; cpu->id_mmfr2 =3D 0x01200000; cpu->id_mmfr3 =3D 0x0211; - cpu->id_isar0 =3D 0x2101111; + cpu->id_isar0 =3D 0x02101111; cpu->id_isar1 =3D 0x13112111; cpu->id_isar2 =3D 0x21232141; cpu->id_isar3 =3D 0x01112131; --=20 2.17.1 From nobody Wed Nov 5 21:43:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538083855956833.372497136289; Thu, 27 Sep 2018 14:30:55 -0700 (PDT) Received: from localhost ([::1]:39483 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g5ds6-0005Jp-NU for importer@patchew.org; Thu, 27 Sep 2018 17:30:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54149) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g5dpa-0003xe-QW for qemu-devel@nongnu.org; Thu, 27 Sep 2018 17:28:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g5dbI-0000ZX-RX for qemu-devel@nongnu.org; Thu, 27 Sep 2018 17:13:36 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:46817) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g5dbI-0000Xz-HM for qemu-devel@nongnu.org; Thu, 27 Sep 2018 17:13:32 -0400 Received: by mail-pf1-x436.google.com with SMTP id d8-v6so2732732pfo.13 for ; Thu, 27 Sep 2018 14:13:32 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id l26-v6sm5395884pfg.161.2018.09.27.14.13.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 27 Sep 2018 14:13:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Z0GMOl8+Ezd6ThTzXld8zyxZaItNAeQNjpk+btBHUf4=; b=Tdnl4UiyhCkbsPi6vx2WNpIoi0JMGb+U8/CoiHgNdj0q/+mynXx7/MAGXAQpIVmx4/ oY0Gar/NZcn7sLRueYkJBnMx/P/b0VEtNF7E1WXV2CHlIRaZPqdtR0God2aamG3MSOSD FhX+gg3Y2asGvz+Ryvpw1/hZEnYiOLiVVSNBE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Z0GMOl8+Ezd6ThTzXld8zyxZaItNAeQNjpk+btBHUf4=; b=TZ9B6f4Mq6OsycoH7/1ubn/uWm/psv0NYun9LOl0CqGixbzwgP0U2ze/cQZtOZyot2 bq8AH7guBHGuLEtI6mtrF5r0qvoQiqxYcoXPhww304JS1Ez4ut/YjS2LDchCXSty15sx Buoj9FI647OMvsT0DsPqNUZM+cH4gSrAdHCt0KnejVTi4RvXjgTl6Vs0zUA37jicd7Cm z2VeErvDB8KfYQElqnw8B1G88ebAPm3i1q5FXE+DZKZL5SFJVQs1++6KxwwNRewcByeA qCyYQ/UMnhsAJHyNaP2SjdLDjc+G894YZ3tT4MIppDp4zKoVEBz32BrUNYg7u9pvmAfA nTrg== X-Gm-Message-State: ABuFfoh9YEroSvlFXQDQR0sZfBkFIKH/zQ7UNl/4O6FtYsop3jXpdhno YLI/4QnxCZRa3+E5vusphm3WauO4gLU= X-Google-Smtp-Source: ACcGV63r1OgWSOvNE6gUqxQfzstIBOWjvowcE/iBUIaGJvgN/hudYO/FOEGT99MJYk3pE6yuXrhPjg== X-Received: by 2002:a63:f501:: with SMTP id w1-v6mr9192355pgh.336.1538082811137; Thu, 27 Sep 2018 14:13:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2018 14:13:17 -0700 Message-Id: <20180927211322.16118-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180927211322.16118-1-richard.henderson@linaro.org> References: <20180927211322.16118-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::436 Subject: [Qemu-devel] [PATCH v2 4/9] target/arm: Fix cortex-a7 id_isar0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The incorrect value advertised only thumb2 div without arm div. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 03bf28f533..020e79918b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1587,7 +1587,10 @@ static void cortex_a7_initfn(Object *obj) cpu->id_mmfr1 =3D 0x40000000; cpu->id_mmfr2 =3D 0x01240000; cpu->id_mmfr3 =3D 0x02102211; - cpu->id_isar0 =3D 0x01101110; + /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but + * table 4-41 gives 0x02101110, which includes the arm div insns. + */ + cpu->id_isar0 =3D 0x02101110; cpu->id_isar1 =3D 0x13112111; cpu->id_isar2 =3D 0x21232041; cpu->id_isar3 =3D 0x11112131; --=20 2.17.1 From nobody Wed Nov 5 21:43:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538084370635612.4255894109234; Thu, 27 Sep 2018 14:39:30 -0700 (PDT) Received: from localhost ([::1]:39589 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g5e0P-0002ow-AC for importer@patchew.org; Thu, 27 Sep 2018 17:39:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54163) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g5dpZ-0003xg-37 for qemu-devel@nongnu.org; Thu, 27 Sep 2018 17:28:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g5dbR-0000p5-3E for qemu-devel@nongnu.org; Thu, 27 Sep 2018 17:13:45 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:41254) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g5dbM-0000bl-6o for qemu-devel@nongnu.org; Thu, 27 Sep 2018 17:13:37 -0400 Received: by mail-pf1-x441.google.com with SMTP id m77-v6so2747574pfi.8 for ; Thu, 27 Sep 2018 14:13:35 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. [97.113.8.179]) by smtp.gmail.com with ESMTPSA id l26-v6sm5395884pfg.161.2018.09.27.14.13.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 27 Sep 2018 14:13:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=waibaX9GfmLCLeNaQ//+CLR7lm2AHxayHMg40yZdgx4=; b=bF/tA565908qsHFUt3Z9cPy1drHNW4WPpnX7Mi3aZq94hFpZGhVymg8PTIJvkWsqrK kjSJ04hGqAEceRdxikf+vi+ulBJo9fFyA548RqBxCzrSF0sjjBwBVfc5EH6+xobmQhuK +dgFJEzpAaZqsyrJuqMIohSqlLnTKzGPP1rfU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=waibaX9GfmLCLeNaQ//+CLR7lm2AHxayHMg40yZdgx4=; b=bfnqHJL3L5rBipVoz11NDc7Aot0+v83NWIIVG6OglHYi5YBvA70EZ5ReHPl6+MJbTs BA88sigkTltBYksgCwP5RVfDldyhf4hrTJfHB10IG6nUhgYcoDgnxaQiddM8aWzxK7kb scZ/+1s6J/y8kaIniBSGKnLGZjfqMmY5ikwMhCFhj62974coSt29RRgaRS3qY6nxctnE zECL2ZzUphz7ViX0hN+XTzO6QebVJhjOSHZN9HclBXZrhD/fPvwnDeeWVI7oByzmZkSS ldf+ViDeWLRso+XYiJVzIhFGnrOm8K1ssTpEYhp9+zLct3tvN+LNcevpemtS33mcIHG2 tifg== X-Gm-Message-State: ABuFfoh5MopN/DyXb2pOt+24XIqTWPJ9u4+rVLYTlTWjYdpG5y5D1FNz f7F7PdnawNXDiuKHLXjtJNkEN7AEUMo= X-Google-Smtp-Source: ACcGV63Hu7l/+wwNAWN2o7ioeZDdoZLmrXw0l5qGFnYVgAwG16tTbzF41xoEI0WIITzbzl53N+1KDA== X-Received: by 2002:a17:902:bc8b:: with SMTP id bb11-v6mr12749780plb.112.1538082812634; Thu, 27 Sep 2018 14:13:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2018 14:13:18 -0700 Message-Id: <20180927211322.16118-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180927211322.16118-1-richard.henderson@linaro.org> References: <20180927211322.16118-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v2 5/9] target/arm: Convert division from feature bits to isar0 tests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Both arm and thumb2 division are controlled by the same ISAR field, which takes care of the arm implies thumb case. Having M imply thumb2 division was wrong for cortex-m0, which is v6m and does not have thumb2 at all, much less thumb2 division. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 12 ++++++++++-- target/arm/translate.h | 2 ++ linux-user/elfload.c | 4 ++-- target/arm/cpu.c | 10 +--------- target/arm/translate.c | 4 ++-- 5 files changed, 17 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1e3c4650ce..cd57c5aae0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1527,7 +1527,6 @@ enum arm_features { ARM_FEATURE_VFP3, ARM_FEATURE_VFP_FP16, ARM_FEATURE_NEON, - ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */ ARM_FEATURE_M, /* Microcontroller profile. */ ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ ARM_FEATURE_THUMB2EE, @@ -1537,7 +1536,6 @@ enum arm_features { ARM_FEATURE_V5, ARM_FEATURE_STRONGARM, ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ - ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */ ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ ARM_FEATURE_GENERIC_TIMER, ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ @@ -3111,6 +3109,16 @@ extern const uint64_t pred_esz_masks[4]; /* * 32-bit feature tests via id registers. */ +static inline bool aa32_feature_thumb_div(ARMCPU *cpu) +{ + return FIELD_EX32(cpu->id_isar0, ID_ISAR0, DIVIDE) !=3D 0; +} + +static inline bool aa32_feature_arm_div(ARMCPU *cpu) +{ + return FIELD_EX32(cpu->id_isar0, ID_ISAR0, DIVIDE) > 1; +} + static inline bool aa32_feature_aes(ARMCPU *cpu) { return FIELD_EX32(cpu->id_isar5, ID_ISAR5, AES) !=3D 0; diff --git a/target/arm/translate.h b/target/arm/translate.h index baacfd7e6b..3eb863ae43 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -194,6 +194,8 @@ static inline TCGv_i32 get_ahp_flag(void) static inline bool aa32_dc_feature_##NAME(DisasContext *dc) \ { return aa32_feature_##NAME(dc->cpu); } =20 +FORWARD_FEATURE(thumb_div) +FORWARD_FEATURE(arm_div) FORWARD_FEATURE(aes) FORWARD_FEATURE(pmull) FORWARD_FEATURE(sha1) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 408bf67206..1ddb1fd102 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -471,8 +471,8 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4); - GET_FEATURE(ARM_FEATURE_ARM_DIV, ARM_HWCAP_ARM_IDIVA); - GET_FEATURE(ARM_FEATURE_THUMB_DIV, ARM_HWCAP_ARM_IDIVT); + GET_FEATURE_ID(arm_div, ARM_HWCAP_ARM_IDIVA); + GET_FEATURE_ID(thumb_div, ARM_HWCAP_ARM_IDIVT); /* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.= c. * Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of * ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 020e79918b..4f2372c6d7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -825,7 +825,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error *= *errp) * Presence of EL2 itself is ARM_FEATURE_EL2, and of the * Security Extensions is ARM_FEATURE_EL3. */ - set_feature(env, ARM_FEATURE_ARM_DIV); + assert(aa32_feature_arm_div(cpu)); set_feature(env, ARM_FEATURE_LPAE); set_feature(env, ARM_FEATURE_V7); } @@ -858,12 +858,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error = **errp) if (arm_feature(env, ARM_FEATURE_V5)) { set_feature(env, ARM_FEATURE_V4T); } - if (arm_feature(env, ARM_FEATURE_M)) { - set_feature(env, ARM_FEATURE_THUMB_DIV); - } - if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { - set_feature(env, ARM_FEATURE_THUMB_DIV); - } if (arm_feature(env, ARM_FEATURE_VFP4)) { set_feature(env, ARM_FEATURE_VFP3); set_feature(env, ARM_FEATURE_VFP_FP16); @@ -1384,8 +1378,6 @@ static void cortex_r5_initfn(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); =20 set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV); - set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); set_feature(&cpu->env, ARM_FEATURE_V7MP); set_feature(&cpu->env, ARM_FEATURE_PMSA); cpu->midr =3D 0x411fc153; /* r1p3 */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 06d61b1e0d..c94c69e331 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9726,7 +9726,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) case 1: case 3: /* SDIV, UDIV */ - if (!arm_dc_feature(s, ARM_FEATURE_ARM_DIV)) { + if (!aa32_dc_feature_arm_div(s)) { goto illegal_op; } if (((insn >> 5) & 7) || (rd !=3D 15)) { @@ -10884,7 +10884,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) tmp2 =3D load_reg(s, rm); if ((op & 0x50) =3D=3D 0x10) { /* sdiv, udiv */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DIV)) { + if (!aa32_dc_feature_thumb_div(s)) { goto illegal_op; } if (op & 0x20) --=20 2.17.1 From nobody Wed Nov 5 21:43:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538084268640286.81185238200123; Thu, 27 Sep 2018 14:37:48 -0700 (PDT) Received: from localhost ([::1]:39579 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g5dyl-0001em-H7 for importer@patchew.org; Thu, 27 Sep 2018 17:37:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53588) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g5dpX-0002Hp-4u for qemu-devel@nongnu.org; Thu, 27 Sep 2018 17:28:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g5dbR-0000pb-76 for qemu-devel@nongnu.org; Thu, 27 Sep 2018 17:13:45 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:34131) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1g5dbM-0000br-F0 for qemu-devel@nongnu.org; Thu, 27 Sep 2018 17:13:39 -0400 Received: by mail-pf1-x431.google.com with SMTP id k19-v6so2770514pfi.1 for ; Thu, 27 Sep 2018 14:13:35 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-8-179.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::431 Subject: [Qemu-devel] [PATCH v2 6/9] target/arm: Convert jazelle from feature bit to isar1 test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Having V6 alone imply jazelle was wrong for cortex-m0. Change to an assertion for V6 & !M. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 6 +++++- target/arm/translate.h | 1 + target/arm/cpu.c | 17 ++++++++++++++--- target/arm/translate.c | 2 +- 4 files changed, 21 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cd57c5aae0..c9996d2534 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1557,7 +1557,6 @@ enum arm_features { ARM_FEATURE_PMU, /* has PMU support */ ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ - ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ ARM_FEATURE_SVE, /* has Scalable Vector Extension */ ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ ARM_FEATURE_M_MAIN, /* M profile Main Extension */ @@ -3119,6 +3118,11 @@ static inline bool aa32_feature_arm_div(ARMCPU *cpu) return FIELD_EX32(cpu->id_isar0, ID_ISAR0, DIVIDE) > 1; } =20 +static inline bool aa32_feature_jazelle(ARMCPU *cpu) +{ + return FIELD_EX32(cpu->id_isar1, ID_ISAR1, JAZELLE) !=3D 0; +} + static inline bool aa32_feature_aes(ARMCPU *cpu) { return FIELD_EX32(cpu->id_isar5, ID_ISAR5, AES) !=3D 0; diff --git a/target/arm/translate.h b/target/arm/translate.h index 3eb863ae43..d8eafbe88d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -196,6 +196,7 @@ static inline TCGv_i32 get_ahp_flag(void) =20 FORWARD_FEATURE(thumb_div) FORWARD_FEATURE(arm_div) +FORWARD_FEATURE(jazelle) FORWARD_FEATURE(aes) FORWARD_FEATURE(pmull) FORWARD_FEATURE(sha1) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4f2372c6d7..41a1b27c61 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -850,8 +850,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error *= *errp) } if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); - set_feature(env, ARM_FEATURE_JAZELLE); if (!arm_feature(env, ARM_FEATURE_M)) { + assert(aa32_feature_jazelle(cpu)); set_feature(env, ARM_FEATURE_AUXCR); } } @@ -1078,11 +1078,16 @@ static void arm926_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); - set_feature(&cpu->env, ARM_FEATURE_JAZELLE); cpu->midr =3D 0x41069265; cpu->reset_fpsid =3D 0x41011090; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00090078; + + /* + * ARMv5 does not have the ID_ISAR registers, but we can still + * set the field to indicate Jazelle support within QEMU. + */ + FIELD_DP32(cpu->id_isar1, ID_ISAR1, JAZELLE, 1); } =20 static void arm946_initfn(Object *obj) @@ -1108,12 +1113,18 @@ static void arm1026_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_AUXCR); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); - set_feature(&cpu->env, ARM_FEATURE_JAZELLE); cpu->midr =3D 0x4106a262; cpu->reset_fpsid =3D 0x410110a0; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00090078; cpu->reset_auxcr =3D 1; + + /* + * ARMv5 does not have the ID_ISAR registers, but we can still + * set the field to indicate Jazelle support within QEMU. + */ + FIELD_DP32(cpu->id_isar1, ID_ISAR1, JAZELLE, 1); + { /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0= ,2 */ ARMCPRegInfo ifar =3D { diff --git a/target/arm/translate.c b/target/arm/translate.c index c94c69e331..4036be6828 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -42,7 +42,7 @@ #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) /* currently all emulated v5 cores are also v5TE, so don't bother */ #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5) -#define ENABLE_ARCH_5J arm_dc_feature(s, ARM_FEATURE_JAZELLE) +#define ENABLE_ARCH_5J aa32_dc_feature_jazelle(s) #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6) #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K) #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2) --=20 2.17.1 From nobody Wed Nov 5 21:43:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v2 7/9] target/arm: Convert t32ee from feature bit to isar3 test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 6 +++++- linux-user/elfload.c | 2 +- target/arm/cpu.c | 4 ---- target/arm/helper.c | 2 +- target/arm/machine.c | 3 +-- 5 files changed, 8 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c9996d2534..da841f8538 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1529,7 +1529,6 @@ enum arm_features { ARM_FEATURE_NEON, ARM_FEATURE_M, /* Microcontroller profile. */ ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ - ARM_FEATURE_THUMB2EE, ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */ ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */ ARM_FEATURE_V4T, @@ -3123,6 +3122,11 @@ static inline bool aa32_feature_jazelle(ARMCPU *cpu) return FIELD_EX32(cpu->id_isar1, ID_ISAR1, JAZELLE) !=3D 0; } =20 +static inline bool aa32_feature_t32ee(ARMCPU *cpu) +{ + return FIELD_EX32(cpu->id_isar3, ID_ISAR3, T32EE) !=3D 0; +} + static inline bool aa32_feature_aes(ARMCPU *cpu) { return FIELD_EX32(cpu->id_isar5, ID_ISAR5, AES) !=3D 0; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 1ddb1fd102..01707ebb91 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -466,7 +466,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); - GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); + GET_FEATURE_ID(t32ee, ARM_HWCAP_ARM_THUMBEE); GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 41a1b27c61..abb1b6fe5c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1436,7 +1436,6 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr =3D 0x410fc080; @@ -1505,7 +1504,6 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); /* Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different @@ -1568,7 +1566,6 @@ static void cortex_a7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); @@ -1614,7 +1611,6 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7VE); set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); diff --git a/target/arm/helper.c b/target/arm/helper.c index 64b1564594..5af89f6d9d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5328,7 +5328,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_cp_reginfo); } - if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { + if (aa32_feature_t32ee(cpu)) { define_arm_cp_regs(cpu, t2ee_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { diff --git a/target/arm/machine.c b/target/arm/machine.c index ff4ec22bf7..d44e891533 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -301,9 +301,8 @@ static const VMStateDescription vmstate_m =3D { static bool thumb2ee_needed(void *opaque) { ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; =20 - return arm_feature(env, ARM_FEATURE_THUMB2EE); + return aa32_feature_t32ee(cpu); } =20 static const VMStateDescription vmstate_thumb2ee =3D { --=20 2.17.1 From nobody Wed Nov 5 21:43:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538084206472408.0569987817628; Thu, 27 Sep 2018 14:36:46 -0700 (PDT) Received: from localhost ([::1]:39562 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g5dxl-00014J-Cj for importer@patchew.org; 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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id l26-v6sm5395884pfg.161.2018.09.27.14.13.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 27 Sep 2018 14:13:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HOK4cOiwY/tcc36qeD6UyKo9TSFGfz9ZdKuHA+NVUUY=; b=awZ2OGjN0B+fWczHe8i6KYnjlZ6OzrU2SVtswlvAV1GelBm4vlZXzbW2lZRMH5Z5C/ Z8uZH3xpMN6JnnFQ0GzZ6I/kVh4BBfhbH2NbsROYSzVRx3Ztxft2XMb/boSkUyKpqJAg jUgConwOYWmZLN5PJqFlckhThjDhCm+3BTolY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HOK4cOiwY/tcc36qeD6UyKo9TSFGfz9ZdKuHA+NVUUY=; b=qjFk4ZiTMV2JK9qqTZ4tjUENZtiMs/2VFzQXo/OhcM3msr0DB7mhqlV1yiRFQXt1fI Chv67zJLk56HeajCV5Llut4oRaKNx+VJba7lKDZ6BKcBLnXdrA31X9gOZpyLfTBWprn6 UYo80lSdJCcs4zohgXnP2+agp2K+oYROY51NbtwZf1quMlb8gvJRQmuKupHZ4vWhkbT2 JCF6OuaoM8KyioTTfDEuIHPVOGX33h+XXAuBf22M5Tn7fIswMA1vTzq2UTRJnMMpKjVR q47VUs00Biip003vv+zk6hbmMzBd634pS/uX0iknGT0bt47XHOwIUlkl6gxZoueu/Oxy otYQ== X-Gm-Message-State: ABuFfoh21Aw94DYxvymAdcOoM232e5qCSqZ6HQK0siWSMUhyzCAePN2Z RVPkwR4uhDKMUkTwHZjdefRQfVj7nHs= X-Google-Smtp-Source: ACcGV62MdpA/1OFzgSI15IztU8G13smVJkGCPNAub8J9VvtymKq2SKj5/Z0udsOe6wKlASK4xhufTQ== X-Received: by 2002:a63:145f:: with SMTP id 31-v6mr221261pgu.35.1538082817040; Thu, 27 Sep 2018 14:13:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2018 14:13:21 -0700 Message-Id: <20180927211322.16118-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180927211322.16118-1-richard.henderson@linaro.org> References: <20180927211322.16118-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::432 Subject: [Qemu-devel] [PATCH v2 8/9] target/arm: Convert sve from feature bit to pfr0 test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 16 +++++++++++++++- target/arm/translate-a64.h | 1 + linux-user/aarch64/signal.c | 4 ++-- linux-user/elfload.c | 2 +- linux-user/syscall.c | 10 ++++++---- target/arm/cpu64.c | 3 ++- target/arm/helper.c | 7 ++++--- target/arm/machine.c | 3 +-- target/arm/translate-a64.c | 4 ++-- 9 files changed, 34 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index da841f8538..152a558a94 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1508,6 +1508,16 @@ FIELD(ID_AA64ISAR1, LRCPC, 20, 4) FIELD(ID_AA64ISAR1, GPA, 24, 4) FIELD(ID_AA64ISAR1, GPI, 28, 4) =20 +FIELD(ID_AA64PFR0, EL0, 0, 4) +FIELD(ID_AA64PFR0, EL1, 4, 4) +FIELD(ID_AA64PFR0, EL2, 8, 4) +FIELD(ID_AA64PFR0, EL3, 12, 4) +FIELD(ID_AA64PFR0, FP, 16, 4) +FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) +FIELD(ID_AA64PFR0, GIC, 24, 4) +FIELD(ID_AA64PFR0, RAS, 28, 4) +FIELD(ID_AA64PFR0, SVE, 32, 4) + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=3D R_V7M_CSSELR_INDE= X_MASK); =20 /* If adding a feature bit which corresponds to a Linux ELF @@ -1556,7 +1566,6 @@ enum arm_features { ARM_FEATURE_PMU, /* has PMU support */ ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ - ARM_FEATURE_SVE, /* has Scalable Vector Extension */ ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ ARM_FEATURE_M_MAIN, /* M profile Main Extension */ }; @@ -3235,4 +3244,9 @@ static inline bool aa64_feature_fcma(ARMCPU *cpu) return FIELD_EX64(cpu->id_aa64isar1, ID_AA64ISAR1, FCMA) !=3D 0; } =20 +static inline bool aa64_feature_sve(ARMCPU *cpu) +{ + return FIELD_EX64(cpu->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0; +} + #endif diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index b4ef9eb024..636f3fded3 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -140,6 +140,7 @@ FORWARD_FEATURE(sm3) FORWARD_FEATURE(sm4) FORWARD_FEATURE(dp) FORWARD_FEATURE(fcma) +FORWARD_FEATURE(sve) =20 #undef FORWARD_FEATURE =20 diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 07fedfc33c..65272fb7a9 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -314,7 +314,7 @@ static int target_restore_sigframe(CPUARMState *env, break; =20 case TARGET_SVE_MAGIC: - if (arm_feature(env, ARM_FEATURE_SVE)) { + if (aa64_feature_sve(arm_env_get_cpu(env))) { vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq)= , 16); if (!sve && size =3D=3D sve_size) { @@ -433,7 +433,7 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, &layout); =20 /* SVE state needs saving only if it exists. */ - if (arm_feature(env, ARM_FEATURE_SVE)) { + if (aa64_feature_sve(arm_env_get_cpu(env))) { vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; sve_size =3D QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); sve_ofs =3D alloc_sigframe_space(sve_size, &layout); diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 01707ebb91..c4969f163e 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -593,7 +593,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(rdm, ARM_HWCAP_A64_ASIMDRDM); GET_FEATURE_ID(dp, ARM_HWCAP_A64_ASIMDDP); GET_FEATURE_ID(fcma, ARM_HWCAP_A64_FCMA); - GET_FEATURE(ARM_FEATURE_SVE, ARM_HWCAP_A64_SVE); + GET_FEATURE_ID(sve, ARM_HWCAP_A64_SVE); =20 #undef GET_FEATURE #undef GET_FEATURE_ID diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 850b72a0c7..f927f51fb4 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10735,7 +10735,7 @@ static abi_long do_syscall1(void *cpu_env, int num,= abi_long arg1, * even though the current architectural maximum is VQ=3D16. */ ret =3D -TARGET_EINVAL; - if (arm_feature(cpu_env, ARM_FEATURE_SVE) + if (aa64_feature_sve(arm_env_get_cpu(cpu_env)) && arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) { CPUARMState *env =3D cpu_env; ARMCPU *cpu =3D arm_env_get_cpu(env); @@ -10754,9 +10754,11 @@ static abi_long do_syscall1(void *cpu_env, int num= , abi_long arg1, return ret; case TARGET_PR_SVE_GET_VL: ret =3D -TARGET_EINVAL; - if (arm_feature(cpu_env, ARM_FEATURE_SVE)) { - CPUARMState *env =3D cpu_env; - ret =3D ((env->vfp.zcr_el[1] & 0xf) + 1) * 16; + { + ARMCPU *cpu =3D arm_env_get_cpu(cpu_env); + if (aa64_feature_sve(cpu)) { + ret =3D ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; + } } return ret; #endif /* AARCH64 */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f9830b67f3..8f95de677a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -258,6 +258,8 @@ static void aarch64_max_initfn(Object *obj) =20 FIELD_DP64(cpu->id_aa64isar1, ID_AA64ISAR1, FCMA, 1); =20 + FIELD_DP64(cpu->id_aa64pfr0, ID_AA64PFR0, SVE, 1); + /* Replicate the same data to the 32-bit id registers. */ FIELD_DP32(cpu->id_isar5, ID_ISAR5, AES, 2); /* AES + PMULL */ FIELD_DP32(cpu->id_isar5, ID_ISAR5, SHA1, 1); @@ -275,7 +277,6 @@ static void aarch64_max_initfn(Object *obj) * present in either. */ set_feature(&cpu->env, ARM_FEATURE_V8_FP16); - set_feature(&cpu->env, ARM_FEATURE_SVE); /* For usermode -cpu max we can use a larger and more efficient DCZ * blocksize since we don't have to follow what the hardware does. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 5af89f6d9d..dd3a2c0b8b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5587,7 +5587,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &sctlr); } =20 - if (arm_feature(env, ARM_FEATURE_SVE)) { + if (aa64_feature_sve(cpu)) { define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); if (arm_feature(env, ARM_FEATURE_EL2)) { define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); @@ -12587,13 +12587,15 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, uint32_t flags; =20 if (is_a64(env)) { + ARMCPU *cpu =3D arm_env_get_cpu(env); + *pc =3D env->pc; flags =3D ARM_TBFLAG_AARCH64_STATE_MASK; /* Get control bits for tagged addresses */ flags |=3D (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT= ); flags |=3D (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT= ); =20 - if (arm_feature(env, ARM_FEATURE_SVE)) { + if (aa64_feature_sve(cpu)) { int sve_el =3D sve_exception_el(env); uint32_t zcr_len; =20 @@ -12604,7 +12606,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, zcr_len =3D 0; } else { int current_el =3D arm_current_el(env); - ARMCPU *cpu =3D arm_env_get_cpu(env); =20 zcr_len =3D cpu->sve_max_vq - 1; if (current_el <=3D 1) { diff --git a/target/arm/machine.c b/target/arm/machine.c index d44e891533..8b3ba96889 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -131,9 +131,8 @@ static const VMStateDescription vmstate_iwmmxt =3D { static bool sve_needed(void *opaque) { ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; =20 - return arm_feature(env, ARM_FEATURE_SVE); + return aa64_feature_sve(cpu); } =20 /* The first two words of each Zreg is stored in VFP state. */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 40575485aa..5527ffb203 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -169,7 +169,7 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, cpu_fprintf(f, " FPCR=3D%08x FPSR=3D%08x\n", vfp_get_fpcr(env), vfp_get_fpsr(env)); =20 - if (arm_feature(env, ARM_FEATURE_SVE)) { + if (aa64_feature_sve(cpu)) { int j, zcr_len =3D env->vfp.zcr_el[1] & 0xf; /* fix for system mod= e */ =20 for (i =3D 0; i <=3D FFR_PRED_NUM; i++) { @@ -13786,7 +13786,7 @@ static void disas_a64_insn(CPUARMState *env, DisasC= ontext *s) unallocated_encoding(s); break; case 0x2: - if (!arm_dc_feature(s, ARM_FEATURE_SVE) || !disas_sve(s, insn)) { + if (!aa64_dc_feature_sve(s) || !disas_sve(s, insn)) { unallocated_encoding(s); } break; --=20 2.17.1 From nobody Wed Nov 5 21:43:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:4864:20::52a Subject: [Qemu-devel] [PATCH v2 9/9] target/arm: Convert v8.2-fp16 from feature bit to pfr0 test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 17 +++++++++++++++- target/arm/translate-a64.h | 1 + target/arm/translate.h | 1 + linux-user/elfload.c | 6 +----- target/arm/cpu64.c | 13 ++++++------- target/arm/helper.c | 2 +- target/arm/translate-a64.c | 40 +++++++++++++++++++------------------- target/arm/translate.c | 6 +++--- 8 files changed, 49 insertions(+), 37 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 152a558a94..bca4ee4281 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1566,7 +1566,6 @@ enum arm_features { ARM_FEATURE_PMU, /* has PMU support */ ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ - ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ ARM_FEATURE_M_MAIN, /* M profile Main Extension */ }; =20 @@ -3176,6 +3175,16 @@ static inline bool aa32_feature_dp(ARMCPU *cpu) return FIELD_EX32(cpu->id_isar6, ID_ISAR6, DP) !=3D 0; } =20 +static inline bool aa32_feature_fp16_arith(ARMCPU *cpu) +{ + /* + * This is a placeholder for use by VCMA until the rest of + * the ARMv8.2-FP16 extension is implemented for aa32 mode. + * At which point we can properly set and check MVFR1.FPHP. + */ + return FIELD_EX64(cpu->id_aa64pfr0, ID_AA64PFR0, FP) =3D=3D 1; +} + /* * 64-bit feature tests via id registers. */ @@ -3244,6 +3253,12 @@ static inline bool aa64_feature_fcma(ARMCPU *cpu) return FIELD_EX64(cpu->id_aa64isar1, ID_AA64ISAR1, FCMA) !=3D 0; } =20 +static inline bool aa64_feature_fp16(ARMCPU *cpu) +{ + /* We always set the AdvSIMD and FP fields identically wrt FP16. */ + return FIELD_EX64(cpu->id_aa64pfr0, ID_AA64PFR0, FP) =3D=3D 1; +} + static inline bool aa64_feature_sve(ARMCPU *cpu) { return FIELD_EX64(cpu->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0; diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 636f3fded3..e122cef242 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -140,6 +140,7 @@ FORWARD_FEATURE(sm3) FORWARD_FEATURE(sm4) FORWARD_FEATURE(dp) FORWARD_FEATURE(fcma) +FORWARD_FEATURE(fp16) FORWARD_FEATURE(sve) =20 #undef FORWARD_FEATURE diff --git a/target/arm/translate.h b/target/arm/translate.h index d8eafbe88d..e022d6d4e6 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -205,6 +205,7 @@ FORWARD_FEATURE(crc32) FORWARD_FEATURE(rdm) FORWARD_FEATURE(vcma) FORWARD_FEATURE(dp) +FORWARD_FEATURE(fp16_arith) =20 #undef FORWARD_FEATURE =20 diff --git a/linux-user/elfload.c b/linux-user/elfload.c index c4969f163e..bcb2c9928c 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -573,8 +573,6 @@ static uint32_t get_elf_hwcap(void) hwcaps |=3D ARM_HWCAP_A64_ASIMD; =20 /* probe for the extra features */ -#define GET_FEATURE(feat, hwcap) \ - do { if (arm_feature(&cpu->env, feat)) { hwcaps |=3D hwcap; } } while = (0) #define GET_FEATURE_ID(feat, hwcap) \ do { if (aa64_feature_##feat(cpu)) { hwcaps |=3D hwcap; } } while (0) =20 @@ -587,15 +585,13 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(sha3, ARM_HWCAP_A64_SHA3); GET_FEATURE_ID(sm3, ARM_HWCAP_A64_SM3); GET_FEATURE_ID(sm4, ARM_HWCAP_A64_SM4); - GET_FEATURE(ARM_FEATURE_V8_FP16, - ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP); + GET_FEATURE_ID(fp16, ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP); GET_FEATURE_ID(atomics, ARM_HWCAP_A64_ATOMICS); GET_FEATURE_ID(rdm, ARM_HWCAP_A64_ASIMDRDM); GET_FEATURE_ID(dp, ARM_HWCAP_A64_ASIMDDP); GET_FEATURE_ID(fcma, ARM_HWCAP_A64_FCMA); GET_FEATURE_ID(sve, ARM_HWCAP_A64_SVE); =20 -#undef GET_FEATURE #undef GET_FEATURE_ID =20 return hwcaps; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 8f95de677a..c734e2b2cd 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -259,6 +259,8 @@ static void aarch64_max_initfn(Object *obj) FIELD_DP64(cpu->id_aa64isar1, ID_AA64ISAR1, FCMA, 1); =20 FIELD_DP64(cpu->id_aa64pfr0, ID_AA64PFR0, SVE, 1); + FIELD_DP64(cpu->id_aa64pfr0, ID_AA64PFR0, FP, 1); + FIELD_DP64(cpu->id_aa64pfr0, ID_AA64PFR0, ADVSIMD, 1); =20 /* Replicate the same data to the 32-bit id registers. */ FIELD_DP32(cpu->id_isar5, ID_ISAR5, AES, 2); /* AES + PMULL */ @@ -268,15 +270,12 @@ static void aarch64_max_initfn(Object *obj) FIELD_DP32(cpu->id_isar5, ID_ISAR5, RDM, 1); FIELD_DP32(cpu->id_isar5, ID_ISAR5, VCMA, 1); FIELD_DP32(cpu->id_isar6, ID_ISAR6, DP, 1); + /* + * FIXME: ARMv8.2-FP16 is not implemented for aa32, + * so do not set MVFR1.FPHP and MVFR.SIMDHP. + */ =20 #ifdef CONFIG_USER_ONLY - /* We don't set these in system emulation mode for the moment, - * since we don't correctly set the ID registers to advertise them, - * and in some cases they're only available in AArch64 and not AAr= ch32, - * whereas the architecture requires them to be present in both if - * present in either. - */ - set_feature(&cpu->env, ARM_FEATURE_V8_FP16); /* For usermode -cpu max we can use a larger and more efficient DCZ * blocksize since we don't have to follow what the hardware does. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index dd3a2c0b8b..996af1b0b3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11528,7 +11528,7 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32= _t val) uint32_t changed; =20 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ - if (!arm_feature(env, ARM_FEATURE_V8_FP16)) { + if (!aa64_feature_fp16(arm_env_get_cpu(env))) { val &=3D ~FPCR_FZ16; } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5527ffb203..095d204992 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4801,7 +4801,7 @@ static void disas_fp_compare(DisasContext *s, uint32_= t insn) break; case 3: size =3D MO_16; - if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + if (aa64_dc_feature_fp16(s)) { break; } /* fallthru */ @@ -4852,7 +4852,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t = insn) break; case 3: size =3D MO_16; - if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + if (aa64_dc_feature_fp16(s)) { break; } /* fallthru */ @@ -4918,7 +4918,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t i= nsn) break; case 3: sz =3D MO_16; - if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + if (aa64_dc_feature_fp16(s)) { break; } /* fallthru */ @@ -5251,7 +5251,7 @@ static void disas_fp_1src(DisasContext *s, uint32_t i= nsn) handle_fp_1src_double(s, opcode, rd, rn); break; case 3: - if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + if (!aa64_dc_feature_fp16(s)) { unallocated_encoding(s); return; } @@ -5466,7 +5466,7 @@ static void disas_fp_2src(DisasContext *s, uint32_t i= nsn) handle_fp_2src_double(s, opcode, rd, rn, rm); break; case 3: - if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + if (!aa64_dc_feature_fp16(s)) { unallocated_encoding(s); return; } @@ -5624,7 +5624,7 @@ static void disas_fp_3src(DisasContext *s, uint32_t i= nsn) handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra); break; case 3: - if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + if (!aa64_dc_feature_fp16(s)) { unallocated_encoding(s); return; } @@ -5694,7 +5694,7 @@ static void disas_fp_imm(DisasContext *s, uint32_t in= sn) break; case 3: sz =3D MO_16; - if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + if (aa64_dc_feature_fp16(s)) { break; } /* fallthru */ @@ -5919,7 +5919,7 @@ static void disas_fp_fixed_conv(DisasContext *s, uint= 32_t insn) case 1: /* float64 */ break; case 3: /* float16 */ - if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + if (aa64_dc_feature_fp16(s)) { break; } /* fallthru */ @@ -6049,7 +6049,7 @@ static void disas_fp_int_conv(DisasContext *s, uint32= _t insn) break; case 0x6: /* 16-bit float, 32-bit int */ case 0xe: /* 16-bit float, 64-bit int */ - if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + if (aa64_dc_feature_fp16(s)) { break; } /* fallthru */ @@ -6076,7 +6076,7 @@ static void disas_fp_int_conv(DisasContext *s, uint32= _t insn) case 1: /* float64 */ break; case 3: /* float16 */ - if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + if (aa64_dc_feature_fp16(s)) { break; } /* fallthru */ @@ -6513,7 +6513,7 @@ static void disas_simd_across_lanes(DisasContext *s, = uint32_t insn) */ is_min =3D extract32(size, 1, 1); is_fp =3D true; - if (!is_u && arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + if (!is_u && aa64_dc_feature_fp16(s)) { size =3D 1; } else if (!is_u || !is_q || extract32(size, 0, 1)) { unallocated_encoding(s); @@ -6909,7 +6909,7 @@ static void disas_simd_mod_imm(DisasContext *s, uint3= 2_t insn) =20 if (o2 !=3D 0 || ((cmode =3D=3D 0xf) && is_neg && !is_q)) { /* Check for FMOV (vector, immediate) - half-precision */ - if (!(arm_dc_feature(s, ARM_FEATURE_V8_FP16) && o2 && cmode =3D=3D= 0xf)) { + if (!(aa64_dc_feature_fp16(s) && o2 && cmode =3D=3D 0xf)) { unallocated_encoding(s); return; } @@ -7076,7 +7076,7 @@ static void disas_simd_scalar_pairwise(DisasContext *= s, uint32_t insn) case 0x2f: /* FMINP */ /* FP op, size[0] is 32 or 64 bit*/ if (!u) { - if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + if (!aa64_dc_feature_fp16(s)) { unallocated_encoding(s); return; } else { @@ -7721,7 +7721,7 @@ static void handle_simd_shift_intfp_conv(DisasContext= *s, bool is_scalar, size =3D MO_32; } else if (immh & 2) { size =3D MO_16; - if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + if (!aa64_dc_feature_fp16(s)) { unallocated_encoding(s); return; } @@ -7766,7 +7766,7 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, size =3D MO_32; } else if (immh & 0x2) { size =3D MO_16; - if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + if (!aa64_dc_feature_fp16(s)) { unallocated_encoding(s); return; } @@ -8530,7 +8530,7 @@ static void disas_simd_scalar_three_reg_same_fp16(Dis= asContext *s, return; } =20 - if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + if (!aa64_dc_feature_fp16(s)) { unallocated_encoding(s); } =20 @@ -11211,7 +11211,7 @@ static void disas_simd_three_reg_same_fp16(DisasCon= text *s, uint32_t insn) TCGv_ptr fpst; bool pairwise =3D false; =20 - if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + if (!aa64_dc_feature_fp16(s)) { unallocated_encoding(s); return; } @@ -11426,7 +11426,7 @@ static void disas_simd_three_reg_same_extra(DisasCo= ntext *s, uint32_t insn) case 0x1c: /* FCADD, #90 */ case 0x1e: /* FCADD, #270 */ if (size =3D=3D 0 - || (size =3D=3D 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) + || (size =3D=3D 1 && !aa64_dc_feature_fp16(s)) || (size =3D=3D 3 && !is_q)) { unallocated_encoding(s); return; @@ -12306,7 +12306,7 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) bool need_fpst =3D true; int rmode; =20 - if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + if (!aa64_dc_feature_fp16(s)) { unallocated_encoding(s); return; } @@ -12723,7 +12723,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) } break; } - if (is_fp16 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + if (is_fp16 && !aa64_dc_feature_fp16(s)) { unallocated_encoding(s); return; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 4036be6828..3dac413c82 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7783,7 +7783,7 @@ static int disas_neon_insn_3same_ext(DisasContext *s,= uint32_t insn) int size =3D extract32(insn, 20, 1); data =3D extract32(insn, 23, 2); /* rot */ if (!aa32_dc_feature_vcma(s) - || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { + || (!size && !aa32_dc_feature_fp16_arith(s))) { return 1; } fn_gvec_ptr =3D size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fc= mlah; @@ -7792,7 +7792,7 @@ static int disas_neon_insn_3same_ext(DisasContext *s,= uint32_t insn) int size =3D extract32(insn, 20, 1); data =3D extract32(insn, 24, 1); /* rot */ if (!aa32_dc_feature_vcma(s) - || (!size && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { + || (!size && !aa32_dc_feature_fp16_arith(s))) { return 1; } fn_gvec_ptr =3D size ? gen_helper_gvec_fcadds : gen_helper_gvec_fc= addh; @@ -7865,7 +7865,7 @@ static int disas_neon_insn_2reg_scalar_ext(DisasConte= xt *s, uint32_t insn) return 1; } if (size =3D=3D 0) { - if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + if (!aa32_dc_feature_fp16_arith(s)) { return 1; } /* For fp16, rm is just Vm, and index is M. */ --=20 2.17.1