From nobody Wed Nov 5 22:23:54 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538063808665260.5228956449595; Thu, 27 Sep 2018 08:56:48 -0700 (PDT) Received: from localhost ([::1]:36918 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g5Yel-0007Qc-I5 for importer@patchew.org; Thu, 27 Sep 2018 11:56:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34482) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g5Ydl-00078W-Dw for qemu-devel@nongnu.org; Thu, 27 Sep 2018 11:55:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g5Ydk-0008N9-It for qemu-devel@nongnu.org; Thu, 27 Sep 2018 11:55:45 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48672) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g5Ydk-0008M2-78 for qemu-devel@nongnu.org; Thu, 27 Sep 2018 11:55:44 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1g5Ydh-0002vF-7G; Thu, 27 Sep 2018 16:55:41 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2018 16:55:38 +0100 Message-Id: <20180927155538.699-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.19.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH] hw/display/qxl: Suppress clang-7 warning about misaligned atomic operation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Gerd Hoffmann , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" If QEMU is compiled with clang-7 it results in the warning: hw/display/qxl.c:1884:19: error: misaligned or large atomic operation may incur significant performance penalty [-Werror,-Watomic-alignment] old_pending =3D atomic_fetch_or(&d->ram->int_pending, le_events); ^ This is because the Spice headers forgot to define the QXLRam struct with the '__aligned__(4)' attribute. clang 7 and newer will thus warn that the access here to int_pending might not be 4-aligned (because the QXLRam object d->ram points at might start at a misaligned address). In fact we set up d->ram in init_qxl_ram() so it always starts at a 4K boundary, so we know the atomic access here is OK. Newer Spice versions (with Spice commit beda5ec7a6848be20c0cac2a9a8ef2a41e8069c1) will fix the bug; for older Spice versions, work around it by telling the compiler explicitly that the alignment is OK using __builtin_assume_aligned(). Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/qemu/compiler.h | 9 +++++++++ hw/display/qxl.c | 26 +++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h index 5843812710c..bf47e7bee4e 100644 --- a/include/qemu/compiler.h +++ b/include/qemu/compiler.h @@ -122,6 +122,15 @@ #ifndef __has_feature #define __has_feature(x) 0 /* compatibility with non-clang compilers */ #endif + +#ifndef __has_builtin +#define __has_builtin(x) 0 /* compatibility with non-clang compilers */ +#endif + +#if __has_builtin(__builtin_assume_aligned) || QEMU_GNUC_PREREQ(4, 7) +#define HAS_ASSUME_ALIGNED +#endif + /* Implement C11 _Generic via GCC builtins. Example: * * QEMU_GENERIC(x, (float, sinf), (long double, sinl), sin) (x) diff --git a/hw/display/qxl.c b/hw/display/qxl.c index 8e9135d9c67..5702e8645d3 100644 --- a/hw/display/qxl.c +++ b/hw/display/qxl.c @@ -1881,7 +1881,31 @@ static void qxl_send_events(PCIQXLDevice *d, uint32_= t events) trace_qxl_send_events_vm_stopped(d->id, events); return; } - old_pending =3D atomic_fetch_or(&d->ram->int_pending, le_events); + /* + * Older versions of Spice forgot to define the QXLRam struct + * with the '__aligned__(4)' attribute. clang 7 and newer will + * thus warn that atomic_fetch_or(&d->ram->int_pending, ...) + * might be a misaligned atomic access, and will generate an + * out-of-line call for it, which results in a link error since + * we don't currently link against libatomic. + * + * In fact we set up d->ram in init_qxl_ram() so it always starts + * at a 4K boundary, so we know that &d->ram->int_pending is + * naturally aligned for a uint32_t. Newer Spice versions + * (with Spice commit beda5ec7a6848be20c0cac2a9a8ef2a41e8069c1) + * will fix the bug directly. To deal with older versions, + * we tell the compiler to assume the address really is aligned. + * Any compiler which cares about the misalignment will have + * __builtin_assume_aligned. + */ +#ifdef HAS_ASSUME_ALIGNED +#define ALIGNED_UINT32_PTR(P) ((uint32_t *)__builtin_assume_aligned(P, 4)) +#else +#define ALIGNED_UINT32_PTR(P) ((uint32_t *)P) +#endif + + old_pending =3D atomic_fetch_or(ALIGNED_UINT32_PTR(&d->ram->int_pendin= g), + le_events); if ((old_pending & le_events) =3D=3D le_events) { return; } --=20 2.19.0