From nobody Sun Apr 28 12:06:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1538050337646212.48905927877638; Thu, 27 Sep 2018 05:12:17 -0700 (PDT) Received: from localhost ([::1]:35506 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g5V9O-0006tS-Vw for importer@patchew.org; Thu, 27 Sep 2018 08:12:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46985) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g5V8Q-0006XE-RH for qemu-devel@nongnu.org; Thu, 27 Sep 2018 08:11:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g5V8K-0005YT-V1 for qemu-devel@nongnu.org; Thu, 27 Sep 2018 08:11:10 -0400 Received: from mx1.redhat.com ([209.132.183.28]:41422) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g5V8K-0005YH-Lw for qemu-devel@nongnu.org; Thu, 27 Sep 2018 08:11:04 -0400 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B5640307C700; Thu, 27 Sep 2018 12:11:03 +0000 (UTC) Received: from sirius.home.kraxel.org (ovpn-116-56.phx2.redhat.com [10.3.116.56]) by smtp.corp.redhat.com (Postfix) with ESMTP id B35A21852C; Thu, 27 Sep 2018 12:10:56 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id 9FA943EB94; Thu, 27 Sep 2018 14:10:55 +0200 (CEST) From: Gerd Hoffmann To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2018 14:10:55 +0200 Message-Id: <20180927121055.28361-1-kraxel@redhat.com> X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.42]); Thu, 27 Sep 2018 12:11:03 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH] pci-testdev: add optional memory bar X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lersek@redhat.com, Gerd Hoffmann , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add memory bar to pci-testdev. Size is configurable using the membar property. Setting the size to zero (default) turns it off. Can be used to check whenever guests handle large pci bars correctly. Signed-off-by: Gerd Hoffmann Reviewed-by: Laszlo Ersek Reviewed-by: Marc-Andr=C3=A9 Lureau Tested-by: Laszlo Ersek --- docs/specs/pci-testdev.txt | 13 +++++++++---- hw/misc/pci-testdev.c | 18 ++++++++++++++++++ 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/docs/specs/pci-testdev.txt b/docs/specs/pci-testdev.txt index 128ae222ef..6b8ace1c55 100644 --- a/docs/specs/pci-testdev.txt +++ b/docs/specs/pci-testdev.txt @@ -1,11 +1,11 @@ pci-test is a device used for testing low level IO =20 -device implements up to two BARs: BAR0 and BAR1. -Each BAR can be memory or IO. Guests must detect +device implements up to three BARs: BAR0, BAR1 and BAR2. +BAR 0+1 can be memory or IO. Guests must detect BAR type and act accordingly. =20 -Each BAR size is up to 4K bytes. -Each BAR starts with the following header: +BAR 0+1 size is up to 4K bytes. +BAR 0+1 starts with the following header: =20 typedef struct PCITestDevHdr { uint8_t test; <- write-only, starts a given test number @@ -24,3 +24,8 @@ All registers are little endian. device is expected to always implement tests 0 to N on each BAR, and to ad= d new tests with higher numbers. In this way a guest can scan test numbers unti= l it detects an access type that it does not support on this BAR, then stop. + +BAR2 is a 64bit memory bar, without backing storage. It is disabled by +default and can be enabled using the membar=3D property. This can +be used to test whenever guests handles pci bars of a specific (possibly +quite large) size correctly. diff --git a/hw/misc/pci-testdev.c b/hw/misc/pci-testdev.c index 32041f535f..af4d678ee4 100644 --- a/hw/misc/pci-testdev.c +++ b/hw/misc/pci-testdev.c @@ -85,6 +85,9 @@ typedef struct PCITestDevState { MemoryRegion portio; IOTest *tests; int current; + + size_t membar_size; + MemoryRegion membar; } PCITestDevState; =20 #define TYPE_PCI_TEST_DEV "pci-testdev" @@ -253,6 +256,15 @@ static void pci_testdev_realize(PCIDevice *pci_dev, Er= ror **errp) pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->portio); =20 + if (d->membar_size) { + memory_region_init(&d->membar, OBJECT(d), "membar", d->membar_size= ); + pci_register_bar(pci_dev, 2, + PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_PREFETCH | + PCI_BASE_ADDRESS_MEM_TYPE_64, + &d->membar); + } + d->current =3D -1; d->tests =3D g_malloc0(IOTEST_MAX * sizeof *d->tests); for (i =3D 0; i < IOTEST_MAX; ++i) { @@ -305,6 +317,11 @@ static void qdev_pci_testdev_reset(DeviceState *dev) pci_testdev_reset(d); } =20 +static Property pci_testdev_properties[] =3D { + DEFINE_PROP_SIZE("membar", PCITestDevState, membar_size, 0), + DEFINE_PROP_END_OF_LIST(), +}; + static void pci_testdev_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -319,6 +336,7 @@ static void pci_testdev_class_init(ObjectClass *klass, = void *data) dc->desc =3D "PCI Test Device"; set_bit(DEVICE_CATEGORY_MISC, dc->categories); dc->reset =3D qdev_pci_testdev_reset; + dc->props =3D pci_testdev_properties; } =20 static const TypeInfo pci_testdev_info =3D { --=20 2.9.3