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v2: use "unsigned int" instead of "uint". thanks -- PMM The following changes since commit 506e4a00de01e0b29fa83db5cbbc3d154253b4ea: Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.1-20180925' into staging (2018-09-25 13:30:45 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180925-1 for you to fetch changes up to 060a65df056a5d6ca3a6a91e7bf150ca1fbccddf: target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode (2018-09-25 15:13:24 +0100) ---------------------------------------------------------------- target-arm queue: * target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs * hw/arm/exynos4210: fix Exynos4210 UART support * hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodes * arm: Add BBC micro:bit machine * aspeed/i2c: Fix interrupt handling bugs * hw/arm/smmu-common: Fix the name of the iommu memory regions * hw/arm/smmuv3: fix eventq recording and IRQ triggerring * hw/intc/arm_gic: Document QEMU interface * hw/intc/arm_gic: Drop GIC_BASE_IRQ macro * hw/net/pcnet-pci: Convert away from old_mmio accessors * hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements * aspeed/timer: fix compile breakage with clang 3.4.2 * hw/arm/aspeed: change the FMC flash model of the AST2500 evb * hw/arm/aspeed: Minor code cleanups * target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode ---------------------------------------------------------------- Bartlomiej Zolnierkiewicz (1): hw/arm/exynos4210: fix Exynos4210 UART support Cédric Le Goater (5): aspeed/i2c: interrupts should be cleared by software only aspeed/timer: fix compile breakage with clang 3.4.2 hw/arm/aspeed: change the FMC flash model of the AST2500 evb hw/arm/aspeed: Add an Aspeed machine class aspeed/smc: fix some alignment issues Eric Auger (2): hw/arm/smmu-common: Fix the name of the iommu memory regions hw/arm/smmuv3: fix eventq recording and IRQ triggerring Guenter Roeck (2): aspeed/i2c: Handle receive command in separate function aspeed/i2c: Fix receive done interrupt handling Joel Stanley (3): MAINTAINERS: Add NRF51 entry arm: Add Nordic Semiconductor nRF51 SoC arm: Add BBC micro:bit machine Peter Maydell (6): hw/intc/arm_gic: Document QEMU interface hw/intc/arm_gic: Drop GIC_BASE_IRQ macro hw/net/pcnet-pci: Convert away from old_mmio accessors hw/net/pcnet-pci: Unify pcnet_ioport_read/write and pcnet_mmio_read/write hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode Richard Henderson (1): target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs Shannon Zhao (1): hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodes hw/arm/Makefile.objs | 1 + hw/arm/smmuv3-internal.h | 26 ++--- hw/intc/gic_internal.h | 2 - include/hw/arm/aspeed.h | 46 +++++++++ include/hw/arm/nrf51_soc.h | 41 ++++++++ include/hw/intc/arm_gic.h | 43 ++++++++ include/hw/timer/aspeed_timer.h | 3 +- hw/arm/aspeed.c | 212 +++++++++++++--------------------------- hw/arm/exynos4210.c | 8 +- hw/arm/microbit.c | 67 +++++++++++++ hw/arm/nrf51_soc.c | 133 +++++++++++++++++++++++++ hw/arm/smmu-common.c | 6 +- hw/arm/smmuv3.c | 2 +- hw/arm/virt-acpi-build.c | 10 +- hw/i2c/aspeed_i2c.c | 63 ++++++++---- hw/intc/arm_gic.c | 31 +++--- hw/intc/arm_gic_common.c | 1 - hw/net/pcnet-pci.c | 98 ++----------------- hw/ssi/aspeed_smc.c | 8 +- hw/timer/aspeed_timer.c | 1 - hw/timer/cmsdk-apb-dualtimer.c | 2 + target/arm/cpu.c | 14 ++- target/arm/helper.c | 45 +++++---- MAINTAINERS | 8 ++ default-configs/arm-softmmu.mak | 1 + hw/net/trace-events | 6 -- 26 files changed, 542 insertions(+), 336 deletions(-) create mode 100644 include/hw/arm/aspeed.h create mode 100644 include/hw/arm/nrf51_soc.h create mode 100644 hw/arm/microbit.c create mode 100644 hw/arm/nrf51_soc.c
v3->v4: Windows headers define an INT type which clashed with an enum value name in arm_gicv3_its.c... The following changes since commit eae587e8e3694b1aceab23239493fb4c7e1a80f5: Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-09-13' into staging (2021-09-13 11:00:30 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210913-3 for you to fetch changes up to 28e987a7e7edaa3ca7feeac65edca26145df8814: hw/arm/mps2.c: Mark internal-only I2C buses as 'full' (2021-09-13 21:01:08 +0100) ---------------------------------------------------------------- target-arm queue: * mark MPS2/MPS3 board-internal i2c buses as 'full' so that command line user-created devices are not plugged into them * Take an exception if PSTATE.IL is set * Support an emulated ITS in the virt board * Add support for kudo-bmc board * Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM * cadence_uart: Fix clock handling issues that prevented u-boot from running ---------------------------------------------------------------- Bin Meng (6): hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase hw/char: cadence_uart: Disable transmit when input clock is disabled hw/char: cadence_uart: Move clock/reset check to uart_can_receive() hw/char: cadence_uart: Convert to memop_with_attrs() ops hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}() hw/char: cadence_uart: Log a guest error when device is unclocked or in reset Chris Rauer (1): hw/arm: Add support for kudo-bmc board. Marc Zyngier (1): hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM Peter Maydell (5): target/arm: Take an exception if PSTATE.IL is set qdev: Support marking individual buses as 'full' hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full' hw/arm/mps2.c: Mark internal-only I2C buses as 'full' Richard Henderson (1): target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn Shashi Mallela (9): hw/intc: GICv3 ITS initial framework hw/intc: GICv3 ITS register definitions added hw/intc: GICv3 ITS command queue framework hw/intc: GICv3 ITS Command processing hw/intc: GICv3 ITS Feature enablement hw/intc: GICv3 redistributor ITS processing tests/data/acpi/virt: Add IORT files for ITS hw/arm/virt: add ITS support in virt GIC tests/data/acpi/virt: Update IORT files for ITS docs/system/arm/nuvoton.rst | 1 + hw/intc/gicv3_internal.h | 188 ++++- include/hw/arm/virt.h | 2 + include/hw/intc/arm_gicv3_common.h | 13 + include/hw/intc/arm_gicv3_its_common.h | 32 +- include/hw/qdev-core.h | 24 + target/arm/cpu.h | 1 + target/arm/kvm_arm.h | 4 +- target/arm/syndrome.h | 5 + target/arm/translate.h | 2 + hw/arm/mps2-tz.c | 92 ++- hw/arm/mps2.c | 12 +- hw/arm/npcm7xx_boards.c | 34 + hw/arm/virt.c | 29 +- hw/char/cadence_uart.c | 61 +- hw/intc/arm_gicv3.c | 14 + hw/intc/arm_gicv3_common.c | 13 + hw/intc/arm_gicv3_cpuif.c | 7 +- hw/intc/arm_gicv3_dist.c | 5 +- hw/intc/arm_gicv3_its.c | 1322 ++++++++++++++++++++++++++++++++ hw/intc/arm_gicv3_its_common.c | 7 +- hw/intc/arm_gicv3_its_kvm.c | 2 +- hw/intc/arm_gicv3_redist.c | 153 +++- hw/misc/zynq_slcr.c | 31 +- softmmu/qdev-monitor.c | 7 +- target/arm/helper-a64.c | 1 + target/arm/helper.c | 8 + target/arm/kvm.c | 7 +- target/arm/translate-a64.c | 255 +++--- target/arm/translate.c | 21 + hw/intc/meson.build | 1 + tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes 35 files changed, 2144 insertions(+), 210 deletions(-) create mode 100644 hw/intc/arm_gicv3_its.c create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb