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From: Peter Maydell <peter.maydell@linaro.org>
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Subject: [Qemu-devel] [PULL 05/21] arm: Add Nordic Semiconductor nRF51 SoC
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From: Joel Stanley <joel@jms.id.au>
The nRF51 is a Cortex-M0 microcontroller with an on-board radio module,
plus other common ARM SoC peripherals.
http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
This defines a basic model of the CPU and memory, with no peripherals
implemented at this stage.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-id: 20180831220920.27113-3-joel@jms.id.au
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: wrapped a few long lines]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/Makefile.objs | 1 +
include/hw/arm/nrf51_soc.h | 41 ++++++++++
hw/arm/nrf51_soc.c | 133 ++++++++++++++++++++++++++++++++
default-configs/arm-softmmu.mak | 1 +
4 files changed, 176 insertions(+)
create mode 100644 include/hw/arm/nrf51_soc.h
create mode 100644 hw/arm/nrf51_soc.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 2902f47b4c4..ae4e20373b9 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -37,3 +37,4 @@ obj-$(CONFIG_IOTKIT) +=3D iotkit.o
obj-$(CONFIG_FSL_IMX7) +=3D fsl-imx7.o mcimx7d-sabre.o
obj-$(CONFIG_ARM_SMMUV3) +=3D smmu-common.o smmuv3.o
obj-$(CONFIG_FSL_IMX6UL) +=3D fsl-imx6ul.o mcimx6ul-evk.o
+obj-$(CONFIG_NRF51_SOC) +=3D nrf51_soc.o
diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h
new file mode 100644
index 00000000000..f4e092b554e
--- /dev/null
+++ b/include/hw/arm/nrf51_soc.h
@@ -0,0 +1,41 @@
+/*
+ * Nordic Semiconductor nRF51 SoC
+ *
+ * Copyright 2018 Joel Stanley <joel@jms.id.au>
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#ifndef NRF51_SOC_H
+#define NRF51_SOC_H
+
+#include "hw/sysbus.h"
+#include "hw/arm/armv7m.h"
+
+#define TYPE_NRF51_SOC "nrf51-soc"
+#define NRF51_SOC(obj) \
+ OBJECT_CHECK(NRF51State, (obj), TYPE_NRF51_SOC)
+
+typedef struct NRF51State {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ ARMv7MState cpu;
+
+ MemoryRegion iomem;
+ MemoryRegion sram;
+ MemoryRegion flash;
+
+ uint32_t sram_size;
+ uint32_t flash_size;
+
+ MemoryRegion *board_memory;
+
+ MemoryRegion container;
+
+} NRF51State;
+
+#endif
+
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
new file mode 100644
index 00000000000..1a59ef45525
--- /dev/null
+++ b/hw/arm/nrf51_soc.c
@@ -0,0 +1,133 @@
+/*
+ * Nordic Semiconductor nRF51 SoC
+ * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
+ *
+ * Copyright 2018 Joel Stanley <joel@jms.id.au>
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "hw/arm/arm.h"
+#include "hw/sysbus.h"
+#include "hw/boards.h"
+#include "hw/devices.h"
+#include "hw/misc/unimp.h"
+#include "exec/address-spaces.h"
+#include "sysemu/sysemu.h"
+#include "qemu/log.h"
+#include "cpu.h"
+
+#include "hw/arm/nrf51_soc.h"
+
+#define IOMEM_BASE 0x40000000
+#define IOMEM_SIZE 0x20000000
+
+#define FICR_BASE 0x10000000
+#define FICR_SIZE 0x000000fc
+
+#define FLASH_BASE 0x00000000
+#define SRAM_BASE 0x20000000
+
+#define PRIVATE_BASE 0xF0000000
+#define PRIVATE_SIZE 0x10000000
+
+/*
+ * The size and base is for the NRF51822 part. If other parts
+ * are supported in the future, add a sub-class of NRF51SoC for
+ * the specific variants
+ */
+#define NRF51822_FLASH_SIZE (256 * 1024)
+#define NRF51822_SRAM_SIZE (16 * 1024)
+
+static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
+{
+ NRF51State *s =3D NRF51_SOC(dev_soc);
+ Error *err =3D NULL;
+
+ if (!s->board_memory) {
+ error_setg(errp, "memory property was not set");
+ return;
+ }
+
+ object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memo=
ry",
+ &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ memory_region_add_subregion_overlap(&s->container, 0, s->board_memory,=
-1);
+
+ memory_region_init_rom(&s->flash, OBJECT(s), "nrf51.flash", s->flash_s=
ize,
+ &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash);
+
+ memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &er=
r);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram);
+
+ create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE);
+ create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE);
+ create_unimplemented_device("nrf51_soc.private",
+ PRIVATE_BASE, PRIVATE_SIZE);
+}
+
+static void nrf51_soc_init(Object *obj)
+{
+ NRF51State *s =3D NRF51_SOC(obj);
+
+ memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
+
+ sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->=
cpu),
+ TYPE_ARMV7M);
+ qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
+ ARM_CPU_TYPE_NAME("cortex-m0"));
+ qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
+}
+
+static Property nrf51_soc_properties[] =3D {
+ DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGIO=
N,
+ MemoryRegion *),
+ DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_S=
IZE),
+ DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size,
+ NRF51822_FLASH_SIZE),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void nrf51_soc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+
+ dc->realize =3D nrf51_soc_realize;
+ dc->props =3D nrf51_soc_properties;
+}
+
+static const TypeInfo nrf51_soc_info =3D {
+ .name =3D TYPE_NRF51_SOC,
+ .parent =3D TYPE_SYS_BUS_DEVICE,
+ .instance_size =3D sizeof(NRF51State),
+ .instance_init =3D nrf51_soc_init,
+ .class_init =3D nrf51_soc_class_init,
+};
+
+static void nrf51_soc_types(void)
+{
+ type_register_static(&nrf51_soc_info);
+}
+type_init(nrf51_soc_types)
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.=
mak
index 0483d548d96..2420491aacd 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -101,6 +101,7 @@ CONFIG_STM32F2XX_SYSCFG=3Dy
CONFIG_STM32F2XX_ADC=3Dy
CONFIG_STM32F2XX_SPI=3Dy
CONFIG_STM32F205_SOC=3Dy
+CONFIG_NRF51_SOC=3Dy
=20
CONFIG_CMSDK_APB_TIMER=3Dy
CONFIG_CMSDK_APB_DUALTIMER=3Dy
--=20
2.19.0