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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Tue, 25 Sep 2018 14:41:44 +0100
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Subject: [Qemu-devel] [PULL 21/21] target/arm: Start AArch32 CPUs with EL2
but not EL3 in Hyp mode
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The ARMv8 architecture defines that an AArch32 CPU starts
in SVC mode, unless EL2 is the highest available EL, in
which case it starts in Hyp mode. (In ARMv7 a CPU with EL2
but not EL3 was not a valid configuration, but we don't
specifically reject this if the user asks for one.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Message-id: 20180823135047.16525-1-peter.maydell@linaro.org
---
target/arm/cpu.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 258ba6dcaad..b5e61cc1775 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -199,8 +199,18 @@ static void arm_cpu_reset(CPUState *s)
env->cp15.c15_cpar =3D 1;
}
#else
- /* SVC mode with interrupts disabled. */
- env->uncached_cpsr =3D ARM_CPU_MODE_SVC;
+
+ /*
+ * If the highest available EL is EL2, AArch32 will start in Hyp
+ * mode; otherwise it starts in SVC. Note that if we start in
+ * AArch64 then these values in the uncached_cpsr will be ignored.
+ */
+ if (arm_feature(env, ARM_FEATURE_EL2) &&
+ !arm_feature(env, ARM_FEATURE_EL3)) {
+ env->uncached_cpsr =3D ARM_CPU_MODE_HYP;
+ } else {
+ env->uncached_cpsr =3D ARM_CPU_MODE_SVC;
+ }
env->daif =3D PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
=20
if (arm_feature(env, ARM_FEATURE_M)) {
--=20
2.19.0