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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Tue, 25 Sep 2018 14:41:41 +0100
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Subject: [Qemu-devel] [PULL 18/21] hw/arm/aspeed: change the FMC flash model
of the AST2500 evb
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From: C=C3=A9dric Le Goater <clg@kaod.org>
The AST2500 evb is shipped with a W25Q256 which has a non volatile bit
to make the chip operate in 4 Byte address mode at power up. This
should be an interesting feature to model as it will exercise a bit
more the SMC controllers and MMIO execution at boot time.
Signed-off-by: C=C3=A9dric Le Goater <clg@kaod.org>
Message-id: 20180921161939.822-3-clg@kaod.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/aspeed.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index bb9590f1aed..f2d64e45511 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -105,7 +105,7 @@ static const AspeedBoardConfig aspeed_boards[] =3D {
[AST2500_EVB] =3D {
.soc_name =3D "ast2500-a1",
.hw_strap1 =3D AST2500_EVB_HW_STRAP1,
- .fmc_model =3D "n25q256a",
+ .fmc_model =3D "w25q256",
.spi_model =3D "mx25l25635e",
.num_cs =3D 1,
.i2c_init =3D ast2500_evb_i2c_init,
--=20
2.19.0