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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Tue, 25 Sep 2018 14:41:38 +0100
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Subject: [Qemu-devel] [PULL 15/21] hw/net/pcnet-pci: Unify
pcnet_ioport_read/write and pcnet_mmio_read/write
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The only difference between our implementation of the pcnet ioport
accessors and the mmio accessors is that the former check BCR_DWIO to
see what access widths are permitted for addresses in the aprom range
(0x0..0xf). In fact our failure to do this in the mmio accessors
is a bug (one which was fixed for the ioport accessors in
commit 7ba79741970 in 2011).
The data sheet for the Am79C970A does not describe the DWIO
bit as only applying for I/O space mapped I/O resources and
not memory mapped I/O resources, and our MMIO accessors already
honour DWIO for accesses in the 0x10..0x1f range (since the
pcnet_ioport_{read,write}{w,l} functions check it).
The data sheet for the later but compatible Am79C976 is clearer:
it states specifically "DWIO mode applies to both I/O- and
memory-mapped acceses." This seems to be reasonable evidence
in favour of interpretating the Am79C970A spec as being the same.
(NB: Linux's pcnet driver only supports I/O accesses, so the
MMIO access part of this device is probably untested anyway.)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/net/pcnet-pci.c | 67 ++-------------------------------------------
hw/net/trace-events | 2 --
2 files changed, 2 insertions(+), 67 deletions(-)
diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c
index 248fb3ba299..7c738557830 100644
--- a/hw/net/pcnet-pci.c
+++ b/hw/net/pcnet-pci.c
@@ -139,69 +139,6 @@ static const MemoryRegionOps pcnet_io_ops =3D {
.endianness =3D DEVICE_LITTLE_ENDIAN,
};
=20
-/*
- * TODO: should MMIO accesses to the addresses corresponding to the
- * APROM also honour the BCR_DWIO() setting? If so, then these functions
- * and pcnet_ioport_write/pcnet_ioport_read could be merged.
- * If not, then should pcnet_ioport_{read,write}{w,l} really check
- * BCR_DWIO() for MMIO writes ?
- */
-static void pcnet_mmio_write(void *opaque, hwaddr addr, uint64_t value,
- unsigned size)
-{
- PCNetState *d =3D opaque;
-
- trace_pcnet_mmio_write(opaque, addr, size, val);
-
- if (addr < 0x10) {
- if (size =3D=3D 1) {
- pcnet_aprom_writeb(d, addr, data);
- } else if ((addr & 1) =3D=3D 0 && size =3D=3D 2) {
- pcnet_aprom_writeb(d, addr, data & 0xff);
- pcnet_aprom_writeb(d, addr + 1, data >> 8);
- } else if ((addr & 3) =3D=3D 0 && size =3D=3D 4) {
- pcnet_aprom_writeb(d, addr, data & 0xff);
- pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff);
- pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff);
- pcnet_aprom_writeb(d, addr + 3, data >> 24);
- }
- } else {
- if (size =3D=3D 2) {
- pcnet_ioport_writew(d, addr, data);
- } else if (size =3D=3D 4) {
- pcnet_ioport_writel(d, addr, data);
- }
- }
-}
-
-static uint64_t pcnet_mmio_read(void *opque, hwaddr addr, unsigned size)
-{
- PCNetState *d =3D opaque;
-
- trace_pcnet_ioport_read(opaque, addr, size);
-
- if (addr < 0x10) {
- if (size =3D=3D 1) {
- return pcnet_aprom_readb(d, addr);
- } else if ((addr & 1) =3D=3D 0 && size =3D=3D 2) {
- return pcnet_aprom_readb(d, addr) |
- (pcnet_aprom_readb(d, addr + 1) << 8);
- } else if ((addr & 3) =3D=3D 0 && size =3D=3D 4) {
- return pcnet_aprom_readb(d, addr) |
- (pcnet_aprom_readb(d, addr + 1) << 8) |
- (pcnet_aprom_readb(d, addr + 2) << 16) |
- (pcnet_aprom_readb(d, addr + 3) << 24);
- }
- } else {
- if (size =3D=3D 2) {
- return pcnet_ioport_readw(d, addr);
- } else if (size =3D=3D 4) {
- return pcnet_ioport_readl(d, addr);
- }
- }
- return ((uint64_t)1 << (size * 8)) - 1;
-}
-
static const VMStateDescription vmstate_pci_pcnet =3D {
.name =3D "pcnet",
.version_id =3D 3,
@@ -216,8 +153,8 @@ static const VMStateDescription vmstate_pci_pcnet =3D {
/* PCI interface */
=20
static const MemoryRegionOps pcnet_mmio_ops =3D {
- .read =3D pcnet_mmio_read,
- .write =3D pcnet_mmio_write,
+ .read =3D pcnet_ioport_read,
+ .write =3D pcnet_ioport_write,
.valid.min_access_size =3D 1,
.valid.max_access_size =3D 4,
.impl.min_access_size =3D 1,
diff --git a/hw/net/trace-events b/hw/net/trace-events
index 5cd0ad50ce2..c1dea4b1562 100644
--- a/hw/net/trace-events
+++ b/hw/net/trace-events
@@ -61,8 +61,6 @@ pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t =
val) "opaque=3D%p addr=3D0x
pcnet_aprom_readb(void *opaque, uint32_t addr, uint32_t val) "opaque=3D%p =
addr=3D0x%08x val=3D0x%02x"
pcnet_ioport_read(void *opaque, uint64_t addr, unsigned size) "opaque=3D%p=
addr=3D0x%"PRIx64" size=3D%d"
pcnet_ioport_write(void *opaque, uint64_t addr, uint64_t data, unsigned si=
ze) "opaque=3D%p addr=3D0x%"PRIx64" data=3D0x%"PRIx64" size=3D%d"
-pcnet_mmio_write(void *opaque, uint64_t addr, uint32_t val, unsigned size)=
"opaque=3D%p addr=3D0x%"PRIx64" val=3D0x%x size=3D%d"
-pcnet_mmio_read(void *opaque, uint64_t addr, unsigned size) "opaque=3D%p a=
ddr=3D0x%"PRIx64" size=3D%d"
=20
# hw/net/net_rx_pkt.c
net_rx_pkt_parsed(bool ip4, bool ip6, bool udp, bool tcp, size_t l3o, size=
_t l4o, size_t l5o) "RX packet parsed: ip4: %d, ip6: %d, udp: %d, tcp: %d, =
l3 offset: %zu, l4 offset: %zu, l5 offset: %zu"
--=20
2.19.0