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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id e30-v6sm2924783ljb.86.2018.09.17.11.08.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Sep 2018 11:08:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=nAgEouU318l+aMLedpL5TGA/OrWoq71HSSeJEkM6HB0=; b=QlVe90igASSkJiI4U6rHw+mAD2iU0wnqEgwBHEy0jNPyNgWyb99hOcyIz8B/qJkMCD 05RKlTszpSXtuy/PwrILwXv8bLtU07SVT2FJUUA3ScXH1H7LR1jSE4Uc89yO5eZEx0Q7 hv4TMV5gv6hqLrU10QqtIscPqw17lkS/tzklqETLvOYmp50FCbTOzoiDsbIZ2UzQrNZr 4cejhtBAzOIqEycwbtZ/dWHq8RZmpe5OtZAJerHUJLnvk5VXdGaa6+2SuqkEHGpnfqvc DTS3zDlZpol55G4wlTsOPDnmvAcZfkUb214b9/cNEA9MaBty2SsIVJDcg8MgFc6VLupd 76pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=nAgEouU318l+aMLedpL5TGA/OrWoq71HSSeJEkM6HB0=; b=Oi7M4A1huneOOTWpFqh/4d2va1MF6VG05iPXvr6M3+If+qkia6ByQ3/RdCArBAcIvc 4uE1MHSPZy7FwYW4ftbEGCsgvq1anzoNBCph27vRgarvDalUAoQcN0JvmDSTaIBBkOIL QCHejVjSrSoO4xnHxwSH7v6EmkZErFykDfJjaZGr26cm+X6IXJSsM80tgNYpf6nMzzPb R1shTbdjzDosHrgGSKnIEETzRmpbRl9/0E7Zs9FTyoN6YiniwGAOaf8Bqk8z0zpI7/Pn kw1tQ44P38puetY6Jsjdvnbj5f4fkfi+UIA/JXv6plLtHkywC8T6Qmc8kpQNN7mIak7z jKhA== X-Gm-Message-State: APzg51BI5Yk5myXOK1Blpo+ZO1ot6bzOWLwabkaUAhZ2143Zo+eZ3J1X dfwtp49wRSnoemNpch4s1zUQ7vlK X-Google-Smtp-Source: ANB0Vdbg92XtePFl2UdrJ4zhjcT4cDNSB9DpW6V+LkFd6DVP6AiHGg+YpcGh5AyfNJaOtkKkmd2oRg== X-Received: by 2002:a19:cd8c:: with SMTP id d134-v6mr16743300lfg.41.1537207690511; Mon, 17 Sep 2018 11:08:10 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Mon, 17 Sep 2018 11:07:57 -0700 Message-Id: <20180917180757.21318-1-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::12f Subject: [Qemu-devel] [PATCH v3] target/xtensa: convert to do_transaction_failed X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Max Filippov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Max Filippov --- Changes v2->v3: - change get_pte return type to bool as suggested by Peter; Changes v1->v2: - change ldl_phys to address_space_ldl in get_pte and check transaction for success; target/xtensa/cpu.c | 2 +- target/xtensa/cpu.h | 7 ++++--- target/xtensa/helper.c | 30 +++++++++++++++++++++++------- target/xtensa/op_helper.c | 12 +++++++----- 4 files changed, 35 insertions(+), 16 deletions(-) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 590813d4f7b9..a54dbe42602d 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -186,7 +186,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) #else cc->do_unaligned_access =3D xtensa_cpu_do_unaligned_access; cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; - cc->do_unassigned_access =3D xtensa_cpu_do_unassigned_access; + cc->do_transaction_failed =3D xtensa_cpu_do_transaction_failed; #endif cc->debug_excp_handler =3D xtensa_breakpoint_handler; cc->disas_set_info =3D xtensa_cpu_disas_set_info; diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 7472cf3ca32a..1362772617ea 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -497,9 +497,10 @@ int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr ad= dress, int rw, int size, int mmu_idx); void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); -void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr, - bool is_write, bool is_exec, int opaq= ue, - unsigned size); +void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, + unsigned size, MMUAccessType access_= type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t reta= ddr); void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f74636f67854..4fceb4424aa3 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -566,7 +566,7 @@ static bool is_access_granted(unsigned access, int is_w= rite) } } =20 -static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte); +static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte); =20 static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, uint32_t vaddr, int is_write, int mmu_idx, @@ -584,7 +584,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, b= ool update_tlb, int ret =3D xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring); =20 if ((ret =3D=3D INST_TLB_MISS_CAUSE || ret =3D=3D LOAD_STORE_TLB_MISS_= CAUSE) && - may_lookup_pt && get_pte(env, vaddr, &pte) =3D=3D 0) { + may_lookup_pt && get_pte(env, vaddr, &pte)) { ring =3D (pte >> 4) & 0x3; wi =3D 0; split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei); @@ -631,7 +631,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, b= ool update_tlb, return 0; } =20 -static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) +static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) { CPUState *cs =3D CPU(xtensa_env_get_cpu(env)); uint32_t paddr; @@ -642,13 +642,29 @@ static int get_pte(CPUXtensaState *env, uint32_t vadd= r, uint32_t *pte) int ret =3D get_physical_addr_mmu(env, false, pt_vaddr, 0, 0, &paddr, &page_size, &access, false); =20 - qemu_log_mask(CPU_LOG_MMU, "%s: trying autorefill(%08x) -> %08x\n", - __func__, vaddr, ret ? ~0 : paddr); + if (ret =3D=3D 0) { + qemu_log_mask(CPU_LOG_MMU, + "%s: autorefill(%08x): PTE va =3D %08x, pa =3D %08x\= n", + __func__, vaddr, pt_vaddr, paddr); + } else { + qemu_log_mask(CPU_LOG_MMU, + "%s: autorefill(%08x): PTE va =3D %08x, failed (%d)\= n", + __func__, vaddr, pt_vaddr, ret); + } =20 if (ret =3D=3D 0) { - *pte =3D ldl_phys(cs->as, paddr); + MemTxResult result; + + *pte =3D address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED, + &result); + if (result !=3D MEMTX_OK) { + qemu_log_mask(CPU_LOG_MMU, + "%s: couldn't load PTE: transaction failed (%u)\= n", + __func__, (unsigned)result); + ret =3D 1; + } } - return ret; + return ret =3D=3D 0; } =20 static int get_physical_addr_region(CPUXtensaState *env, diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index d4c942d87980..06fe346f02ff 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -78,18 +78,20 @@ void tlb_fill(CPUState *cs, target_ulong vaddr, int siz= e, } } =20 -void xtensa_cpu_do_unassigned_access(CPUState *cs, hwaddr addr, - bool is_write, bool is_exec, int opaq= ue, - unsigned size) +void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, + unsigned size, MMUAccessType access_= type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t reta= ddr) { XtensaCPU *cpu =3D XTENSA_CPU(cs); CPUXtensaState *env =3D &cpu->env; =20 + cpu_restore_state(cs, retaddr, true); HELPER(exception_cause_vaddr)(env, env->pc, - is_exec ? + access_type =3D=3D MMU_INST_FETCH ? INSTR_PIF_ADDR_ERROR_CAUSE : LOAD_STORE_PIF_ADDR_ERROR_CAUSE, - is_exec ? addr : cs->mem_io_vaddr); + addr); } =20 static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) --=20 2.11.0