From nobody Wed Nov 5 20:11:29 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1537202021909997.0717947433432; Mon, 17 Sep 2018 09:33:41 -0700 (PDT) Received: from localhost ([::1]:36439 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g1wSy-0007iQ-Kc for importer@patchew.org; Mon, 17 Sep 2018 12:33:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40784) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g1wQd-0006F0-MA for qemu-devel@nongnu.org; Mon, 17 Sep 2018 12:31:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g1wQa-0001pR-75 for qemu-devel@nongnu.org; Mon, 17 Sep 2018 12:31:15 -0400 Received: from wout2-smtp.messagingengine.com ([64.147.123.25]:40579) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g1wQZ-0001nr-TS for qemu-devel@nongnu.org; Mon, 17 Sep 2018 12:31:12 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id C84B4514; Mon, 17 Sep 2018 12:31:06 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Mon, 17 Sep 2018 12:31:07 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 0B955E49CB; Mon, 17 Sep 2018 12:31:06 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=mesmtp; bh=vbZfZvB5enU7Rt KO0PXcZWYkk9A0VxabXx08KxB0lBs=; b=O3hAEQiYjwGcJ3xcu6ikJmhYpyTkBj TLp2RJZuF4S6Q1M44K433AwNHN/eAVQ5gB5wcKBQTL8RqM/hdkdpghKw+ED1+kqx 9KwqvG2IgaPYw5dZqABas79iY9PO3ioIM6ukzdDixqXMVgBdsqIbkLM7rnTdp1BF y8cS+yaSfSOuI= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=vbZfZvB5enU7RtKO0PXcZWYkk9A0VxabXx08KxB0lBs=; b=pMonHU+Q GdcNZjIpct283f5S3GOexPSsKJ25T66XNHT1jlfhhParPCCAxw1I9hYyC2qZ+qoL xQZVNZq7ei6WEpq7N4Str+1rL8SHLlWirJh/O+uOtN+whCDPWFTbQQpU7wuQqv3Z FoajhQeHxYnTvh45tUNvJZag2OxEgIL2oSXFCUzPw2ZK2hqUs29gtEc3LUp9e5Pj uXJ4UjHf04Ss6eMxD693ymxe7J0Zngl6ZuYMNk+NIv03FDvPEcs4iSlg6FqizELP V2ZcRdZ9P5SIn0BifU1aOWVXnb4KAs4Ec5wDPkvQN00uJgyzwTb26QSzU4onsI04 OkXeIXpP/UBTyg== X-ME-Proxy: X-ME-Sender: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Mon, 17 Sep 2018 12:30:35 -0400 Message-Id: <20180917163103.6113-8-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180917163103.6113-1-cota@braap.org> References: <20180917163103.6113-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 64.147.123.25 Subject: [Qemu-devel] [PATCH 07/35] target/alpha: access cpu->interrupt_request with atomics X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Paolo Bonzini Cc: Richard Henderson Signed-off-by: Paolo Bonzini Signed-off-by: Emilio G. Cota --- target/alpha/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index b08078e7fc..76001e66f1 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -42,10 +42,10 @@ static bool alpha_cpu_has_work(CPUState *cs) assume that if a CPU really wants to stay asleep, it will mask interrupts at the chipset level, which will prevent these bits from being set in the first place. */ - return cs->interrupt_request & (CPU_INTERRUPT_HARD - | CPU_INTERRUPT_TIMER - | CPU_INTERRUPT_SMP - | CPU_INTERRUPT_MCHK); + return atomic_read(&cs->interrupt_request) & (CPU_INTERRUPT_HARD + | CPU_INTERRUPT_TIMER + | CPU_INTERRUPT_SMP + | CPU_INTERRUPT_MCHK); } =20 static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) --=20 2.17.1