From nobody Wed Nov 5 20:16:10 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1537202455862494.6849493698335; Mon, 17 Sep 2018 09:40:55 -0700 (PDT) Received: from localhost ([::1]:36480 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g1wZy-0005ev-IQ for importer@patchew.org; Mon, 17 Sep 2018 12:40:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40946) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1g1wQh-0006Ib-RC for qemu-devel@nongnu.org; Mon, 17 Sep 2018 12:31:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1g1wQg-0001zI-9m for qemu-devel@nongnu.org; Mon, 17 Sep 2018 12:31:19 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:50525) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1g1wQb-0001rC-Mg; Mon, 17 Sep 2018 12:31:13 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 5FB7D21C08; Mon, 17 Sep 2018 12:31:13 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Mon, 17 Sep 2018 12:31:13 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id D5505E49EC; Mon, 17 Sep 2018 12:31:12 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=mesmtp; bh=hP3BNXg9fUYlH9 mrXcVwqXX3Jxaadm+2okW5WxgMl58=; b=t0k38ogxl8BXY3m2tREnHvB25lJWSx g7zD1EqEH2hkI/NKCUwrakORm783Rps0I45j5wns6R49X48sUQJ3hZbond7xAnLf qL07P//HmjW35o6l33xGtF5FyBMvVCeLHeQRqTwnKb/qr81BtmQDfXTNX0+zt1zC uh9twUe6DNil0= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=hP3BNXg9fUYlH9mrXcVwqXX3Jxaadm+2okW5WxgMl58=; b=SmlTA+CQ rAfSw6VLqvmOKbJubMF5E4CKJC//QJYrNksBWjBGbfw9zjAxmenfbkPFcOOiHxX+ /O5wOFm9kQ0QPvVIatmAW1+M4brmrmYOQ5SzHLr5TMEhhTYa55atqT1ofm22nuvV cTDkf/r4TG++b/N63ZDp9atkxQWtxa3FxNAAMtOcxeVWKhxrrZ6qRIvJq8+tr2Sg RaOK4TkdyyFcb+LH5eiwXtYH3wVkmF1Qxk2gvnQPIofvpzK3NuhkGhkg0UzTiXaL TSoy27LT51X8/8erpZr7jlajZamvoOEP0FPeNeE4KHqvA17kPazQaGtNz7Su9hDx eb/ii1gbjnRQXg== X-ME-Proxy: X-ME-Sender: From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Mon, 17 Sep 2018 12:31:03 -0400 Message-Id: <20180917163103.6113-36-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180917163103.6113-1-cota@braap.org> References: <20180917163103.6113-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH 35/35] exec: push BQL down to cpu->cpu_exec_interrupt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Cornelia Huck , kvm@vger.kernel.org, David Hildenbrand , James Hogan , Anthony Green , Mark Cave-Ayland , "Edgar E. Iglesias" , Guan Xuetao , Marek Vasut , Alexander Graf , Christian Borntraeger , Richard Henderson , Artyom Tarasenko , Eduardo Habkost , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, Stafford Horne , David Gibson , Chris Wulff , Peter Crosthwaite , Marcelo Tosatti , Laurent Vivier , Michael Walle , qemu-ppc@nongnu.org, Aleksandar Markovic , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Paolo Bonzini Most interrupt requests do not need to take the BQL, and in fact most architectures do not need it at all. Push the BQL acquisition down to target code. Cc: Aleksandar Markovic Cc: Alexander Graf Cc: Anthony Green Cc: Artyom Tarasenko Cc: Aurelien Jarno Cc: Christian Borntraeger Cc: Chris Wulff Cc: Cornelia Huck Cc: David Gibson Cc: David Hildenbrand Cc: "Edgar E. Iglesias" Cc: Eduardo Habkost Cc: Guan Xuetao Cc: James Hogan Cc: kvm@vger.kernel.org Cc: Laurent Vivier Cc: Marcelo Tosatti Cc: Marek Vasut Cc: Mark Cave-Ayland Cc: Michael Walle Cc: Peter Crosthwaite Cc: Peter Maydell Cc: qemu-arm@nongnu.org Cc: qemu-ppc@nongnu.org Cc: qemu-s390x@nongnu.org Cc: Richard Henderson Cc: Stafford Horne Signed-off-by: Paolo Bonzini Signed-off-by: Emilio G. Cota --- docs/devel/multi-thread-tcg.txt | 7 +++++-- accel/tcg/cpu-exec.c | 9 +-------- target/arm/cpu.c | 15 ++++++++++++++- target/i386/seg_helper.c | 3 +++ target/ppc/excp_helper.c | 2 ++ target/s390x/excp_helper.c | 3 +++ 6 files changed, 28 insertions(+), 11 deletions(-) diff --git a/docs/devel/multi-thread-tcg.txt b/docs/devel/multi-thread-tcg.= txt index 782bebc28b..422de4736b 100644 --- a/docs/devel/multi-thread-tcg.txt +++ b/docs/devel/multi-thread-tcg.txt @@ -231,8 +231,11 @@ BQL. Currently ARM targets serialise all ARM_CP_IO reg= ister accesses and also defer the reset/startup of vCPUs to the vCPU context by way of async_run_on_cpu(). =20 -Updates to interrupt state are also protected by the BQL as they can -often be cross vCPU. +The CPUClass callbacks cpu_exec_interrupt and do_interrupt are invoked +without BQL protection. Accesses to the interrupt controller from +the vCPU thread, for example while processing CPU_INTERRUPT_HARD, must +either call qemu_mutex_lock_iothread/qemu_mutex_unlock_iothread or use +a separate mutex. =20 Memory Consistency =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index b649e3d772..f5e08e79d1 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -524,7 +524,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, =20 if (unlikely(atomic_read(&cpu->interrupt_request))) { int interrupt_request; - qemu_mutex_lock_iothread(); + interrupt_request =3D atomic_read(&cpu->interrupt_request); if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) { /* Mask out external interrupts for this step. */ @@ -533,7 +533,6 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, if (interrupt_request & CPU_INTERRUPT_DEBUG) { cpu_reset_interrupt(cpu, CPU_INTERRUPT_DEBUG); cpu->exception_index =3D EXCP_DEBUG; - qemu_mutex_unlock_iothread(); return true; } if (replay_mode =3D=3D REPLAY_MODE_PLAY && !replay_has_interrupt()= ) { @@ -543,7 +542,6 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, cpu_reset_interrupt(cpu, CPU_INTERRUPT_HALT); cpu->halted =3D 1; cpu->exception_index =3D EXCP_HLT; - qemu_mutex_unlock_iothread(); return true; } #if defined(TARGET_I386) @@ -554,14 +552,12 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0, 0); do_cpu_init(x86_cpu); cpu->exception_index =3D EXCP_HALTED; - qemu_mutex_unlock_iothread(); return true; } #else else if (interrupt_request & CPU_INTERRUPT_RESET) { replay_interrupt(); cpu_reset(cpu); - qemu_mutex_unlock_iothread(); return true; } #endif @@ -585,9 +581,6 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, the program flow was changed */ *last_tb =3D NULL; } - - /* If we exit via cpu_loop_exit/longjmp it is reset in cpu_exec */ - qemu_mutex_unlock_iothread(); } =20 /* Finally, check if we need to exit to the main loop. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e2c492efdf..246ea13d8f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -347,7 +347,8 @@ static void arm_cpu_reset(CPUState *s) hw_watchpoint_update_all(cpu); } =20 -bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +/* call with the BQL held */ +static bool arm_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_requ= est) { CPUClass *cc =3D CPU_GET_CLASS(cs); CPUARMState *env =3D cs->env_ptr; @@ -401,6 +402,16 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) return ret; } =20 +bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + bool ret; + + qemu_mutex_lock_iothread(); + ret =3D arm_cpu_exec_interrupt_locked(cs, interrupt_request); + qemu_mutex_unlock_iothread(); + return ret; +} + #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { @@ -409,6 +420,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, in= t interrupt_request) CPUARMState *env =3D &cpu->env; bool ret =3D false; =20 + qemu_mutex_lock_iothread(); /* ARMv7-M interrupt masking works differently than -A or -R. * There is no FIQ/IRQ distinction. Instead of I and F bits * masking FIQ and IRQ interrupts, an exception is taken only @@ -422,6 +434,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, in= t interrupt_request) cc->do_interrupt(cs); ret =3D true; } + qemu_mutex_unlock_iothread(); return ret; } #endif diff --git a/target/i386/seg_helper.c b/target/i386/seg_helper.c index 0dd85329db..2fdfbd3c37 100644 --- a/target/i386/seg_helper.c +++ b/target/i386/seg_helper.c @@ -19,6 +19,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/main-loop.h" #include "cpu.h" #include "qemu/log.h" #include "exec/helper-proto.h" @@ -1324,7 +1325,9 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) #if !defined(CONFIG_USER_ONLY) if (interrupt_request & CPU_INTERRUPT_POLL) { cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL); + qemu_mutex_lock_iothread(); apic_poll_irq(cpu->apic_state); + qemu_mutex_unlock_iothread(); /* Don't process multiple interrupt requests in a single call. This is required to make icount-driven execution deterministic.= */ return true; diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 8b2cc48cad..57acba2a80 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -885,10 +885,12 @@ bool ppc_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) CPUPPCState *env =3D &cpu->env; =20 if (interrupt_request & CPU_INTERRUPT_HARD) { + qemu_mutex_lock_iothread(); ppc_hw_interrupt(env); if (env->pending_interrupts =3D=3D 0) { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); } + qemu_mutex_unlock_iothread(); return true; } return false; diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index 931c0103c8..f2a93abf01 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -480,10 +480,13 @@ bool s390_cpu_exec_interrupt(CPUState *cs, int interr= upt_request) the parent EXECUTE insn. */ return false; } + qemu_mutex_lock_iothread(); if (s390_cpu_has_int(cpu)) { s390_cpu_do_interrupt(cs); + qemu_mutex_unlock_iothread(); return true; } + qemu_mutex_unlock_iothread(); if (env->psw.mask & PSW_MASK_WAIT) { /* Woken up because of a floating interrupt but it has already * been delivered. Go back to sleep. */ --=20 2.17.1