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Cota" To: qemu-devel@nongnu.org Date: Mon, 17 Sep 2018 12:30:46 -0400 Message-Id: <20180917163103.6113-19-cota@braap.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180917163103.6113-1-cota@braap.org> References: <20180917163103.6113-1-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH 18/35] target/mips: access cpu->interrupt_request with atomics X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Aleksandar Markovic , Aurelien Jarno , James Hogan Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Paolo Bonzini Cc: Aurelien Jarno Cc: Aleksandar Markovic Cc: James Hogan Signed-off-by: Paolo Bonzini Signed-off-by: Emilio G. Cota --- target/mips/cpu.c | 7 ++++--- target/mips/kvm.c | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 497706b669..8d07696825 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -56,11 +56,12 @@ static bool mips_cpu_has_work(CPUState *cs) MIPSCPU *cpu =3D MIPS_CPU(cs); CPUMIPSState *env =3D &cpu->env; bool has_work =3D false; + uint32_t interrupt_request =3D atomic_read(&cs->interrupt_request); =20 /* Prior to MIPS Release 6 it is implementation dependent if non-enabl= ed interrupts wake-up the CPU, however most of the implementations only check for interrupts that can be taken. */ - if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && + if ((interrupt_request & CPU_INTERRUPT_HARD) && cpu_mips_hw_interrupts_pending(env)) { if (cpu_mips_hw_interrupts_enabled(env) || (env->insn_flags & ISA_MIPS32R6)) { @@ -72,7 +73,7 @@ static bool mips_cpu_has_work(CPUState *cs) if (env->CP0_Config3 & (1 << CP0C3_MT)) { /* The QEMU model will issue an _WAKE request whenever the CPUs should be woken up. */ - if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { + if (interrupt_request & CPU_INTERRUPT_WAKE) { has_work =3D true; } =20 @@ -82,7 +83,7 @@ static bool mips_cpu_has_work(CPUState *cs) } /* MIPS Release 6 has the ability to halt the CPU. */ if (env->CP0_Config5 & (1 << CP0C5_VP)) { - if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { + if (interrupt_request & CPU_INTERRUPT_WAKE) { has_work =3D true; } if (!mips_vp_active(env)) { diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 8e72850962..71fe3501a8 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -135,7 +135,7 @@ void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) =20 qemu_mutex_lock_iothread(); =20 - if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && + if ((atomic_read(&cs->interrupt_request) & CPU_INTERRUPT_HARD) && cpu_mips_io_interrupts_pending(cpu)) { intr.cpu =3D -1; intr.irq =3D 2; --=20 2.17.1